MipsDSPInstrInfo.td revision 451b0e7b8a56457114d8989ac836163d82a1cf5e
1//===- MipsDSPInstrInfo.td - DSP ASE instructions -*- tablegen ------------*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes Mips DSP ASE instructions. 11// 12//===----------------------------------------------------------------------===// 13 14// ImmLeaf 15def immZExt2 : ImmLeaf<i32, [{return isUInt<2>(Imm);}]>; 16def immZExt3 : ImmLeaf<i32, [{return isUInt<3>(Imm);}]>; 17def immZExt4 : ImmLeaf<i32, [{return isUInt<4>(Imm);}]>; 18def immZExt8 : ImmLeaf<i32, [{return isUInt<8>(Imm);}]>; 19def immZExt10 : ImmLeaf<i32, [{return isUInt<10>(Imm);}]>; 20def immSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}]>; 21 22// Mips-specific dsp nodes 23def SDT_MipsExtr : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>]>; 24def SDT_MipsShilo : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 25def SDT_MipsDPA : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>]>; 26 27class MipsDSPBase<string Opc, SDTypeProfile Prof> : 28 SDNode<!strconcat("MipsISD::", Opc), Prof, 29 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>; 30 31class MipsDSPSideEffectBase<string Opc, SDTypeProfile Prof> : 32 SDNode<!strconcat("MipsISD::", Opc), Prof, 33 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPSideEffect]>; 34 35def MipsEXTP : MipsDSPSideEffectBase<"EXTP", SDT_MipsExtr>; 36def MipsEXTPDP : MipsDSPSideEffectBase<"EXTPDP", SDT_MipsExtr>; 37def MipsEXTR_S_H : MipsDSPSideEffectBase<"EXTR_S_H", SDT_MipsExtr>; 38def MipsEXTR_W : MipsDSPSideEffectBase<"EXTR_W", SDT_MipsExtr>; 39def MipsEXTR_R_W : MipsDSPSideEffectBase<"EXTR_R_W", SDT_MipsExtr>; 40def MipsEXTR_RS_W : MipsDSPSideEffectBase<"EXTR_RS_W", SDT_MipsExtr>; 41 42def MipsSHILO : MipsDSPBase<"SHILO", SDT_MipsShilo>; 43def MipsMTHLIP : MipsDSPBase<"MTHLIP", SDT_MipsShilo>; 44 45def MipsMULSAQ_S_W_PH : MipsDSPSideEffectBase<"MULSAQ_S_W_PH", SDT_MipsDPA>; 46def MipsMAQ_S_W_PHL : MipsDSPSideEffectBase<"MAQ_S_W_PHL", SDT_MipsDPA>; 47def MipsMAQ_S_W_PHR : MipsDSPSideEffectBase<"MAQ_S_W_PHR", SDT_MipsDPA>; 48def MipsMAQ_SA_W_PHL : MipsDSPSideEffectBase<"MAQ_SA_W_PHL", SDT_MipsDPA>; 49def MipsMAQ_SA_W_PHR : MipsDSPSideEffectBase<"MAQ_SA_W_PHR", SDT_MipsDPA>; 50 51def MipsDPAU_H_QBL : MipsDSPBase<"DPAU_H_QBL", SDT_MipsDPA>; 52def MipsDPAU_H_QBR : MipsDSPBase<"DPAU_H_QBR", SDT_MipsDPA>; 53def MipsDPSU_H_QBL : MipsDSPBase<"DPSU_H_QBL", SDT_MipsDPA>; 54def MipsDPSU_H_QBR : MipsDSPBase<"DPSU_H_QBR", SDT_MipsDPA>; 55def MipsDPAQ_S_W_PH : MipsDSPSideEffectBase<"DPAQ_S_W_PH", SDT_MipsDPA>; 56def MipsDPSQ_S_W_PH : MipsDSPSideEffectBase<"DPSQ_S_W_PH", SDT_MipsDPA>; 57def MipsDPAQ_SA_L_W : MipsDSPSideEffectBase<"DPAQ_SA_L_W", SDT_MipsDPA>; 58def MipsDPSQ_SA_L_W : MipsDSPSideEffectBase<"DPSQ_SA_L_W", SDT_MipsDPA>; 59 60def MipsDPA_W_PH : MipsDSPBase<"DPA_W_PH", SDT_MipsDPA>; 61def MipsDPS_W_PH : MipsDSPBase<"DPS_W_PH", SDT_MipsDPA>; 62def MipsDPAQX_S_W_PH : MipsDSPSideEffectBase<"DPAQX_S_W_PH", SDT_MipsDPA>; 63def MipsDPAQX_SA_W_PH : MipsDSPSideEffectBase<"DPAQX_SA_W_PH", SDT_MipsDPA>; 64def MipsDPAX_W_PH : MipsDSPBase<"DPAX_W_PH", SDT_MipsDPA>; 65def MipsDPSX_W_PH : MipsDSPBase<"DPSX_W_PH", SDT_MipsDPA>; 66def MipsDPSQX_S_W_PH : MipsDSPSideEffectBase<"DPSQX_S_W_PH", SDT_MipsDPA>; 67def MipsDPSQX_SA_W_PH : MipsDSPSideEffectBase<"DPSQX_SA_W_PH", SDT_MipsDPA>; 68def MipsMULSA_W_PH : MipsDSPBase<"MULSA_W_PH", SDT_MipsDPA>; 69 70def MipsMULT : MipsDSPBase<"MULT", SDT_MipsDPA>; 71def MipsMULTU : MipsDSPBase<"MULTU", SDT_MipsDPA>; 72def MipsMADD_DSP : MipsDSPBase<"MADD_DSP", SDT_MipsDPA>; 73def MipsMADDU_DSP : MipsDSPBase<"MADDU_DSP", SDT_MipsDPA>; 74def MipsMSUB_DSP : MipsDSPBase<"MSUB_DSP", SDT_MipsDPA>; 75def MipsMSUBU_DSP : MipsDSPBase<"MSUBU_DSP", SDT_MipsDPA>; 76 77// Flags. 78class IsCommutable { 79 bit isCommutable = 1; 80} 81 82class UseAC { 83 list<Register> Uses = [AC0]; 84} 85 86class UseDSPCtrl { 87 list<Register> Uses = [DSPCtrl]; 88} 89 90class ClearDefs { 91 list<Register> Defs = []; 92} 93 94// Instruction encoding. 95class ADDU_QB_ENC : ADDU_QB_FMT<0b00000>; 96class ADDU_S_QB_ENC : ADDU_QB_FMT<0b00100>; 97class SUBU_QB_ENC : ADDU_QB_FMT<0b00001>; 98class SUBU_S_QB_ENC : ADDU_QB_FMT<0b00101>; 99class ADDQ_PH_ENC : ADDU_QB_FMT<0b01010>; 100class ADDQ_S_PH_ENC : ADDU_QB_FMT<0b01110>; 101class SUBQ_PH_ENC : ADDU_QB_FMT<0b01011>; 102class SUBQ_S_PH_ENC : ADDU_QB_FMT<0b01111>; 103class ADDQ_S_W_ENC : ADDU_QB_FMT<0b10110>; 104class SUBQ_S_W_ENC : ADDU_QB_FMT<0b10111>; 105class ADDSC_ENC : ADDU_QB_FMT<0b10000>; 106class ADDWC_ENC : ADDU_QB_FMT<0b10001>; 107class MODSUB_ENC : ADDU_QB_FMT<0b10010>; 108class RADDU_W_QB_ENC : RADDU_W_QB_FMT<0b10100>; 109class PRECRQ_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01100>; 110class PRECRQ_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10100>; 111class PRECRQ_RS_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10101>; 112class PRECRQU_S_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01111>; 113class MULEU_S_PH_QBL_ENC : ADDU_QB_FMT<0b00110>; 114class MULEU_S_PH_QBR_ENC : ADDU_QB_FMT<0b00111>; 115class MULEQ_S_W_PHL_ENC : ADDU_QB_FMT<0b11100>; 116class MULEQ_S_W_PHR_ENC : ADDU_QB_FMT<0b11101>; 117class MULQ_RS_PH_ENC : ADDU_QB_FMT<0b11111>; 118class MULSAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00110>; 119class MAQ_S_W_PHL_ENC : DPA_W_PH_FMT<0b10100>; 120class MAQ_S_W_PHR_ENC : DPA_W_PH_FMT<0b10110>; 121class MAQ_SA_W_PHL_ENC : DPA_W_PH_FMT<0b10000>; 122class MAQ_SA_W_PHR_ENC : DPA_W_PH_FMT<0b10010>; 123class DPAU_H_QBL_ENC : DPA_W_PH_FMT<0b00011>; 124class DPAU_H_QBR_ENC : DPA_W_PH_FMT<0b00111>; 125class DPSU_H_QBL_ENC : DPA_W_PH_FMT<0b01011>; 126class DPSU_H_QBR_ENC : DPA_W_PH_FMT<0b01111>; 127class DPAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00100>; 128class DPSQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00101>; 129class DPAQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01100>; 130class DPSQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01101>; 131class MULT_DSP_ENC : MULT_FMT<0b000000, 0b011000>; 132class MULTU_DSP_ENC : MULT_FMT<0b000000, 0b011001>; 133class MADD_DSP_ENC : MULT_FMT<0b011100, 0b000000>; 134class MADDU_DSP_ENC : MULT_FMT<0b011100, 0b000001>; 135class MSUB_DSP_ENC : MULT_FMT<0b011100, 0b000100>; 136class MSUBU_DSP_ENC : MULT_FMT<0b011100, 0b000101>; 137class CMPU_EQ_QB_ENC : CMP_EQ_QB_R2_FMT<0b00000>; 138class CMPU_LT_QB_ENC : CMP_EQ_QB_R2_FMT<0b00001>; 139class CMPU_LE_QB_ENC : CMP_EQ_QB_R2_FMT<0b00010>; 140class CMPGU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b00100>; 141class CMPGU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b00101>; 142class CMPGU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b00110>; 143class CMP_EQ_PH_ENC : CMP_EQ_QB_R2_FMT<0b01000>; 144class CMP_LT_PH_ENC : CMP_EQ_QB_R2_FMT<0b01001>; 145class CMP_LE_PH_ENC : CMP_EQ_QB_R2_FMT<0b01010>; 146class PACKRL_PH_ENC : CMP_EQ_QB_R3_FMT<0b01110>; 147class PICK_QB_ENC : CMP_EQ_QB_R3_FMT<0b00011>; 148class PICK_PH_ENC : CMP_EQ_QB_R3_FMT<0b01011>; 149class BPOSGE32_ENC : BPOSGE32_FMT<0b11100>; 150 151class EXTP_ENC : EXTR_W_TY1_FMT<0b00010>; 152class EXTPV_ENC : EXTR_W_TY1_FMT<0b00011>; 153class EXTPDP_ENC : EXTR_W_TY1_FMT<0b01010>; 154class EXTPDPV_ENC : EXTR_W_TY1_FMT<0b01011>; 155class EXTR_W_ENC : EXTR_W_TY1_FMT<0b00000>; 156class EXTRV_W_ENC : EXTR_W_TY1_FMT<0b00001>; 157class EXTR_R_W_ENC : EXTR_W_TY1_FMT<0b00100>; 158class EXTRV_R_W_ENC : EXTR_W_TY1_FMT<0b00101>; 159class EXTR_RS_W_ENC : EXTR_W_TY1_FMT<0b00110>; 160class EXTRV_RS_W_ENC : EXTR_W_TY1_FMT<0b00111>; 161class EXTR_S_H_ENC : EXTR_W_TY1_FMT<0b01110>; 162class EXTRV_S_H_ENC : EXTR_W_TY1_FMT<0b01111>; 163class SHILO_ENC : SHILO_R1_FMT<0b11010>; 164class SHILOV_ENC : SHILO_R2_FMT<0b11011>; 165class MTHLIP_ENC : SHILO_R2_FMT<0b11111>; 166 167class ADDU_PH_ENC : ADDU_QB_FMT<0b01000>; 168class ADDU_S_PH_ENC : ADDU_QB_FMT<0b01100>; 169class SUBU_PH_ENC : ADDU_QB_FMT<0b01001>; 170class SUBU_S_PH_ENC : ADDU_QB_FMT<0b01101>; 171class CMPGDU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b11000>; 172class CMPGDU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b11001>; 173class CMPGDU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b11010>; 174class MULQ_S_PH_ENC : ADDU_QB_FMT<0b11110>; 175class DPA_W_PH_ENC : DPA_W_PH_FMT<0b00000>; 176class DPS_W_PH_ENC : DPA_W_PH_FMT<0b00001>; 177class DPAQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11000>; 178class DPAQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11010>; 179class DPAX_W_PH_ENC : DPA_W_PH_FMT<0b01000>; 180class DPSX_W_PH_ENC : DPA_W_PH_FMT<0b01001>; 181class DPSQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11001>; 182class DPSQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11011>; 183class MULSA_W_PH_ENC : DPA_W_PH_FMT<0b00010>; 184class PRECR_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01101>; 185class PRECR_SRA_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11110>; 186class PRECR_SRA_R_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11111>; 187 188// Instruction desc. 189class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 190 InstrItinClass itin, RegisterClass RCD, 191 RegisterClass RCS, RegisterClass RCT = RCS> { 192 dag OutOperandList = (outs RCD:$rd); 193 dag InOperandList = (ins RCS:$rs, RCT:$rt); 194 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt"); 195 list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs, RCT:$rt))]; 196 InstrItinClass Itinerary = itin; 197 list<Register> Defs = [DSPCtrl]; 198} 199 200class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 201 InstrItinClass itin, RegisterClass RCD, 202 RegisterClass RCS = RCD> { 203 dag OutOperandList = (outs RCD:$rd); 204 dag InOperandList = (ins RCS:$rs); 205 string AsmString = !strconcat(instr_asm, "\t$rd, $rs"); 206 list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs))]; 207 InstrItinClass Itinerary = itin; 208 list<Register> Defs = [DSPCtrl]; 209} 210 211class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 212 InstrItinClass itin, RegisterClass RCS, 213 RegisterClass RCT = RCS> { 214 dag OutOperandList = (outs); 215 dag InOperandList = (ins RCS:$rs, RCT:$rt); 216 string AsmString = !strconcat(instr_asm, "\t$rs, $rt"); 217 list<dag> Pattern = [(OpNode RCS:$rs, RCT:$rt)]; 218 InstrItinClass Itinerary = itin; 219 list<Register> Defs = [DSPCtrl]; 220} 221 222class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 223 InstrItinClass itin, RegisterClass RCD, 224 RegisterClass RCS, RegisterClass RCT = RCS> { 225 dag OutOperandList = (outs RCD:$rd); 226 dag InOperandList = (ins RCS:$rs, RCT:$rt); 227 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt"); 228 list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs, RCT:$rt))]; 229 InstrItinClass Itinerary = itin; 230 list<Register> Defs = [DSPCtrl]; 231} 232 233class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 234 InstrItinClass itin, RegisterClass RCT, 235 RegisterClass RCS = RCT> { 236 dag OutOperandList = (outs RCT:$rt); 237 dag InOperandList = (ins RCS:$rs, shamt:$sa, RCS:$src); 238 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa"); 239 list<dag> Pattern = [(set RCT:$rt, (OpNode RCS:$src, RCS:$rs, immZExt5:$sa))]; 240 InstrItinClass Itinerary = itin; 241 list<Register> Defs = [DSPCtrl]; 242 string Constraints = "$src = $rt"; 243} 244 245class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 246 InstrItinClass itin> { 247 dag OutOperandList = (outs CPURegs:$rt); 248 dag InOperandList = (ins ACRegs:$ac, CPURegs:$shift_rs); 249 string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs"); 250 InstrItinClass Itinerary = itin; 251 list<Register> Defs = [DSPCtrl]; 252} 253 254class EXTR_W_TY1_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 255 InstrItinClass itin> { 256 dag OutOperandList = (outs CPURegs:$rt); 257 dag InOperandList = (ins ACRegs:$ac, uimm16:$shift_rs); 258 string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs"); 259 InstrItinClass Itinerary = itin; 260 list<Register> Defs = [DSPCtrl]; 261} 262 263class SHILO_R1_PSEUDO_BASE<SDPatternOperator OpNode, InstrItinClass itin, 264 Instruction realinst> : 265 PseudoDSP<(outs), (ins simm16:$shift), [(OpNode immSExt6:$shift)]>, 266 PseudoInstExpansion<(realinst AC0, simm16:$shift)> { 267 list<Register> Defs = [DSPCtrl, AC0]; 268 list<Register> Uses = [AC0]; 269 InstrItinClass Itinerary = itin; 270} 271 272class SHILO_R1_DESC_BASE<string instr_asm> { 273 dag OutOperandList = (outs ACRegs:$ac); 274 dag InOperandList = (ins simm16:$shift); 275 string AsmString = !strconcat(instr_asm, "\t$ac, $shift"); 276} 277 278class SHILO_R2_PSEUDO_BASE<SDPatternOperator OpNode, InstrItinClass itin, 279 Instruction realinst> : 280 PseudoDSP<(outs), (ins CPURegs:$rs), [(OpNode CPURegs:$rs)]>, 281 PseudoInstExpansion<(realinst AC0, CPURegs:$rs)> { 282 list<Register> Defs = [DSPCtrl, AC0]; 283 list<Register> Uses = [AC0]; 284 InstrItinClass Itinerary = itin; 285} 286 287class SHILO_R2_DESC_BASE<string instr_asm> { 288 dag OutOperandList = (outs ACRegs:$ac); 289 dag InOperandList = (ins CPURegs:$rs); 290 string AsmString = !strconcat(instr_asm, "\t$ac, $rs"); 291} 292 293class MTHLIP_DESC_BASE<string instr_asm> { 294 dag OutOperandList = (outs ACRegs:$ac); 295 dag InOperandList = (ins CPURegs:$rs); 296 string AsmString = !strconcat(instr_asm, "\t$rs, $ac"); 297} 298 299class DPA_W_PH_PSEUDO_BASE<SDPatternOperator OpNode, InstrItinClass itin, 300 Instruction realinst> : 301 PseudoDSP<(outs), (ins CPURegs:$rs, CPURegs:$rt), 302 [(OpNode CPURegs:$rs, CPURegs:$rt)]>, 303 PseudoInstExpansion<(realinst AC0, CPURegs:$rs, CPURegs:$rt)> { 304 list<Register> Defs = [DSPCtrl, AC0]; 305 list<Register> Uses = [AC0]; 306 InstrItinClass Itinerary = itin; 307} 308 309class DPA_W_PH_DESC_BASE<string instr_asm> { 310 dag OutOperandList = (outs ACRegs:$ac); 311 dag InOperandList = (ins CPURegs:$rs, CPURegs:$rt); 312 string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt"); 313} 314 315class MULT_PSEUDO_BASE<SDPatternOperator OpNode, InstrItinClass itin, 316 Instruction realinst> : 317 PseudoDSP<(outs), (ins CPURegs:$rs, CPURegs:$rt), 318 [(OpNode CPURegs:$rs, CPURegs:$rt)]>, 319 PseudoInstExpansion<(realinst AC0, CPURegs:$rs, CPURegs:$rt)> { 320 list<Register> Defs = [DSPCtrl, AC0]; 321 InstrItinClass Itinerary = itin; 322} 323 324class MULT_DESC_BASE<string instr_asm> { 325 dag OutOperandList = (outs ACRegs:$ac); 326 dag InOperandList = (ins CPURegs:$rs, CPURegs:$rt); 327 string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt"); 328} 329 330class BPOSGE32_PSEUDO_DESC_BASE<SDPatternOperator OpNode, InstrItinClass itin> : 331 MipsPseudo<(outs CPURegs:$dst), (ins), "", [(set CPURegs:$dst, (OpNode))]> { 332 list<Register> Uses = [DSPCtrl]; 333 bit usesCustomInserter = 1; 334} 335 336class BPOSGE32_DESC_BASE<string instr_asm, InstrItinClass itin> { 337 dag OutOperandList = (outs); 338 dag InOperandList = (ins brtarget:$offset); 339 string AsmString = !strconcat(instr_asm, "\t$offset"); 340 InstrItinClass Itinerary = itin; 341 list<Register> Uses = [DSPCtrl]; 342 bit isBranch = 1; 343 bit isTerminator = 1; 344 bit hasDelaySlot = 1; 345} 346 347//===----------------------------------------------------------------------===// 348// MIPS DSP Rev 1 349//===----------------------------------------------------------------------===// 350 351// Addition/subtraction 352class ADDU_QB_DESC : ADDU_QB_DESC_BASE<"addu.qb", int_mips_addu_qb, NoItinerary, 353 DSPRegs, DSPRegs>, IsCommutable; 354 355class ADDU_S_QB_DESC : ADDU_QB_DESC_BASE<"addu_s.qb", int_mips_addu_s_qb, 356 NoItinerary, DSPRegs, DSPRegs>, 357 IsCommutable; 358 359class SUBU_QB_DESC : ADDU_QB_DESC_BASE<"subu.qb", int_mips_subu_qb, NoItinerary, 360 DSPRegs, DSPRegs>; 361 362class SUBU_S_QB_DESC : ADDU_QB_DESC_BASE<"subu_s.qb", int_mips_subu_s_qb, 363 NoItinerary, DSPRegs, DSPRegs>; 364 365class ADDQ_PH_DESC : ADDU_QB_DESC_BASE<"addq.ph", int_mips_addq_ph, NoItinerary, 366 DSPRegs, DSPRegs>, IsCommutable; 367 368class ADDQ_S_PH_DESC : ADDU_QB_DESC_BASE<"addq_s.ph", int_mips_addq_s_ph, 369 NoItinerary, DSPRegs, DSPRegs>, 370 IsCommutable; 371 372class SUBQ_PH_DESC : ADDU_QB_DESC_BASE<"subq.ph", int_mips_subq_ph, NoItinerary, 373 DSPRegs, DSPRegs>; 374 375class SUBQ_S_PH_DESC : ADDU_QB_DESC_BASE<"subq_s.ph", int_mips_subq_s_ph, 376 NoItinerary, DSPRegs, DSPRegs>; 377 378class ADDQ_S_W_DESC : ADDU_QB_DESC_BASE<"addq_s.w", int_mips_addq_s_w, 379 NoItinerary, CPURegs, CPURegs>, 380 IsCommutable; 381 382class SUBQ_S_W_DESC : ADDU_QB_DESC_BASE<"subq_s.w", int_mips_subq_s_w, 383 NoItinerary, CPURegs, CPURegs>; 384 385class ADDSC_DESC : ADDU_QB_DESC_BASE<"addsc", int_mips_addsc, NoItinerary, 386 CPURegs, CPURegs>, IsCommutable; 387 388class ADDWC_DESC : ADDU_QB_DESC_BASE<"addwc", int_mips_addwc, NoItinerary, 389 CPURegs, CPURegs>, 390 IsCommutable, UseDSPCtrl; 391 392class MODSUB_DESC : ADDU_QB_DESC_BASE<"modsub", int_mips_modsub, NoItinerary, 393 CPURegs, CPURegs>, ClearDefs; 394 395class RADDU_W_QB_DESC : RADDU_W_QB_DESC_BASE<"raddu.w.qb", int_mips_raddu_w_qb, 396 NoItinerary, CPURegs, DSPRegs>, 397 ClearDefs; 398 399// Precision reduce/expand 400class PRECRQ_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.qb.ph", 401 int_mips_precrq_qb_ph, 402 NoItinerary, DSPRegs, DSPRegs>, 403 ClearDefs; 404 405class PRECRQ_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.ph.w", 406 int_mips_precrq_ph_w, 407 NoItinerary, DSPRegs, CPURegs>, 408 ClearDefs; 409 410class PRECRQ_RS_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq_rs.ph.w", 411 int_mips_precrq_rs_ph_w, 412 NoItinerary, DSPRegs, 413 CPURegs>; 414 415class PRECRQU_S_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrqu_s.qb.ph", 416 int_mips_precrqu_s_qb_ph, 417 NoItinerary, DSPRegs, 418 DSPRegs>; 419 420// Multiplication 421class MULEU_S_PH_QBL_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbl", 422 int_mips_muleu_s_ph_qbl, 423 NoItinerary, DSPRegs, DSPRegs>; 424 425class MULEU_S_PH_QBR_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbr", 426 int_mips_muleu_s_ph_qbr, 427 NoItinerary, DSPRegs, DSPRegs>; 428 429class MULEQ_S_W_PHL_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phl", 430 int_mips_muleq_s_w_phl, 431 NoItinerary, CPURegs, DSPRegs>, 432 IsCommutable; 433 434class MULEQ_S_W_PHR_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phr", 435 int_mips_muleq_s_w_phr, 436 NoItinerary, CPURegs, DSPRegs>, 437 IsCommutable; 438 439class MULQ_RS_PH_DESC : ADDU_QB_DESC_BASE<"mulq_rs.ph", int_mips_mulq_rs_ph, 440 NoItinerary, DSPRegs, DSPRegs>, 441 IsCommutable; 442 443class MULSAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsaq_s.w.ph">; 444 445class MAQ_S_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phl">; 446 447class MAQ_S_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phr">; 448 449class MAQ_SA_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phl">; 450 451class MAQ_SA_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phr">; 452 453// Dot product with accumulate/subtract 454class DPAU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbl">; 455 456class DPAU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbr">; 457 458class DPSU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbl">; 459 460class DPSU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbr">; 461 462class DPAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaq_s.w.ph">; 463 464class DPSQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsq_s.w.ph">; 465 466class DPAQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpaq_sa.l.w">; 467 468class DPSQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpsq_sa.l.w">; 469 470class MULT_DSP_DESC : MULT_DESC_BASE<"mult">; 471 472class MULTU_DSP_DESC : MULT_DESC_BASE<"multu">; 473 474class MADD_DSP_DESC : MULT_DESC_BASE<"madd">; 475 476class MADDU_DSP_DESC : MULT_DESC_BASE<"maddu">; 477 478class MSUB_DSP_DESC : MULT_DESC_BASE<"msub">; 479 480class MSUBU_DSP_DESC : MULT_DESC_BASE<"msubu">; 481 482// Comparison 483class CMPU_EQ_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.eq.qb", 484 int_mips_cmpu_eq_qb, NoItinerary, 485 DSPRegs>, IsCommutable; 486 487class CMPU_LT_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.lt.qb", 488 int_mips_cmpu_lt_qb, NoItinerary, 489 DSPRegs>, IsCommutable; 490 491class CMPU_LE_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.le.qb", 492 int_mips_cmpu_le_qb, NoItinerary, 493 DSPRegs>, IsCommutable; 494 495class CMPGU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.eq.qb", 496 int_mips_cmpgu_eq_qb, 497 NoItinerary, CPURegs, DSPRegs>, 498 IsCommutable; 499 500class CMPGU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.lt.qb", 501 int_mips_cmpgu_lt_qb, 502 NoItinerary, CPURegs, DSPRegs>, 503 IsCommutable; 504 505class CMPGU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.le.qb", 506 int_mips_cmpgu_le_qb, 507 NoItinerary, CPURegs, DSPRegs>, 508 IsCommutable; 509 510class CMP_EQ_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.eq.ph", int_mips_cmp_eq_ph, 511 NoItinerary, DSPRegs>, 512 IsCommutable; 513 514class CMP_LT_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.lt.ph", int_mips_cmp_lt_ph, 515 NoItinerary, DSPRegs>, 516 IsCommutable; 517 518class CMP_LE_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.le.ph", int_mips_cmp_le_ph, 519 NoItinerary, DSPRegs>, 520 IsCommutable; 521 522// Misc 523class PACKRL_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"packrl.ph", int_mips_packrl_ph, 524 NoItinerary, DSPRegs, DSPRegs>, 525 ClearDefs; 526 527class PICK_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.qb", int_mips_pick_qb, 528 NoItinerary, DSPRegs, DSPRegs>, 529 ClearDefs, UseDSPCtrl; 530 531class PICK_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.ph", int_mips_pick_ph, 532 NoItinerary, DSPRegs, DSPRegs>, 533 ClearDefs, UseDSPCtrl; 534 535class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", NoItinerary>; 536 537// Extr 538class EXTP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extp", MipsEXTP, NoItinerary>; 539 540class EXTPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpv", MipsEXTP, NoItinerary>; 541 542class EXTPDP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extpdp", MipsEXTPDP, NoItinerary>; 543 544class EXTPDPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpdpv", MipsEXTPDP, 545 NoItinerary>; 546 547class EXTR_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr.w", MipsEXTR_W, NoItinerary>; 548 549class EXTRV_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv.w", MipsEXTR_W, 550 NoItinerary>; 551 552class EXTR_R_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_r.w", MipsEXTR_R_W, 553 NoItinerary>; 554 555class EXTRV_R_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_r.w", MipsEXTR_R_W, 556 NoItinerary>; 557 558class EXTR_RS_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_rs.w", MipsEXTR_RS_W, 559 NoItinerary>; 560 561class EXTRV_RS_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_rs.w", MipsEXTR_RS_W, 562 NoItinerary>; 563 564class EXTR_S_H_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_s.h", MipsEXTR_S_H, 565 NoItinerary>; 566 567class EXTRV_S_H_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_s.h", MipsEXTR_S_H, 568 NoItinerary>; 569 570class SHILO_DESC : SHILO_R1_DESC_BASE<"shilo">; 571 572class SHILOV_DESC : SHILO_R2_DESC_BASE<"shilov">; 573 574class MTHLIP_DESC : MTHLIP_DESC_BASE<"mthlip">; 575 576//===----------------------------------------------------------------------===// 577// MIPS DSP Rev 2 578// Addition/subtraction 579class ADDU_PH_DESC : ADDU_QB_DESC_BASE<"addu.ph", int_mips_addu_ph, NoItinerary, 580 DSPRegs, DSPRegs>, IsCommutable; 581 582class ADDU_S_PH_DESC : ADDU_QB_DESC_BASE<"addu_s.ph", int_mips_addu_s_ph, 583 NoItinerary, DSPRegs, DSPRegs>, 584 IsCommutable; 585 586class SUBU_PH_DESC : ADDU_QB_DESC_BASE<"subu.ph", int_mips_subu_ph, NoItinerary, 587 DSPRegs, DSPRegs>; 588 589class SUBU_S_PH_DESC : ADDU_QB_DESC_BASE<"subu_s.ph", int_mips_subu_s_ph, 590 NoItinerary, DSPRegs, DSPRegs>; 591 592// Comparison 593class CMPGDU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.eq.qb", 594 int_mips_cmpgdu_eq_qb, 595 NoItinerary, CPURegs, DSPRegs>, 596 IsCommutable; 597 598class CMPGDU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.lt.qb", 599 int_mips_cmpgdu_lt_qb, 600 NoItinerary, CPURegs, DSPRegs>, 601 IsCommutable; 602 603class CMPGDU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.le.qb", 604 int_mips_cmpgdu_le_qb, 605 NoItinerary, CPURegs, DSPRegs>, 606 IsCommutable; 607 608// Multiplication 609class MULQ_S_PH_DESC : ADDU_QB_DESC_BASE<"mulq_s.ph", int_mips_mulq_s_ph, 610 NoItinerary, DSPRegs, DSPRegs>, 611 IsCommutable; 612 613// Dot product with accumulate/subtract 614class DPA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpa.w.ph">; 615 616class DPS_W_PH_DESC : DPA_W_PH_DESC_BASE<"dps.w.ph">; 617 618class DPAQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_s.w.ph">; 619 620class DPAQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_sa.w.ph">; 621 622class DPAX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpax.w.ph">; 623 624class DPSX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsx.w.ph">; 625 626class DPSQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_s.w.ph">; 627 628class DPSQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_sa.w.ph">; 629 630class MULSA_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsa.w.ph">; 631 632// Precision reduce/expand 633class PRECR_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precr.qb.ph", 634 int_mips_precr_qb_ph, 635 NoItinerary, DSPRegs, DSPRegs>; 636 637class PRECR_SRA_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra.ph.w", 638 int_mips_precr_sra_ph_w, 639 NoItinerary, DSPRegs, 640 CPURegs>, ClearDefs; 641 642class PRECR_SRA_R_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra_r.ph.w", 643 int_mips_precr_sra_r_ph_w, 644 NoItinerary, DSPRegs, 645 CPURegs>, ClearDefs; 646 647// Pseudos. 648def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32, NoItinerary>; 649 650// Instruction defs. 651// MIPS DSP Rev 1 652def ADDU_QB : ADDU_QB_ENC, ADDU_QB_DESC; 653def ADDU_S_QB : ADDU_S_QB_ENC, ADDU_S_QB_DESC; 654def SUBU_QB : SUBU_QB_ENC, SUBU_QB_DESC; 655def SUBU_S_QB : SUBU_S_QB_ENC, SUBU_S_QB_DESC; 656def ADDQ_PH : ADDQ_PH_ENC, ADDQ_PH_DESC; 657def ADDQ_S_PH : ADDQ_S_PH_ENC, ADDQ_S_PH_DESC; 658def SUBQ_PH : SUBQ_PH_ENC, SUBQ_PH_DESC; 659def SUBQ_S_PH : SUBQ_S_PH_ENC, SUBQ_S_PH_DESC; 660def ADDQ_S_W : ADDQ_S_W_ENC, ADDQ_S_W_DESC; 661def SUBQ_S_W : SUBQ_S_W_ENC, SUBQ_S_W_DESC; 662def ADDSC : ADDSC_ENC, ADDSC_DESC; 663def ADDWC : ADDWC_ENC, ADDWC_DESC; 664def MODSUB : MODSUB_ENC, MODSUB_DESC; 665def RADDU_W_QB : RADDU_W_QB_ENC, RADDU_W_QB_DESC; 666def PRECRQ_QB_PH : PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC; 667def PRECRQ_PH_W : PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC; 668def PRECRQ_RS_PH_W : PRECRQ_RS_PH_W_ENC, PRECRQ_RS_PH_W_DESC; 669def PRECRQU_S_QB_PH : PRECRQU_S_QB_PH_ENC, PRECRQU_S_QB_PH_DESC; 670def MULEU_S_PH_QBL : MULEU_S_PH_QBL_ENC, MULEU_S_PH_QBL_DESC; 671def MULEU_S_PH_QBR : MULEU_S_PH_QBR_ENC, MULEU_S_PH_QBR_DESC; 672def MULEQ_S_W_PHL : MULEQ_S_W_PHL_ENC, MULEQ_S_W_PHL_DESC; 673def MULEQ_S_W_PHR : MULEQ_S_W_PHR_ENC, MULEQ_S_W_PHR_DESC; 674def MULQ_RS_PH : MULQ_RS_PH_ENC, MULQ_RS_PH_DESC; 675def MULSAQ_S_W_PH : MULSAQ_S_W_PH_ENC, MULSAQ_S_W_PH_DESC; 676def MAQ_S_W_PHL : MAQ_S_W_PHL_ENC, MAQ_S_W_PHL_DESC; 677def MAQ_S_W_PHR : MAQ_S_W_PHR_ENC, MAQ_S_W_PHR_DESC; 678def MAQ_SA_W_PHL : MAQ_SA_W_PHL_ENC, MAQ_SA_W_PHL_DESC; 679def MAQ_SA_W_PHR : MAQ_SA_W_PHR_ENC, MAQ_SA_W_PHR_DESC; 680def DPAU_H_QBL : DPAU_H_QBL_ENC, DPAU_H_QBL_DESC; 681def DPAU_H_QBR : DPAU_H_QBR_ENC, DPAU_H_QBR_DESC; 682def DPSU_H_QBL : DPSU_H_QBL_ENC, DPSU_H_QBL_DESC; 683def DPSU_H_QBR : DPSU_H_QBR_ENC, DPSU_H_QBR_DESC; 684def DPAQ_S_W_PH : DPAQ_S_W_PH_ENC, DPAQ_S_W_PH_DESC; 685def DPSQ_S_W_PH : DPSQ_S_W_PH_ENC, DPSQ_S_W_PH_DESC; 686def DPAQ_SA_L_W : DPAQ_SA_L_W_ENC, DPAQ_SA_L_W_DESC; 687def DPSQ_SA_L_W : DPSQ_SA_L_W_ENC, DPSQ_SA_L_W_DESC; 688def MULT_DSP : MULT_DSP_ENC, MULT_DSP_DESC; 689def MULTU_DSP : MULTU_DSP_ENC, MULTU_DSP_DESC; 690def MADD_DSP : MADD_DSP_ENC, MADD_DSP_DESC; 691def MADDU_DSP : MADDU_DSP_ENC, MADDU_DSP_DESC; 692def MSUB_DSP : MSUB_DSP_ENC, MSUB_DSP_DESC; 693def MSUBU_DSP : MSUBU_DSP_ENC, MSUBU_DSP_DESC; 694def CMPU_EQ_QB : CMPU_EQ_QB_ENC, CMPU_EQ_QB_DESC; 695def CMPU_LT_QB : CMPU_LT_QB_ENC, CMPU_LT_QB_DESC; 696def CMPU_LE_QB : CMPU_LE_QB_ENC, CMPU_LE_QB_DESC; 697def CMPGU_EQ_QB : CMPGU_EQ_QB_ENC, CMPGU_EQ_QB_DESC; 698def CMPGU_LT_QB : CMPGU_LT_QB_ENC, CMPGU_LT_QB_DESC; 699def CMPGU_LE_QB : CMPGU_LE_QB_ENC, CMPGU_LE_QB_DESC; 700def CMP_EQ_PH : CMP_EQ_PH_ENC, CMP_EQ_PH_DESC; 701def CMP_LT_PH : CMP_LT_PH_ENC, CMP_LT_PH_DESC; 702def CMP_LE_PH : CMP_LE_PH_ENC, CMP_LE_PH_DESC; 703def PACKRL_PH : PACKRL_PH_ENC, PACKRL_PH_DESC; 704def PICK_QB : PICK_QB_ENC, PICK_QB_DESC; 705def PICK_PH : PICK_PH_ENC, PICK_PH_DESC; 706def BPOSGE32 : BPOSGE32_ENC, BPOSGE32_DESC; 707def EXTP : EXTP_ENC, EXTP_DESC; 708def EXTPV : EXTPV_ENC, EXTPV_DESC; 709def EXTPDP : EXTPDP_ENC, EXTPDP_DESC; 710def EXTPDPV : EXTPDPV_ENC, EXTPDPV_DESC; 711def EXTR_W : EXTR_W_ENC, EXTR_W_DESC; 712def EXTRV_W : EXTRV_W_ENC, EXTRV_W_DESC; 713def EXTR_R_W : EXTR_R_W_ENC, EXTR_R_W_DESC; 714def EXTRV_R_W : EXTRV_R_W_ENC, EXTRV_R_W_DESC; 715def EXTR_RS_W : EXTR_RS_W_ENC, EXTR_RS_W_DESC; 716def EXTRV_RS_W : EXTRV_RS_W_ENC, EXTRV_RS_W_DESC; 717def EXTR_S_H : EXTR_S_H_ENC, EXTR_S_H_DESC; 718def EXTRV_S_H : EXTRV_S_H_ENC, EXTRV_S_H_DESC; 719def SHILO : SHILO_ENC, SHILO_DESC; 720def SHILOV : SHILOV_ENC, SHILOV_DESC; 721def MTHLIP : MTHLIP_ENC, MTHLIP_DESC; 722 723// MIPS DSP Rev 2 724let Predicates = [HasDSPR2] in { 725 726def ADDU_PH : ADDU_PH_ENC, ADDU_PH_DESC; 727def ADDU_S_PH : ADDU_S_PH_ENC, ADDU_S_PH_DESC; 728def SUBU_PH : SUBU_PH_ENC, SUBU_PH_DESC; 729def SUBU_S_PH : SUBU_S_PH_ENC, SUBU_S_PH_DESC; 730def CMPGDU_EQ_QB : CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC; 731def CMPGDU_LT_QB : CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC; 732def CMPGDU_LE_QB : CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC; 733def MULQ_S_PH : MULQ_S_PH_ENC, MULQ_S_PH_DESC; 734def DPA_W_PH : DPA_W_PH_ENC, DPA_W_PH_DESC; 735def DPS_W_PH : DPS_W_PH_ENC, DPS_W_PH_DESC; 736def DPAQX_S_W_PH : DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC; 737def DPAQX_SA_W_PH : DPAQX_SA_W_PH_ENC, DPAQX_SA_W_PH_DESC; 738def DPAX_W_PH : DPAX_W_PH_ENC, DPAX_W_PH_DESC; 739def DPSX_W_PH : DPSX_W_PH_ENC, DPSX_W_PH_DESC; 740def DPSQX_S_W_PH : DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC; 741def DPSQX_SA_W_PH : DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC; 742def MULSA_W_PH : MULSA_W_PH_ENC, MULSA_W_PH_DESC; 743def PRECR_QB_PH : PRECR_QB_PH_ENC, PRECR_QB_PH_DESC; 744def PRECR_SRA_PH_W : PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC; 745def PRECR_SRA_R_PH_W : PRECR_SRA_R_PH_W_ENC, PRECR_SRA_R_PH_W_DESC; 746 747} 748 749// Pseudos. 750def MULSAQ_S_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMULSAQ_S_W_PH, NoItinerary, 751 MULSAQ_S_W_PH>; 752def MAQ_S_W_PHL_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMAQ_S_W_PHL, NoItinerary, 753 MAQ_S_W_PHL>; 754def MAQ_S_W_PHR_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMAQ_S_W_PHR, NoItinerary, 755 MAQ_S_W_PHR>; 756def MAQ_SA_W_PHL_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMAQ_SA_W_PHL, NoItinerary, 757 MAQ_SA_W_PHL>; 758def MAQ_SA_W_PHR_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMAQ_SA_W_PHR, NoItinerary, 759 MAQ_SA_W_PHR>; 760def DPAU_H_QBL_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAU_H_QBL, NoItinerary, 761 DPAU_H_QBL>; 762def DPAU_H_QBR_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAU_H_QBR, NoItinerary, 763 DPAU_H_QBR>; 764def DPSU_H_QBL_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSU_H_QBL, NoItinerary, 765 DPSU_H_QBL>; 766def DPSU_H_QBR_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSU_H_QBR, NoItinerary, 767 DPSU_H_QBR>; 768def DPAQ_S_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAQ_S_W_PH, NoItinerary, 769 DPAQ_S_W_PH>; 770def DPSQ_S_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSQ_S_W_PH, NoItinerary, 771 DPSQ_S_W_PH>; 772def DPAQ_SA_L_W_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAQ_SA_L_W, NoItinerary, 773 DPAQ_SA_L_W>; 774def DPSQ_SA_L_W_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSQ_SA_L_W, NoItinerary, 775 DPSQ_SA_L_W>; 776 777def MULT_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMULT, NoItinerary, MULT_DSP>, 778 IsCommutable; 779def MULTU_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMULTU, NoItinerary, MULTU_DSP>, 780 IsCommutable; 781def MADD_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMADD_DSP, NoItinerary, MADD_DSP>, 782 IsCommutable, UseAC; 783def MADDU_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMADDU_DSP, NoItinerary, MADDU_DSP>, 784 IsCommutable, UseAC; 785def MSUB_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMSUB_DSP, NoItinerary, MSUB_DSP>, 786 UseAC; 787def MSUBU_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMSUBU_DSP, NoItinerary, MSUBU_DSP>, 788 UseAC; 789 790def SHILO_PSEUDO : SHILO_R1_PSEUDO_BASE<MipsSHILO, NoItinerary, SHILO>; 791def SHILOV_PSEUDO : SHILO_R2_PSEUDO_BASE<MipsSHILO, NoItinerary, SHILOV>; 792def MTHLIP_PSEUDO : SHILO_R2_PSEUDO_BASE<MipsMTHLIP, NoItinerary, MTHLIP>; 793 794let Predicates = [HasDSPR2] in { 795 796def DPA_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPA_W_PH, NoItinerary, DPA_W_PH>; 797def DPS_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPS_W_PH, NoItinerary, DPS_W_PH>; 798def DPAQX_S_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAQX_S_W_PH, NoItinerary, 799 DPAQX_S_W_PH>; 800def DPAQX_SA_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAQX_SA_W_PH, NoItinerary, 801 DPAQX_SA_W_PH>; 802def DPAX_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAX_W_PH, NoItinerary, 803 DPAX_W_PH>; 804def DPSX_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSX_W_PH, NoItinerary, 805 DPSX_W_PH>; 806def DPSQX_S_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSQX_S_W_PH, NoItinerary, 807 DPSQX_S_W_PH>; 808def DPSQX_SA_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSQX_SA_W_PH, NoItinerary, 809 DPSQX_SA_W_PH>; 810def MULSA_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMULSA_W_PH, NoItinerary, 811 MULSA_W_PH>; 812 813} 814 815// Patterns. 816class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> : 817 Pat<pattern, result>, Requires<[pred]>; 818 819class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC, 820 RegisterClass SrcRC> : 821 DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))), 822 (COPY_TO_REGCLASS SrcRC:$src, DstRC)>; 823 824def : BitconvertPat<i32, v2i16, CPURegs, DSPRegs>; 825def : BitconvertPat<i32, v4i8, CPURegs, DSPRegs>; 826def : BitconvertPat<v2i16, i32, DSPRegs, CPURegs>; 827def : BitconvertPat<v4i8, i32, DSPRegs, CPURegs>; 828 829def : DSPPat<(v2i16 (load addr:$a)), 830 (v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPRegs))>; 831def : DSPPat<(v4i8 (load addr:$a)), 832 (v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPRegs))>; 833def : DSPPat<(store (v2i16 DSPRegs:$val), addr:$a), 834 (SW (COPY_TO_REGCLASS DSPRegs:$val, CPURegs), addr:$a)>; 835def : DSPPat<(store (v4i8 DSPRegs:$val), addr:$a), 836 (SW (COPY_TO_REGCLASS DSPRegs:$val, CPURegs), addr:$a)>; 837 838// Extr patterns. 839class EXTR_W_TY1_R2_Pat<SDPatternOperator OpNode, Instruction Instr> : 840 DSPPat<(i32 (OpNode CPURegs:$rs)), (Instr AC0, CPURegs:$rs)>; 841 842class EXTR_W_TY1_R1_Pat<SDPatternOperator OpNode, Instruction Instr> : 843 DSPPat<(i32 (OpNode immZExt5:$shift)), (Instr AC0, immZExt5:$shift)>; 844 845def : EXTR_W_TY1_R1_Pat<MipsEXTP, EXTP>; 846def : EXTR_W_TY1_R2_Pat<MipsEXTP, EXTPV>; 847def : EXTR_W_TY1_R1_Pat<MipsEXTPDP, EXTPDP>; 848def : EXTR_W_TY1_R2_Pat<MipsEXTPDP, EXTPDPV>; 849def : EXTR_W_TY1_R1_Pat<MipsEXTR_W, EXTR_W>; 850def : EXTR_W_TY1_R2_Pat<MipsEXTR_W, EXTRV_W>; 851def : EXTR_W_TY1_R1_Pat<MipsEXTR_R_W, EXTR_R_W>; 852def : EXTR_W_TY1_R2_Pat<MipsEXTR_R_W, EXTRV_R_W>; 853def : EXTR_W_TY1_R1_Pat<MipsEXTR_RS_W, EXTR_RS_W>; 854def : EXTR_W_TY1_R2_Pat<MipsEXTR_RS_W, EXTRV_RS_W>; 855def : EXTR_W_TY1_R1_Pat<MipsEXTR_S_H, EXTR_S_H>; 856def : EXTR_W_TY1_R2_Pat<MipsEXTR_S_H, EXTRV_S_H>; 857