MipsDSPInstrInfo.td revision 93ba059e489fd8fdf3a87db638a7283e66942a31
1//===- MipsDSPInstrInfo.td - DSP ASE instructions -*- tablegen ------------*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes Mips DSP ASE instructions. 11// 12//===----------------------------------------------------------------------===// 13 14// ImmLeaf 15def immZExt2 : ImmLeaf<i32, [{return isUInt<2>(Imm);}]>; 16def immZExt3 : ImmLeaf<i32, [{return isUInt<3>(Imm);}]>; 17def immZExt4 : ImmLeaf<i32, [{return isUInt<4>(Imm);}]>; 18def immZExt8 : ImmLeaf<i32, [{return isUInt<8>(Imm);}]>; 19def immZExt10 : ImmLeaf<i32, [{return isUInt<10>(Imm);}]>; 20def immSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}]>; 21 22// Mips-specific dsp nodes 23def SDT_MipsExtr : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>]>; 24def SDT_MipsShilo : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 25def SDT_MipsDPA : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>]>; 26 27class MipsDSPBase<string Opc, SDTypeProfile Prof> : 28 SDNode<!strconcat("MipsISD::", Opc), Prof, 29 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>; 30 31class MipsDSPSideEffectBase<string Opc, SDTypeProfile Prof> : 32 SDNode<!strconcat("MipsISD::", Opc), Prof, 33 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPSideEffect]>; 34 35def MipsEXTP : MipsDSPSideEffectBase<"EXTP", SDT_MipsExtr>; 36def MipsEXTPDP : MipsDSPSideEffectBase<"EXTPDP", SDT_MipsExtr>; 37def MipsEXTR_S_H : MipsDSPSideEffectBase<"EXTR_S_H", SDT_MipsExtr>; 38def MipsEXTR_W : MipsDSPSideEffectBase<"EXTR_W", SDT_MipsExtr>; 39def MipsEXTR_R_W : MipsDSPSideEffectBase<"EXTR_R_W", SDT_MipsExtr>; 40def MipsEXTR_RS_W : MipsDSPSideEffectBase<"EXTR_RS_W", SDT_MipsExtr>; 41 42def MipsSHILO : MipsDSPBase<"SHILO", SDT_MipsShilo>; 43def MipsMTHLIP : MipsDSPBase<"MTHLIP", SDT_MipsShilo>; 44 45def MipsMULSAQ_S_W_PH : MipsDSPSideEffectBase<"MULSAQ_S_W_PH", SDT_MipsDPA>; 46def MipsMAQ_S_W_PHL : MipsDSPSideEffectBase<"MAQ_S_W_PHL", SDT_MipsDPA>; 47def MipsMAQ_S_W_PHR : MipsDSPSideEffectBase<"MAQ_S_W_PHR", SDT_MipsDPA>; 48def MipsMAQ_SA_W_PHL : MipsDSPSideEffectBase<"MAQ_SA_W_PHL", SDT_MipsDPA>; 49def MipsMAQ_SA_W_PHR : MipsDSPSideEffectBase<"MAQ_SA_W_PHR", SDT_MipsDPA>; 50 51def MipsDPAU_H_QBL : MipsDSPBase<"DPAU_H_QBL", SDT_MipsDPA>; 52def MipsDPAU_H_QBR : MipsDSPBase<"DPAU_H_QBR", SDT_MipsDPA>; 53def MipsDPSU_H_QBL : MipsDSPBase<"DPSU_H_QBL", SDT_MipsDPA>; 54def MipsDPSU_H_QBR : MipsDSPBase<"DPSU_H_QBR", SDT_MipsDPA>; 55def MipsDPAQ_S_W_PH : MipsDSPSideEffectBase<"DPAQ_S_W_PH", SDT_MipsDPA>; 56def MipsDPSQ_S_W_PH : MipsDSPSideEffectBase<"DPSQ_S_W_PH", SDT_MipsDPA>; 57def MipsDPAQ_SA_L_W : MipsDSPSideEffectBase<"DPAQ_SA_L_W", SDT_MipsDPA>; 58def MipsDPSQ_SA_L_W : MipsDSPSideEffectBase<"DPSQ_SA_L_W", SDT_MipsDPA>; 59 60def MipsDPA_W_PH : MipsDSPBase<"DPA_W_PH", SDT_MipsDPA>; 61def MipsDPS_W_PH : MipsDSPBase<"DPS_W_PH", SDT_MipsDPA>; 62def MipsDPAQX_S_W_PH : MipsDSPSideEffectBase<"DPAQX_S_W_PH", SDT_MipsDPA>; 63def MipsDPAQX_SA_W_PH : MipsDSPSideEffectBase<"DPAQX_SA_W_PH", SDT_MipsDPA>; 64def MipsDPAX_W_PH : MipsDSPBase<"DPAX_W_PH", SDT_MipsDPA>; 65def MipsDPSX_W_PH : MipsDSPBase<"DPSX_W_PH", SDT_MipsDPA>; 66def MipsDPSQX_S_W_PH : MipsDSPSideEffectBase<"DPSQX_S_W_PH", SDT_MipsDPA>; 67def MipsDPSQX_SA_W_PH : MipsDSPSideEffectBase<"DPSQX_SA_W_PH", SDT_MipsDPA>; 68def MipsMULSA_W_PH : MipsDSPBase<"MULSA_W_PH", SDT_MipsDPA>; 69 70def MipsMULT : MipsDSPBase<"MULT", SDT_MipsDPA>; 71def MipsMULTU : MipsDSPBase<"MULTU", SDT_MipsDPA>; 72def MipsMADD_DSP : MipsDSPBase<"MADD_DSP", SDT_MipsDPA>; 73def MipsMADDU_DSP : MipsDSPBase<"MADDU_DSP", SDT_MipsDPA>; 74def MipsMSUB_DSP : MipsDSPBase<"MSUB_DSP", SDT_MipsDPA>; 75def MipsMSUBU_DSP : MipsDSPBase<"MSUBU_DSP", SDT_MipsDPA>; 76 77// Flags. 78class IsCommutable { 79 bit isCommutable = 1; 80} 81 82class UseAC { 83 list<Register> Uses = [AC0]; 84} 85 86class UseDSPCtrl { 87 list<Register> Uses = [DSPCtrl]; 88} 89 90class ClearDefs { 91 list<Register> Defs = []; 92} 93 94// Instruction encoding. 95class ADDU_QB_ENC : ADDU_QB_FMT<0b00000>; 96class ADDU_S_QB_ENC : ADDU_QB_FMT<0b00100>; 97class SUBU_QB_ENC : ADDU_QB_FMT<0b00001>; 98class SUBU_S_QB_ENC : ADDU_QB_FMT<0b00101>; 99class ADDQ_PH_ENC : ADDU_QB_FMT<0b01010>; 100class ADDQ_S_PH_ENC : ADDU_QB_FMT<0b01110>; 101class SUBQ_PH_ENC : ADDU_QB_FMT<0b01011>; 102class SUBQ_S_PH_ENC : ADDU_QB_FMT<0b01111>; 103class ADDQ_S_W_ENC : ADDU_QB_FMT<0b10110>; 104class SUBQ_S_W_ENC : ADDU_QB_FMT<0b10111>; 105class ADDSC_ENC : ADDU_QB_FMT<0b10000>; 106class ADDWC_ENC : ADDU_QB_FMT<0b10001>; 107class MODSUB_ENC : ADDU_QB_FMT<0b10010>; 108class RADDU_W_QB_ENC : RADDU_W_QB_FMT<0b10100>; 109class ABSQ_S_PH_ENC : ABSQ_S_PH_R2_FMT<0b01001>; 110class ABSQ_S_W_ENC : ABSQ_S_PH_R2_FMT<0b10001>; 111class PRECRQ_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01100>; 112class PRECRQ_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10100>; 113class PRECRQ_RS_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10101>; 114class PRECRQU_S_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01111>; 115class PRECEQ_W_PHL_ENC : ABSQ_S_PH_R2_FMT<0b01100>; 116class PRECEQ_W_PHR_ENC : ABSQ_S_PH_R2_FMT<0b01101>; 117class PRECEQU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b00100>; 118class PRECEQU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b00101>; 119class PRECEQU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b00110>; 120class PRECEQU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b00111>; 121class PRECEU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b11100>; 122class PRECEU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b11101>; 123class PRECEU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b11110>; 124class PRECEU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b11111>; 125class SHLL_QB_ENC : SHLL_QB_FMT<0b00000>; 126class SHLLV_QB_ENC : SHLL_QB_FMT<0b00010>; 127class SHRL_QB_ENC : SHLL_QB_FMT<0b00001>; 128class SHRLV_QB_ENC : SHLL_QB_FMT<0b00011>; 129class SHLL_PH_ENC : SHLL_QB_FMT<0b01000>; 130class SHLLV_PH_ENC : SHLL_QB_FMT<0b01010>; 131class SHLL_S_PH_ENC : SHLL_QB_FMT<0b01100>; 132class SHLLV_S_PH_ENC : SHLL_QB_FMT<0b01110>; 133class SHRA_PH_ENC : SHLL_QB_FMT<0b01001>; 134class SHRAV_PH_ENC : SHLL_QB_FMT<0b01011>; 135class SHRA_R_PH_ENC : SHLL_QB_FMT<0b01101>; 136class SHRAV_R_PH_ENC : SHLL_QB_FMT<0b01111>; 137class SHLL_S_W_ENC : SHLL_QB_FMT<0b10100>; 138class SHLLV_S_W_ENC : SHLL_QB_FMT<0b10110>; 139class SHRA_R_W_ENC : SHLL_QB_FMT<0b10101>; 140class SHRAV_R_W_ENC : SHLL_QB_FMT<0b10111>; 141class MULEU_S_PH_QBL_ENC : ADDU_QB_FMT<0b00110>; 142class MULEU_S_PH_QBR_ENC : ADDU_QB_FMT<0b00111>; 143class MULEQ_S_W_PHL_ENC : ADDU_QB_FMT<0b11100>; 144class MULEQ_S_W_PHR_ENC : ADDU_QB_FMT<0b11101>; 145class MULQ_RS_PH_ENC : ADDU_QB_FMT<0b11111>; 146class MULSAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00110>; 147class MAQ_S_W_PHL_ENC : DPA_W_PH_FMT<0b10100>; 148class MAQ_S_W_PHR_ENC : DPA_W_PH_FMT<0b10110>; 149class MAQ_SA_W_PHL_ENC : DPA_W_PH_FMT<0b10000>; 150class MAQ_SA_W_PHR_ENC : DPA_W_PH_FMT<0b10010>; 151class DPAU_H_QBL_ENC : DPA_W_PH_FMT<0b00011>; 152class DPAU_H_QBR_ENC : DPA_W_PH_FMT<0b00111>; 153class DPSU_H_QBL_ENC : DPA_W_PH_FMT<0b01011>; 154class DPSU_H_QBR_ENC : DPA_W_PH_FMT<0b01111>; 155class DPAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00100>; 156class DPSQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00101>; 157class DPAQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01100>; 158class DPSQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01101>; 159class MULT_DSP_ENC : MULT_FMT<0b000000, 0b011000>; 160class MULTU_DSP_ENC : MULT_FMT<0b000000, 0b011001>; 161class MADD_DSP_ENC : MULT_FMT<0b011100, 0b000000>; 162class MADDU_DSP_ENC : MULT_FMT<0b011100, 0b000001>; 163class MSUB_DSP_ENC : MULT_FMT<0b011100, 0b000100>; 164class MSUBU_DSP_ENC : MULT_FMT<0b011100, 0b000101>; 165class CMPU_EQ_QB_ENC : CMP_EQ_QB_R2_FMT<0b00000>; 166class CMPU_LT_QB_ENC : CMP_EQ_QB_R2_FMT<0b00001>; 167class CMPU_LE_QB_ENC : CMP_EQ_QB_R2_FMT<0b00010>; 168class CMPGU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b00100>; 169class CMPGU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b00101>; 170class CMPGU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b00110>; 171class CMP_EQ_PH_ENC : CMP_EQ_QB_R2_FMT<0b01000>; 172class CMP_LT_PH_ENC : CMP_EQ_QB_R2_FMT<0b01001>; 173class CMP_LE_PH_ENC : CMP_EQ_QB_R2_FMT<0b01010>; 174class BITREV_ENC : ABSQ_S_PH_R2_FMT<0b11011>; 175class PACKRL_PH_ENC : CMP_EQ_QB_R3_FMT<0b01110>; 176class REPL_QB_ENC : REPL_FMT<0b00010>; 177class REPL_PH_ENC : REPL_FMT<0b01010>; 178class REPLV_QB_ENC : ABSQ_S_PH_R2_FMT<0b00011>; 179class REPLV_PH_ENC : ABSQ_S_PH_R2_FMT<0b01011>; 180class PICK_QB_ENC : CMP_EQ_QB_R3_FMT<0b00011>; 181class PICK_PH_ENC : CMP_EQ_QB_R3_FMT<0b01011>; 182class LWX_ENC : LX_FMT<0b00000>; 183class LHX_ENC : LX_FMT<0b00100>; 184class LBUX_ENC : LX_FMT<0b00110>; 185class BPOSGE32_ENC : BPOSGE32_FMT<0b11100>; 186class INSV_ENC : INSV_FMT<0b001100>; 187 188class EXTP_ENC : EXTR_W_TY1_FMT<0b00010>; 189class EXTPV_ENC : EXTR_W_TY1_FMT<0b00011>; 190class EXTPDP_ENC : EXTR_W_TY1_FMT<0b01010>; 191class EXTPDPV_ENC : EXTR_W_TY1_FMT<0b01011>; 192class EXTR_W_ENC : EXTR_W_TY1_FMT<0b00000>; 193class EXTRV_W_ENC : EXTR_W_TY1_FMT<0b00001>; 194class EXTR_R_W_ENC : EXTR_W_TY1_FMT<0b00100>; 195class EXTRV_R_W_ENC : EXTR_W_TY1_FMT<0b00101>; 196class EXTR_RS_W_ENC : EXTR_W_TY1_FMT<0b00110>; 197class EXTRV_RS_W_ENC : EXTR_W_TY1_FMT<0b00111>; 198class EXTR_S_H_ENC : EXTR_W_TY1_FMT<0b01110>; 199class EXTRV_S_H_ENC : EXTR_W_TY1_FMT<0b01111>; 200class SHILO_ENC : SHILO_R1_FMT<0b11010>; 201class SHILOV_ENC : SHILO_R2_FMT<0b11011>; 202class MTHLIP_ENC : SHILO_R2_FMT<0b11111>; 203 204class RDDSP_ENC : RDDSP_FMT<0b10010>; 205class WRDSP_ENC : WRDSP_FMT<0b10011>; 206class ADDU_PH_ENC : ADDU_QB_FMT<0b01000>; 207class ADDU_S_PH_ENC : ADDU_QB_FMT<0b01100>; 208class SUBU_PH_ENC : ADDU_QB_FMT<0b01001>; 209class SUBU_S_PH_ENC : ADDU_QB_FMT<0b01101>; 210class CMPGDU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b11000>; 211class CMPGDU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b11001>; 212class CMPGDU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b11010>; 213class ABSQ_S_QB_ENC : ABSQ_S_PH_R2_FMT<0b00001>; 214class ADDUH_QB_ENC : ADDUH_QB_FMT<0b00000>; 215class ADDUH_R_QB_ENC : ADDUH_QB_FMT<0b00010>; 216class SUBUH_QB_ENC : ADDUH_QB_FMT<0b00001>; 217class SUBUH_R_QB_ENC : ADDUH_QB_FMT<0b00011>; 218class ADDQH_PH_ENC : ADDUH_QB_FMT<0b01000>; 219class ADDQH_R_PH_ENC : ADDUH_QB_FMT<0b01010>; 220class SUBQH_PH_ENC : ADDUH_QB_FMT<0b01001>; 221class SUBQH_R_PH_ENC : ADDUH_QB_FMT<0b01011>; 222class ADDQH_W_ENC : ADDUH_QB_FMT<0b10000>; 223class ADDQH_R_W_ENC : ADDUH_QB_FMT<0b10010>; 224class SUBQH_W_ENC : ADDUH_QB_FMT<0b10001>; 225class SUBQH_R_W_ENC : ADDUH_QB_FMT<0b10011>; 226class MUL_PH_ENC : ADDUH_QB_FMT<0b01100>; 227class MUL_S_PH_ENC : ADDUH_QB_FMT<0b01110>; 228class MULQ_S_W_ENC : ADDUH_QB_FMT<0b10110>; 229class MULQ_RS_W_ENC : ADDUH_QB_FMT<0b10111>; 230class MULQ_S_PH_ENC : ADDU_QB_FMT<0b11110>; 231class DPA_W_PH_ENC : DPA_W_PH_FMT<0b00000>; 232class DPS_W_PH_ENC : DPA_W_PH_FMT<0b00001>; 233class DPAQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11000>; 234class DPAQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11010>; 235class DPAX_W_PH_ENC : DPA_W_PH_FMT<0b01000>; 236class DPSX_W_PH_ENC : DPA_W_PH_FMT<0b01001>; 237class DPSQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11001>; 238class DPSQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11011>; 239class MULSA_W_PH_ENC : DPA_W_PH_FMT<0b00010>; 240class PRECR_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01101>; 241class PRECR_SRA_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11110>; 242class PRECR_SRA_R_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11111>; 243class SHRA_QB_ENC : SHLL_QB_FMT<0b00100>; 244class SHRAV_QB_ENC : SHLL_QB_FMT<0b00110>; 245class SHRA_R_QB_ENC : SHLL_QB_FMT<0b00101>; 246class SHRAV_R_QB_ENC : SHLL_QB_FMT<0b00111>; 247class SHRL_PH_ENC : SHLL_QB_FMT<0b11001>; 248class SHRLV_PH_ENC : SHLL_QB_FMT<0b11011>; 249class APPEND_ENC : APPEND_FMT<0b00000>; 250class BALIGN_ENC : APPEND_FMT<0b10000>; 251class PREPEND_ENC : APPEND_FMT<0b00001>; 252 253// Instruction desc. 254class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 255 InstrItinClass itin, RegisterClass RCD, 256 RegisterClass RCS, RegisterClass RCT = RCS> { 257 dag OutOperandList = (outs RCD:$rd); 258 dag InOperandList = (ins RCS:$rs, RCT:$rt); 259 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt"); 260 list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs, RCT:$rt))]; 261 InstrItinClass Itinerary = itin; 262 list<Register> Defs = [DSPCtrl]; 263} 264 265class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 266 InstrItinClass itin, RegisterClass RCD, 267 RegisterClass RCS = RCD> { 268 dag OutOperandList = (outs RCD:$rd); 269 dag InOperandList = (ins RCS:$rs); 270 string AsmString = !strconcat(instr_asm, "\t$rd, $rs"); 271 list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs))]; 272 InstrItinClass Itinerary = itin; 273 list<Register> Defs = [DSPCtrl]; 274} 275 276class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 277 InstrItinClass itin, RegisterClass RCS, 278 RegisterClass RCT = RCS> { 279 dag OutOperandList = (outs); 280 dag InOperandList = (ins RCS:$rs, RCT:$rt); 281 string AsmString = !strconcat(instr_asm, "\t$rs, $rt"); 282 list<dag> Pattern = [(OpNode RCS:$rs, RCT:$rt)]; 283 InstrItinClass Itinerary = itin; 284 list<Register> Defs = [DSPCtrl]; 285} 286 287class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 288 InstrItinClass itin, RegisterClass RCD, 289 RegisterClass RCS, RegisterClass RCT = RCS> { 290 dag OutOperandList = (outs RCD:$rd); 291 dag InOperandList = (ins RCS:$rs, RCT:$rt); 292 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt"); 293 list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs, RCT:$rt))]; 294 InstrItinClass Itinerary = itin; 295 list<Register> Defs = [DSPCtrl]; 296} 297 298class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 299 InstrItinClass itin, RegisterClass RCT, 300 RegisterClass RCS = RCT> { 301 dag OutOperandList = (outs RCT:$rt); 302 dag InOperandList = (ins RCS:$rs, shamt:$sa, RCS:$src); 303 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa"); 304 list<dag> Pattern = [(set RCT:$rt, (OpNode RCS:$src, RCS:$rs, immZExt5:$sa))]; 305 InstrItinClass Itinerary = itin; 306 list<Register> Defs = [DSPCtrl]; 307 string Constraints = "$src = $rt"; 308} 309 310class ABSQ_S_PH_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 311 InstrItinClass itin, RegisterClass RCD, 312 RegisterClass RCT = RCD> { 313 dag OutOperandList = (outs RCD:$rd); 314 dag InOperandList = (ins RCT:$rt); 315 string AsmString = !strconcat(instr_asm, "\t$rd, $rt"); 316 list<dag> Pattern = [(set RCD:$rd, (OpNode RCT:$rt))]; 317 InstrItinClass Itinerary = itin; 318 list<Register> Defs = [DSPCtrl]; 319} 320 321class REPL_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 322 ImmLeaf immPat, InstrItinClass itin, RegisterClass RC> { 323 dag OutOperandList = (outs RC:$rd); 324 dag InOperandList = (ins uimm16:$imm); 325 string AsmString = !strconcat(instr_asm, "\t$rd, $imm"); 326 list<dag> Pattern = [(set RC:$rd, (OpNode immPat:$imm))]; 327 InstrItinClass Itinerary = itin; 328 list<Register> Defs = [DSPCtrl]; 329} 330 331class SHLL_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 332 InstrItinClass itin, RegisterClass RC> { 333 dag OutOperandList = (outs RC:$rd); 334 dag InOperandList = (ins RC:$rt, CPURegs:$rs_sa); 335 string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa"); 336 list<dag> Pattern = [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs_sa))]; 337 InstrItinClass Itinerary = itin; 338 list<Register> Defs = [DSPCtrl]; 339} 340 341class SHLL_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 342 SDPatternOperator ImmPat, InstrItinClass itin, 343 RegisterClass RC> { 344 dag OutOperandList = (outs RC:$rd); 345 dag InOperandList = (ins RC:$rt, uimm16:$rs_sa); 346 string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa"); 347 list<dag> Pattern = [(set RC:$rd, (OpNode RC:$rt, ImmPat:$rs_sa))]; 348 InstrItinClass Itinerary = itin; 349 list<Register> Defs = [DSPCtrl]; 350} 351 352class LX_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 353 InstrItinClass itin> { 354 dag OutOperandList = (outs CPURegs:$rd); 355 dag InOperandList = (ins CPURegs:$base, CPURegs:$index); 356 string AsmString = !strconcat(instr_asm, "\t$rd, ${index}(${base})"); 357 list<dag> Pattern = [(set CPURegs:$rd, 358 (OpNode CPURegs:$base, CPURegs:$index))]; 359 InstrItinClass Itinerary = itin; 360 list<Register> Defs = [DSPCtrl]; 361 bit mayLoad = 1; 362} 363 364class ADDUH_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 365 InstrItinClass itin, RegisterClass RCD, 366 RegisterClass RCS = RCD, RegisterClass RCT = RCD> { 367 dag OutOperandList = (outs RCD:$rd); 368 dag InOperandList = (ins RCS:$rs, RCT:$rt); 369 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt"); 370 list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs, RCT:$rt))]; 371 InstrItinClass Itinerary = itin; 372 list<Register> Defs = [DSPCtrl]; 373} 374 375class APPEND_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 376 SDPatternOperator ImmOp, InstrItinClass itin> { 377 dag OutOperandList = (outs CPURegs:$rt); 378 dag InOperandList = (ins CPURegs:$rs, shamt:$sa, CPURegs:$src); 379 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa"); 380 list<dag> Pattern = [(set CPURegs:$rt, 381 (OpNode CPURegs:$src, CPURegs:$rs, ImmOp:$sa))]; 382 InstrItinClass Itinerary = itin; 383 list<Register> Defs = [DSPCtrl]; 384 string Constraints = "$src = $rt"; 385} 386 387class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 388 InstrItinClass itin> { 389 dag OutOperandList = (outs CPURegs:$rt); 390 dag InOperandList = (ins ACRegs:$ac, CPURegs:$shift_rs); 391 string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs"); 392 InstrItinClass Itinerary = itin; 393 list<Register> Defs = [DSPCtrl]; 394} 395 396class EXTR_W_TY1_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 397 InstrItinClass itin> { 398 dag OutOperandList = (outs CPURegs:$rt); 399 dag InOperandList = (ins ACRegs:$ac, uimm16:$shift_rs); 400 string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs"); 401 InstrItinClass Itinerary = itin; 402 list<Register> Defs = [DSPCtrl]; 403} 404 405class SHILO_R1_PSEUDO_BASE<SDPatternOperator OpNode, InstrItinClass itin, 406 Instruction realinst> : 407 PseudoDSP<(outs), (ins simm16:$shift), [(OpNode immSExt6:$shift)]>, 408 PseudoInstExpansion<(realinst AC0, simm16:$shift)> { 409 list<Register> Defs = [DSPCtrl, AC0]; 410 list<Register> Uses = [AC0]; 411 InstrItinClass Itinerary = itin; 412} 413 414class SHILO_R1_DESC_BASE<string instr_asm> { 415 dag OutOperandList = (outs ACRegs:$ac); 416 dag InOperandList = (ins simm16:$shift); 417 string AsmString = !strconcat(instr_asm, "\t$ac, $shift"); 418} 419 420class SHILO_R2_PSEUDO_BASE<SDPatternOperator OpNode, InstrItinClass itin, 421 Instruction realinst> : 422 PseudoDSP<(outs), (ins CPURegs:$rs), [(OpNode CPURegs:$rs)]>, 423 PseudoInstExpansion<(realinst AC0, CPURegs:$rs)> { 424 list<Register> Defs = [DSPCtrl, AC0]; 425 list<Register> Uses = [AC0]; 426 InstrItinClass Itinerary = itin; 427} 428 429class SHILO_R2_DESC_BASE<string instr_asm> { 430 dag OutOperandList = (outs ACRegs:$ac); 431 dag InOperandList = (ins CPURegs:$rs); 432 string AsmString = !strconcat(instr_asm, "\t$ac, $rs"); 433} 434 435class MTHLIP_DESC_BASE<string instr_asm> { 436 dag OutOperandList = (outs ACRegs:$ac); 437 dag InOperandList = (ins CPURegs:$rs); 438 string AsmString = !strconcat(instr_asm, "\t$rs, $ac"); 439} 440 441class RDDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 442 InstrItinClass itin> { 443 dag OutOperandList = (outs CPURegs:$rd); 444 dag InOperandList = (ins uimm16:$mask); 445 string AsmString = !strconcat(instr_asm, "\t$rd, $mask"); 446 list<dag> Pattern = [(set CPURegs:$rd, (OpNode immZExt10:$mask))]; 447 InstrItinClass Itinerary = itin; 448 list<Register> Uses = [DSPCtrl]; 449} 450 451class WRDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 452 InstrItinClass itin> { 453 dag OutOperandList = (outs); 454 dag InOperandList = (ins CPURegs:$rs, uimm16:$mask); 455 string AsmString = !strconcat(instr_asm, "\t$rs, $mask"); 456 list<dag> Pattern = [(OpNode CPURegs:$rs, immZExt10:$mask)]; 457 InstrItinClass Itinerary = itin; 458 list<Register> Defs = [DSPCtrl]; 459} 460 461class DPA_W_PH_PSEUDO_BASE<SDPatternOperator OpNode, InstrItinClass itin, 462 Instruction realinst> : 463 PseudoDSP<(outs), (ins CPURegs:$rs, CPURegs:$rt), 464 [(OpNode CPURegs:$rs, CPURegs:$rt)]>, 465 PseudoInstExpansion<(realinst AC0, CPURegs:$rs, CPURegs:$rt)> { 466 list<Register> Defs = [DSPCtrl, AC0]; 467 list<Register> Uses = [AC0]; 468 InstrItinClass Itinerary = itin; 469} 470 471class DPA_W_PH_DESC_BASE<string instr_asm> { 472 dag OutOperandList = (outs ACRegs:$ac); 473 dag InOperandList = (ins CPURegs:$rs, CPURegs:$rt); 474 string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt"); 475} 476 477class MULT_PSEUDO_BASE<SDPatternOperator OpNode, InstrItinClass itin, 478 Instruction realinst> : 479 PseudoDSP<(outs), (ins CPURegs:$rs, CPURegs:$rt), 480 [(OpNode CPURegs:$rs, CPURegs:$rt)]>, 481 PseudoInstExpansion<(realinst AC0, CPURegs:$rs, CPURegs:$rt)> { 482 list<Register> Defs = [DSPCtrl, AC0]; 483 InstrItinClass Itinerary = itin; 484} 485 486class MULT_DESC_BASE<string instr_asm> { 487 dag OutOperandList = (outs ACRegs:$ac); 488 dag InOperandList = (ins CPURegs:$rs, CPURegs:$rt); 489 string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt"); 490} 491 492class BPOSGE32_PSEUDO_DESC_BASE<SDPatternOperator OpNode, InstrItinClass itin> : 493 MipsPseudo<(outs CPURegs:$dst), (ins), "", [(set CPURegs:$dst, (OpNode))]> { 494 list<Register> Uses = [DSPCtrl]; 495 bit usesCustomInserter = 1; 496} 497 498class BPOSGE32_DESC_BASE<string instr_asm, InstrItinClass itin> { 499 dag OutOperandList = (outs); 500 dag InOperandList = (ins brtarget:$offset); 501 string AsmString = !strconcat(instr_asm, "\t$offset"); 502 InstrItinClass Itinerary = itin; 503 list<Register> Uses = [DSPCtrl]; 504 bit isBranch = 1; 505 bit isTerminator = 1; 506 bit hasDelaySlot = 1; 507} 508 509class INSV_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 510 InstrItinClass itin> { 511 dag OutOperandList = (outs CPURegs:$rt); 512 dag InOperandList = (ins CPURegs:$src, CPURegs:$rs); 513 string AsmString = !strconcat(instr_asm, "\t$rt, $rs"); 514 list<dag> Pattern = [(set CPURegs:$rt, (OpNode CPURegs:$src, CPURegs:$rs))]; 515 InstrItinClass Itinerary = itin; 516 list<Register> Uses = [DSPCtrl]; 517 string Constraints = "$src = $rt"; 518} 519 520//===----------------------------------------------------------------------===// 521// MIPS DSP Rev 1 522//===----------------------------------------------------------------------===// 523 524// Addition/subtraction 525class ADDU_QB_DESC : ADDU_QB_DESC_BASE<"addu.qb", int_mips_addu_qb, NoItinerary, 526 DSPRegs, DSPRegs>, IsCommutable; 527 528class ADDU_S_QB_DESC : ADDU_QB_DESC_BASE<"addu_s.qb", int_mips_addu_s_qb, 529 NoItinerary, DSPRegs, DSPRegs>, 530 IsCommutable; 531 532class SUBU_QB_DESC : ADDU_QB_DESC_BASE<"subu.qb", int_mips_subu_qb, NoItinerary, 533 DSPRegs, DSPRegs>; 534 535class SUBU_S_QB_DESC : ADDU_QB_DESC_BASE<"subu_s.qb", int_mips_subu_s_qb, 536 NoItinerary, DSPRegs, DSPRegs>; 537 538class ADDQ_PH_DESC : ADDU_QB_DESC_BASE<"addq.ph", int_mips_addq_ph, NoItinerary, 539 DSPRegs, DSPRegs>, IsCommutable; 540 541class ADDQ_S_PH_DESC : ADDU_QB_DESC_BASE<"addq_s.ph", int_mips_addq_s_ph, 542 NoItinerary, DSPRegs, DSPRegs>, 543 IsCommutable; 544 545class SUBQ_PH_DESC : ADDU_QB_DESC_BASE<"subq.ph", int_mips_subq_ph, NoItinerary, 546 DSPRegs, DSPRegs>; 547 548class SUBQ_S_PH_DESC : ADDU_QB_DESC_BASE<"subq_s.ph", int_mips_subq_s_ph, 549 NoItinerary, DSPRegs, DSPRegs>; 550 551class ADDQ_S_W_DESC : ADDU_QB_DESC_BASE<"addq_s.w", int_mips_addq_s_w, 552 NoItinerary, CPURegs, CPURegs>, 553 IsCommutable; 554 555class SUBQ_S_W_DESC : ADDU_QB_DESC_BASE<"subq_s.w", int_mips_subq_s_w, 556 NoItinerary, CPURegs, CPURegs>; 557 558class ADDSC_DESC : ADDU_QB_DESC_BASE<"addsc", int_mips_addsc, NoItinerary, 559 CPURegs, CPURegs>, IsCommutable; 560 561class ADDWC_DESC : ADDU_QB_DESC_BASE<"addwc", int_mips_addwc, NoItinerary, 562 CPURegs, CPURegs>, 563 IsCommutable, UseDSPCtrl; 564 565class MODSUB_DESC : ADDU_QB_DESC_BASE<"modsub", int_mips_modsub, NoItinerary, 566 CPURegs, CPURegs>, ClearDefs; 567 568class RADDU_W_QB_DESC : RADDU_W_QB_DESC_BASE<"raddu.w.qb", int_mips_raddu_w_qb, 569 NoItinerary, CPURegs, DSPRegs>, 570 ClearDefs; 571 572// Absolute value 573class ABSQ_S_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.ph", int_mips_absq_s_ph, 574 NoItinerary, DSPRegs>; 575 576class ABSQ_S_W_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.w", int_mips_absq_s_w, 577 NoItinerary, CPURegs>; 578 579// Precision reduce/expand 580class PRECRQ_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.qb.ph", 581 int_mips_precrq_qb_ph, 582 NoItinerary, DSPRegs, DSPRegs>, 583 ClearDefs; 584 585class PRECRQ_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.ph.w", 586 int_mips_precrq_ph_w, 587 NoItinerary, DSPRegs, CPURegs>, 588 ClearDefs; 589 590class PRECRQ_RS_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq_rs.ph.w", 591 int_mips_precrq_rs_ph_w, 592 NoItinerary, DSPRegs, 593 CPURegs>; 594 595class PRECRQU_S_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrqu_s.qb.ph", 596 int_mips_precrqu_s_qb_ph, 597 NoItinerary, DSPRegs, 598 DSPRegs>; 599 600class PRECEQ_W_PHL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phl", 601 int_mips_preceq_w_phl, 602 NoItinerary, CPURegs, DSPRegs>, 603 ClearDefs; 604 605class PRECEQ_W_PHR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phr", 606 int_mips_preceq_w_phr, 607 NoItinerary, CPURegs, DSPRegs>, 608 ClearDefs; 609 610class PRECEQU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbl", 611 int_mips_precequ_ph_qbl, 612 NoItinerary, DSPRegs>, 613 ClearDefs; 614 615class PRECEQU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbr", 616 int_mips_precequ_ph_qbr, 617 NoItinerary, DSPRegs>, 618 ClearDefs; 619 620class PRECEQU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbla", 621 int_mips_precequ_ph_qbla, 622 NoItinerary, DSPRegs>, 623 ClearDefs; 624 625class PRECEQU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbra", 626 int_mips_precequ_ph_qbra, 627 NoItinerary, DSPRegs>, 628 ClearDefs; 629 630class PRECEU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbl", 631 int_mips_preceu_ph_qbl, 632 NoItinerary, DSPRegs>, 633 ClearDefs; 634 635class PRECEU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbr", 636 int_mips_preceu_ph_qbr, 637 NoItinerary, DSPRegs>, 638 ClearDefs; 639 640class PRECEU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbla", 641 int_mips_preceu_ph_qbla, 642 NoItinerary, DSPRegs>, 643 ClearDefs; 644 645class PRECEU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbra", 646 int_mips_preceu_ph_qbra, 647 NoItinerary, DSPRegs>, 648 ClearDefs; 649 650// Shift 651class SHLL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shll.qb", int_mips_shll_qb, immZExt3, 652 NoItinerary, DSPRegs>; 653 654class SHLLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shllv.qb", int_mips_shll_qb, 655 NoItinerary, DSPRegs>; 656 657class SHRL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shrl.qb", int_mips_shrl_qb, immZExt3, 658 NoItinerary, DSPRegs>, ClearDefs; 659 660class SHRLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.qb", int_mips_shrl_qb, 661 NoItinerary, DSPRegs>, ClearDefs; 662 663class SHLL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll.ph", int_mips_shll_ph, immZExt4, 664 NoItinerary, DSPRegs>; 665 666class SHLLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv.ph", int_mips_shll_ph, 667 NoItinerary, DSPRegs>; 668 669class SHLL_S_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.ph", int_mips_shll_s_ph, 670 immZExt4, NoItinerary, DSPRegs>; 671 672class SHLLV_S_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.ph", int_mips_shll_s_ph, 673 NoItinerary, DSPRegs>; 674 675class SHRA_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra.ph", int_mips_shra_ph, immZExt4, 676 NoItinerary, DSPRegs>, ClearDefs; 677 678class SHRAV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav.ph", int_mips_shra_ph, 679 NoItinerary, DSPRegs>, ClearDefs; 680 681class SHRA_R_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.ph", int_mips_shra_r_ph, 682 immZExt4, NoItinerary, DSPRegs>, 683 ClearDefs; 684 685class SHRAV_R_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.ph", int_mips_shra_r_ph, 686 NoItinerary, DSPRegs>, ClearDefs; 687 688class SHLL_S_W_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.w", int_mips_shll_s_w, 689 immZExt5, NoItinerary, CPURegs>; 690 691class SHLLV_S_W_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.w", int_mips_shll_s_w, 692 NoItinerary, CPURegs>; 693 694class SHRA_R_W_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.w", int_mips_shra_r_w, 695 immZExt5, NoItinerary, CPURegs>, 696 ClearDefs; 697 698class SHRAV_R_W_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.w", int_mips_shra_r_w, 699 NoItinerary, CPURegs>; 700 701// Multiplication 702class MULEU_S_PH_QBL_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbl", 703 int_mips_muleu_s_ph_qbl, 704 NoItinerary, DSPRegs, DSPRegs>; 705 706class MULEU_S_PH_QBR_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbr", 707 int_mips_muleu_s_ph_qbr, 708 NoItinerary, DSPRegs, DSPRegs>; 709 710class MULEQ_S_W_PHL_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phl", 711 int_mips_muleq_s_w_phl, 712 NoItinerary, CPURegs, DSPRegs>, 713 IsCommutable; 714 715class MULEQ_S_W_PHR_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phr", 716 int_mips_muleq_s_w_phr, 717 NoItinerary, CPURegs, DSPRegs>, 718 IsCommutable; 719 720class MULQ_RS_PH_DESC : ADDU_QB_DESC_BASE<"mulq_rs.ph", int_mips_mulq_rs_ph, 721 NoItinerary, DSPRegs, DSPRegs>, 722 IsCommutable; 723 724class MULSAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsaq_s.w.ph">; 725 726class MAQ_S_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phl">; 727 728class MAQ_S_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phr">; 729 730class MAQ_SA_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phl">; 731 732class MAQ_SA_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phr">; 733 734// Dot product with accumulate/subtract 735class DPAU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbl">; 736 737class DPAU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbr">; 738 739class DPSU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbl">; 740 741class DPSU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbr">; 742 743class DPAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaq_s.w.ph">; 744 745class DPSQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsq_s.w.ph">; 746 747class DPAQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpaq_sa.l.w">; 748 749class DPSQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpsq_sa.l.w">; 750 751class MULT_DSP_DESC : MULT_DESC_BASE<"mult">; 752 753class MULTU_DSP_DESC : MULT_DESC_BASE<"multu">; 754 755class MADD_DSP_DESC : MULT_DESC_BASE<"madd">; 756 757class MADDU_DSP_DESC : MULT_DESC_BASE<"maddu">; 758 759class MSUB_DSP_DESC : MULT_DESC_BASE<"msub">; 760 761class MSUBU_DSP_DESC : MULT_DESC_BASE<"msubu">; 762 763// Comparison 764class CMPU_EQ_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.eq.qb", 765 int_mips_cmpu_eq_qb, NoItinerary, 766 DSPRegs>, IsCommutable; 767 768class CMPU_LT_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.lt.qb", 769 int_mips_cmpu_lt_qb, NoItinerary, 770 DSPRegs>, IsCommutable; 771 772class CMPU_LE_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.le.qb", 773 int_mips_cmpu_le_qb, NoItinerary, 774 DSPRegs>, IsCommutable; 775 776class CMPGU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.eq.qb", 777 int_mips_cmpgu_eq_qb, 778 NoItinerary, CPURegs, DSPRegs>, 779 IsCommutable; 780 781class CMPGU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.lt.qb", 782 int_mips_cmpgu_lt_qb, 783 NoItinerary, CPURegs, DSPRegs>, 784 IsCommutable; 785 786class CMPGU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.le.qb", 787 int_mips_cmpgu_le_qb, 788 NoItinerary, CPURegs, DSPRegs>, 789 IsCommutable; 790 791class CMP_EQ_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.eq.ph", int_mips_cmp_eq_ph, 792 NoItinerary, DSPRegs>, 793 IsCommutable; 794 795class CMP_LT_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.lt.ph", int_mips_cmp_lt_ph, 796 NoItinerary, DSPRegs>, 797 IsCommutable; 798 799class CMP_LE_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.le.ph", int_mips_cmp_le_ph, 800 NoItinerary, DSPRegs>, 801 IsCommutable; 802 803// Misc 804class BITREV_DESC : ABSQ_S_PH_R2_DESC_BASE<"bitrev", int_mips_bitrev, 805 NoItinerary, CPURegs>, ClearDefs; 806 807class PACKRL_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"packrl.ph", int_mips_packrl_ph, 808 NoItinerary, DSPRegs, DSPRegs>, 809 ClearDefs; 810 811class REPL_QB_DESC : REPL_DESC_BASE<"repl.qb", int_mips_repl_qb, immZExt8, 812 NoItinerary, DSPRegs>, ClearDefs; 813 814class REPL_PH_DESC : REPL_DESC_BASE<"repl.ph", int_mips_repl_ph, immZExt10, 815 NoItinerary, DSPRegs>, ClearDefs; 816 817class REPLV_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.qb", int_mips_repl_qb, 818 NoItinerary, DSPRegs, CPURegs>, 819 ClearDefs; 820 821class REPLV_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.ph", int_mips_repl_ph, 822 NoItinerary, DSPRegs, CPURegs>, 823 ClearDefs; 824 825class PICK_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.qb", int_mips_pick_qb, 826 NoItinerary, DSPRegs, DSPRegs>, 827 ClearDefs, UseDSPCtrl; 828 829class PICK_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.ph", int_mips_pick_ph, 830 NoItinerary, DSPRegs, DSPRegs>, 831 ClearDefs, UseDSPCtrl; 832 833class LWX_DESC : LX_DESC_BASE<"lwx", int_mips_lwx, NoItinerary>, ClearDefs; 834 835class LHX_DESC : LX_DESC_BASE<"lhx", int_mips_lhx, NoItinerary>, ClearDefs; 836 837class LBUX_DESC : LX_DESC_BASE<"lbux", int_mips_lbux, NoItinerary>, ClearDefs; 838 839class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", NoItinerary>; 840 841// Extr 842class EXTP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extp", MipsEXTP, NoItinerary>; 843 844class EXTPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpv", MipsEXTP, NoItinerary>; 845 846class EXTPDP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extpdp", MipsEXTPDP, NoItinerary>; 847 848class EXTPDPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpdpv", MipsEXTPDP, 849 NoItinerary>; 850 851class EXTR_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr.w", MipsEXTR_W, NoItinerary>; 852 853class EXTRV_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv.w", MipsEXTR_W, 854 NoItinerary>; 855 856class EXTR_R_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_r.w", MipsEXTR_R_W, 857 NoItinerary>; 858 859class EXTRV_R_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_r.w", MipsEXTR_R_W, 860 NoItinerary>; 861 862class EXTR_RS_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_rs.w", MipsEXTR_RS_W, 863 NoItinerary>; 864 865class EXTRV_RS_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_rs.w", MipsEXTR_RS_W, 866 NoItinerary>; 867 868class EXTR_S_H_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_s.h", MipsEXTR_S_H, 869 NoItinerary>; 870 871class EXTRV_S_H_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_s.h", MipsEXTR_S_H, 872 NoItinerary>; 873 874class SHILO_DESC : SHILO_R1_DESC_BASE<"shilo">; 875 876class SHILOV_DESC : SHILO_R2_DESC_BASE<"shilov">; 877 878class MTHLIP_DESC : MTHLIP_DESC_BASE<"mthlip">; 879 880class RDDSP_DESC : RDDSP_DESC_BASE<"rddsp", int_mips_rddsp, NoItinerary>; 881 882class WRDSP_DESC : WRDSP_DESC_BASE<"wrdsp", int_mips_wrdsp, NoItinerary>; 883 884class INSV_DESC : INSV_DESC_BASE<"insv", int_mips_insv, NoItinerary>; 885 886//===----------------------------------------------------------------------===// 887// MIPS DSP Rev 2 888// Addition/subtraction 889class ADDU_PH_DESC : ADDU_QB_DESC_BASE<"addu.ph", int_mips_addu_ph, NoItinerary, 890 DSPRegs, DSPRegs>, IsCommutable; 891 892class ADDU_S_PH_DESC : ADDU_QB_DESC_BASE<"addu_s.ph", int_mips_addu_s_ph, 893 NoItinerary, DSPRegs, DSPRegs>, 894 IsCommutable; 895 896class SUBU_PH_DESC : ADDU_QB_DESC_BASE<"subu.ph", int_mips_subu_ph, NoItinerary, 897 DSPRegs, DSPRegs>; 898 899class SUBU_S_PH_DESC : ADDU_QB_DESC_BASE<"subu_s.ph", int_mips_subu_s_ph, 900 NoItinerary, DSPRegs, DSPRegs>; 901 902class ADDUH_QB_DESC : ADDUH_QB_DESC_BASE<"adduh.qb", int_mips_adduh_qb, 903 NoItinerary, DSPRegs>, 904 ClearDefs, IsCommutable; 905 906class ADDUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"adduh_r.qb", int_mips_adduh_r_qb, 907 NoItinerary, DSPRegs>, 908 ClearDefs, IsCommutable; 909 910class SUBUH_QB_DESC : ADDUH_QB_DESC_BASE<"subuh.qb", int_mips_subuh_qb, 911 NoItinerary, DSPRegs>, ClearDefs; 912 913class SUBUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"subuh_r.qb", int_mips_subuh_r_qb, 914 NoItinerary, DSPRegs>, ClearDefs; 915 916class ADDQH_PH_DESC : ADDUH_QB_DESC_BASE<"addqh.ph", int_mips_addqh_ph, 917 NoItinerary, DSPRegs>, 918 ClearDefs, IsCommutable; 919 920class ADDQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"addqh_r.ph", int_mips_addqh_r_ph, 921 NoItinerary, DSPRegs>, 922 ClearDefs, IsCommutable; 923 924class SUBQH_PH_DESC : ADDUH_QB_DESC_BASE<"subqh.ph", int_mips_subqh_ph, 925 NoItinerary, DSPRegs>, ClearDefs; 926 927class SUBQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"subqh_r.ph", int_mips_subqh_r_ph, 928 NoItinerary, DSPRegs>, ClearDefs; 929 930class ADDQH_W_DESC : ADDUH_QB_DESC_BASE<"addqh.w", int_mips_addqh_w, 931 NoItinerary, CPURegs>, 932 ClearDefs, IsCommutable; 933 934class ADDQH_R_W_DESC : ADDUH_QB_DESC_BASE<"addqh_r.w", int_mips_addqh_r_w, 935 NoItinerary, CPURegs>, 936 ClearDefs, IsCommutable; 937 938class SUBQH_W_DESC : ADDUH_QB_DESC_BASE<"subqh.w", int_mips_subqh_w, 939 NoItinerary, CPURegs>, ClearDefs; 940 941class SUBQH_R_W_DESC : ADDUH_QB_DESC_BASE<"subqh_r.w", int_mips_subqh_r_w, 942 NoItinerary, CPURegs>, ClearDefs; 943 944// Comparison 945class CMPGDU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.eq.qb", 946 int_mips_cmpgdu_eq_qb, 947 NoItinerary, CPURegs, DSPRegs>, 948 IsCommutable; 949 950class CMPGDU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.lt.qb", 951 int_mips_cmpgdu_lt_qb, 952 NoItinerary, CPURegs, DSPRegs>, 953 IsCommutable; 954 955class CMPGDU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.le.qb", 956 int_mips_cmpgdu_le_qb, 957 NoItinerary, CPURegs, DSPRegs>, 958 IsCommutable; 959 960// Absolute 961class ABSQ_S_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.qb", int_mips_absq_s_qb, 962 NoItinerary, DSPRegs>; 963 964// Multiplication 965class MUL_PH_DESC : ADDUH_QB_DESC_BASE<"mul.ph", int_mips_mul_ph, NoItinerary, 966 DSPRegs>, IsCommutable; 967 968class MUL_S_PH_DESC : ADDUH_QB_DESC_BASE<"mul_s.ph", int_mips_mul_s_ph, 969 NoItinerary, DSPRegs>, IsCommutable; 970 971class MULQ_S_W_DESC : ADDUH_QB_DESC_BASE<"mulq_s.w", int_mips_mulq_s_w, 972 NoItinerary, CPURegs>, IsCommutable; 973 974class MULQ_RS_W_DESC : ADDUH_QB_DESC_BASE<"mulq_rs.w", int_mips_mulq_rs_w, 975 NoItinerary, CPURegs>, IsCommutable; 976 977class MULQ_S_PH_DESC : ADDU_QB_DESC_BASE<"mulq_s.ph", int_mips_mulq_s_ph, 978 NoItinerary, DSPRegs, DSPRegs>, 979 IsCommutable; 980 981// Dot product with accumulate/subtract 982class DPA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpa.w.ph">; 983 984class DPS_W_PH_DESC : DPA_W_PH_DESC_BASE<"dps.w.ph">; 985 986class DPAQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_s.w.ph">; 987 988class DPAQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_sa.w.ph">; 989 990class DPAX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpax.w.ph">; 991 992class DPSX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsx.w.ph">; 993 994class DPSQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_s.w.ph">; 995 996class DPSQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_sa.w.ph">; 997 998class MULSA_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsa.w.ph">; 999 1000// Precision reduce/expand 1001class PRECR_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precr.qb.ph", 1002 int_mips_precr_qb_ph, 1003 NoItinerary, DSPRegs, DSPRegs>; 1004 1005class PRECR_SRA_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra.ph.w", 1006 int_mips_precr_sra_ph_w, 1007 NoItinerary, DSPRegs, 1008 CPURegs>, ClearDefs; 1009 1010class PRECR_SRA_R_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra_r.ph.w", 1011 int_mips_precr_sra_r_ph_w, 1012 NoItinerary, DSPRegs, 1013 CPURegs>, ClearDefs; 1014 1015// Shift 1016class SHRA_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra.qb", int_mips_shra_qb, immZExt3, 1017 NoItinerary, DSPRegs>, ClearDefs; 1018 1019class SHRAV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav.qb", int_mips_shra_qb, 1020 NoItinerary, DSPRegs>, ClearDefs; 1021 1022class SHRA_R_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.qb", int_mips_shra_r_qb, 1023 immZExt3, NoItinerary, DSPRegs>, 1024 ClearDefs; 1025 1026class SHRAV_R_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.qb", int_mips_shra_r_qb, 1027 NoItinerary, DSPRegs>, ClearDefs; 1028 1029class SHRL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shrl.ph", int_mips_shrl_ph, immZExt4, 1030 NoItinerary, DSPRegs>, ClearDefs; 1031 1032class SHRLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.ph", int_mips_shrl_ph, 1033 NoItinerary, DSPRegs>, ClearDefs; 1034 1035// Misc 1036class APPEND_DESC : APPEND_DESC_BASE<"append", int_mips_append, immZExt5, 1037 NoItinerary>, ClearDefs; 1038 1039class BALIGN_DESC : APPEND_DESC_BASE<"balign", int_mips_balign, immZExt2, 1040 NoItinerary>, ClearDefs; 1041 1042class PREPEND_DESC : APPEND_DESC_BASE<"prepend", int_mips_prepend, immZExt5, 1043 NoItinerary>, ClearDefs; 1044 1045// Pseudos. 1046def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32, NoItinerary>; 1047 1048// Instruction defs. 1049// MIPS DSP Rev 1 1050def ADDU_QB : ADDU_QB_ENC, ADDU_QB_DESC; 1051def ADDU_S_QB : ADDU_S_QB_ENC, ADDU_S_QB_DESC; 1052def SUBU_QB : SUBU_QB_ENC, SUBU_QB_DESC; 1053def SUBU_S_QB : SUBU_S_QB_ENC, SUBU_S_QB_DESC; 1054def ADDQ_PH : ADDQ_PH_ENC, ADDQ_PH_DESC; 1055def ADDQ_S_PH : ADDQ_S_PH_ENC, ADDQ_S_PH_DESC; 1056def SUBQ_PH : SUBQ_PH_ENC, SUBQ_PH_DESC; 1057def SUBQ_S_PH : SUBQ_S_PH_ENC, SUBQ_S_PH_DESC; 1058def ADDQ_S_W : ADDQ_S_W_ENC, ADDQ_S_W_DESC; 1059def SUBQ_S_W : SUBQ_S_W_ENC, SUBQ_S_W_DESC; 1060def ADDSC : ADDSC_ENC, ADDSC_DESC; 1061def ADDWC : ADDWC_ENC, ADDWC_DESC; 1062def MODSUB : MODSUB_ENC, MODSUB_DESC; 1063def RADDU_W_QB : RADDU_W_QB_ENC, RADDU_W_QB_DESC; 1064def ABSQ_S_PH : ABSQ_S_PH_ENC, ABSQ_S_PH_DESC; 1065def ABSQ_S_W : ABSQ_S_W_ENC, ABSQ_S_W_DESC; 1066def PRECRQ_QB_PH : PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC; 1067def PRECRQ_PH_W : PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC; 1068def PRECRQ_RS_PH_W : PRECRQ_RS_PH_W_ENC, PRECRQ_RS_PH_W_DESC; 1069def PRECRQU_S_QB_PH : PRECRQU_S_QB_PH_ENC, PRECRQU_S_QB_PH_DESC; 1070def PRECEQ_W_PHL : PRECEQ_W_PHL_ENC, PRECEQ_W_PHL_DESC; 1071def PRECEQ_W_PHR : PRECEQ_W_PHR_ENC, PRECEQ_W_PHR_DESC; 1072def PRECEQU_PH_QBL : PRECEQU_PH_QBL_ENC, PRECEQU_PH_QBL_DESC; 1073def PRECEQU_PH_QBR : PRECEQU_PH_QBR_ENC, PRECEQU_PH_QBR_DESC; 1074def PRECEQU_PH_QBLA : PRECEQU_PH_QBLA_ENC, PRECEQU_PH_QBLA_DESC; 1075def PRECEQU_PH_QBRA : PRECEQU_PH_QBRA_ENC, PRECEQU_PH_QBRA_DESC; 1076def PRECEU_PH_QBL : PRECEU_PH_QBL_ENC, PRECEU_PH_QBL_DESC; 1077def PRECEU_PH_QBR : PRECEU_PH_QBR_ENC, PRECEU_PH_QBR_DESC; 1078def PRECEU_PH_QBLA : PRECEU_PH_QBLA_ENC, PRECEU_PH_QBLA_DESC; 1079def PRECEU_PH_QBRA : PRECEU_PH_QBRA_ENC, PRECEU_PH_QBRA_DESC; 1080def SHLL_QB : SHLL_QB_ENC, SHLL_QB_DESC; 1081def SHLLV_QB : SHLLV_QB_ENC, SHLLV_QB_DESC; 1082def SHRL_QB : SHRL_QB_ENC, SHRL_QB_DESC; 1083def SHRLV_QB : SHRLV_QB_ENC, SHRLV_QB_DESC; 1084def SHLL_PH : SHLL_PH_ENC, SHLL_PH_DESC; 1085def SHLLV_PH : SHLLV_PH_ENC, SHLLV_PH_DESC; 1086def SHLL_S_PH : SHLL_S_PH_ENC, SHLL_S_PH_DESC; 1087def SHLLV_S_PH : SHLLV_S_PH_ENC, SHLLV_S_PH_DESC; 1088def SHRA_PH : SHRA_PH_ENC, SHRA_PH_DESC; 1089def SHRAV_PH : SHRAV_PH_ENC, SHRAV_PH_DESC; 1090def SHRA_R_PH : SHRA_R_PH_ENC, SHRA_R_PH_DESC; 1091def SHRAV_R_PH : SHRAV_R_PH_ENC, SHRAV_R_PH_DESC; 1092def SHLL_S_W : SHLL_S_W_ENC, SHLL_S_W_DESC; 1093def SHLLV_S_W : SHLLV_S_W_ENC, SHLLV_S_W_DESC; 1094def SHRA_R_W : SHRA_R_W_ENC, SHRA_R_W_DESC; 1095def SHRAV_R_W : SHRAV_R_W_ENC, SHRAV_R_W_DESC; 1096def MULEU_S_PH_QBL : MULEU_S_PH_QBL_ENC, MULEU_S_PH_QBL_DESC; 1097def MULEU_S_PH_QBR : MULEU_S_PH_QBR_ENC, MULEU_S_PH_QBR_DESC; 1098def MULEQ_S_W_PHL : MULEQ_S_W_PHL_ENC, MULEQ_S_W_PHL_DESC; 1099def MULEQ_S_W_PHR : MULEQ_S_W_PHR_ENC, MULEQ_S_W_PHR_DESC; 1100def MULQ_RS_PH : MULQ_RS_PH_ENC, MULQ_RS_PH_DESC; 1101def MULSAQ_S_W_PH : MULSAQ_S_W_PH_ENC, MULSAQ_S_W_PH_DESC; 1102def MAQ_S_W_PHL : MAQ_S_W_PHL_ENC, MAQ_S_W_PHL_DESC; 1103def MAQ_S_W_PHR : MAQ_S_W_PHR_ENC, MAQ_S_W_PHR_DESC; 1104def MAQ_SA_W_PHL : MAQ_SA_W_PHL_ENC, MAQ_SA_W_PHL_DESC; 1105def MAQ_SA_W_PHR : MAQ_SA_W_PHR_ENC, MAQ_SA_W_PHR_DESC; 1106def DPAU_H_QBL : DPAU_H_QBL_ENC, DPAU_H_QBL_DESC; 1107def DPAU_H_QBR : DPAU_H_QBR_ENC, DPAU_H_QBR_DESC; 1108def DPSU_H_QBL : DPSU_H_QBL_ENC, DPSU_H_QBL_DESC; 1109def DPSU_H_QBR : DPSU_H_QBR_ENC, DPSU_H_QBR_DESC; 1110def DPAQ_S_W_PH : DPAQ_S_W_PH_ENC, DPAQ_S_W_PH_DESC; 1111def DPSQ_S_W_PH : DPSQ_S_W_PH_ENC, DPSQ_S_W_PH_DESC; 1112def DPAQ_SA_L_W : DPAQ_SA_L_W_ENC, DPAQ_SA_L_W_DESC; 1113def DPSQ_SA_L_W : DPSQ_SA_L_W_ENC, DPSQ_SA_L_W_DESC; 1114def MULT_DSP : MULT_DSP_ENC, MULT_DSP_DESC; 1115def MULTU_DSP : MULTU_DSP_ENC, MULTU_DSP_DESC; 1116def MADD_DSP : MADD_DSP_ENC, MADD_DSP_DESC; 1117def MADDU_DSP : MADDU_DSP_ENC, MADDU_DSP_DESC; 1118def MSUB_DSP : MSUB_DSP_ENC, MSUB_DSP_DESC; 1119def MSUBU_DSP : MSUBU_DSP_ENC, MSUBU_DSP_DESC; 1120def CMPU_EQ_QB : CMPU_EQ_QB_ENC, CMPU_EQ_QB_DESC; 1121def CMPU_LT_QB : CMPU_LT_QB_ENC, CMPU_LT_QB_DESC; 1122def CMPU_LE_QB : CMPU_LE_QB_ENC, CMPU_LE_QB_DESC; 1123def CMPGU_EQ_QB : CMPGU_EQ_QB_ENC, CMPGU_EQ_QB_DESC; 1124def CMPGU_LT_QB : CMPGU_LT_QB_ENC, CMPGU_LT_QB_DESC; 1125def CMPGU_LE_QB : CMPGU_LE_QB_ENC, CMPGU_LE_QB_DESC; 1126def CMP_EQ_PH : CMP_EQ_PH_ENC, CMP_EQ_PH_DESC; 1127def CMP_LT_PH : CMP_LT_PH_ENC, CMP_LT_PH_DESC; 1128def CMP_LE_PH : CMP_LE_PH_ENC, CMP_LE_PH_DESC; 1129def BITREV : BITREV_ENC, BITREV_DESC; 1130def PACKRL_PH : PACKRL_PH_ENC, PACKRL_PH_DESC; 1131def REPL_QB : REPL_QB_ENC, REPL_QB_DESC; 1132def REPL_PH : REPL_PH_ENC, REPL_PH_DESC; 1133def REPLV_QB : REPLV_QB_ENC, REPLV_QB_DESC; 1134def REPLV_PH : REPLV_PH_ENC, REPLV_PH_DESC; 1135def PICK_QB : PICK_QB_ENC, PICK_QB_DESC; 1136def PICK_PH : PICK_PH_ENC, PICK_PH_DESC; 1137def LWX : LWX_ENC, LWX_DESC; 1138def LHX : LHX_ENC, LHX_DESC; 1139def LBUX : LBUX_ENC, LBUX_DESC; 1140def BPOSGE32 : BPOSGE32_ENC, BPOSGE32_DESC; 1141def INSV : INSV_ENC, INSV_DESC; 1142def EXTP : EXTP_ENC, EXTP_DESC; 1143def EXTPV : EXTPV_ENC, EXTPV_DESC; 1144def EXTPDP : EXTPDP_ENC, EXTPDP_DESC; 1145def EXTPDPV : EXTPDPV_ENC, EXTPDPV_DESC; 1146def EXTR_W : EXTR_W_ENC, EXTR_W_DESC; 1147def EXTRV_W : EXTRV_W_ENC, EXTRV_W_DESC; 1148def EXTR_R_W : EXTR_R_W_ENC, EXTR_R_W_DESC; 1149def EXTRV_R_W : EXTRV_R_W_ENC, EXTRV_R_W_DESC; 1150def EXTR_RS_W : EXTR_RS_W_ENC, EXTR_RS_W_DESC; 1151def EXTRV_RS_W : EXTRV_RS_W_ENC, EXTRV_RS_W_DESC; 1152def EXTR_S_H : EXTR_S_H_ENC, EXTR_S_H_DESC; 1153def EXTRV_S_H : EXTRV_S_H_ENC, EXTRV_S_H_DESC; 1154def SHILO : SHILO_ENC, SHILO_DESC; 1155def SHILOV : SHILOV_ENC, SHILOV_DESC; 1156def MTHLIP : MTHLIP_ENC, MTHLIP_DESC; 1157def RDDSP : RDDSP_ENC, RDDSP_DESC; 1158def WRDSP : WRDSP_ENC, WRDSP_DESC; 1159 1160// MIPS DSP Rev 2 1161let Predicates = [HasDSPR2] in { 1162 1163def ADDU_PH : ADDU_PH_ENC, ADDU_PH_DESC; 1164def ADDU_S_PH : ADDU_S_PH_ENC, ADDU_S_PH_DESC; 1165def SUBU_PH : SUBU_PH_ENC, SUBU_PH_DESC; 1166def SUBU_S_PH : SUBU_S_PH_ENC, SUBU_S_PH_DESC; 1167def CMPGDU_EQ_QB : CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC; 1168def CMPGDU_LT_QB : CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC; 1169def CMPGDU_LE_QB : CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC; 1170def ABSQ_S_QB : ABSQ_S_QB_ENC, ABSQ_S_QB_DESC; 1171def ADDUH_QB : ADDUH_QB_ENC, ADDUH_QB_DESC; 1172def ADDUH_R_QB : ADDUH_R_QB_ENC, ADDUH_R_QB_DESC; 1173def SUBUH_QB : SUBUH_QB_ENC, SUBUH_QB_DESC; 1174def SUBUH_R_QB : SUBUH_R_QB_ENC, SUBUH_R_QB_DESC; 1175def ADDQH_PH : ADDQH_PH_ENC, ADDQH_PH_DESC; 1176def ADDQH_R_PH : ADDQH_R_PH_ENC, ADDQH_R_PH_DESC; 1177def SUBQH_PH : SUBQH_PH_ENC, SUBQH_PH_DESC; 1178def SUBQH_R_PH : SUBQH_R_PH_ENC, SUBQH_R_PH_DESC; 1179def ADDQH_W : ADDQH_W_ENC, ADDQH_W_DESC; 1180def ADDQH_R_W : ADDQH_R_W_ENC, ADDQH_R_W_DESC; 1181def SUBQH_W : SUBQH_W_ENC, SUBQH_W_DESC; 1182def SUBQH_R_W : SUBQH_R_W_ENC, SUBQH_R_W_DESC; 1183def MUL_PH : MUL_PH_ENC, MUL_PH_DESC; 1184def MUL_S_PH : MUL_S_PH_ENC, MUL_S_PH_DESC; 1185def MULQ_S_W : MULQ_S_W_ENC, MULQ_S_W_DESC; 1186def MULQ_RS_W : MULQ_RS_W_ENC, MULQ_RS_W_DESC; 1187def MULQ_S_PH : MULQ_S_PH_ENC, MULQ_S_PH_DESC; 1188def DPA_W_PH : DPA_W_PH_ENC, DPA_W_PH_DESC; 1189def DPS_W_PH : DPS_W_PH_ENC, DPS_W_PH_DESC; 1190def DPAQX_S_W_PH : DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC; 1191def DPAQX_SA_W_PH : DPAQX_SA_W_PH_ENC, DPAQX_SA_W_PH_DESC; 1192def DPAX_W_PH : DPAX_W_PH_ENC, DPAX_W_PH_DESC; 1193def DPSX_W_PH : DPSX_W_PH_ENC, DPSX_W_PH_DESC; 1194def DPSQX_S_W_PH : DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC; 1195def DPSQX_SA_W_PH : DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC; 1196def MULSA_W_PH : MULSA_W_PH_ENC, MULSA_W_PH_DESC; 1197def PRECR_QB_PH : PRECR_QB_PH_ENC, PRECR_QB_PH_DESC; 1198def PRECR_SRA_PH_W : PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC; 1199def PRECR_SRA_R_PH_W : PRECR_SRA_R_PH_W_ENC, PRECR_SRA_R_PH_W_DESC; 1200def SHRA_QB : SHRA_QB_ENC, SHRA_QB_DESC; 1201def SHRAV_QB : SHRAV_QB_ENC, SHRAV_QB_DESC; 1202def SHRA_R_QB : SHRA_R_QB_ENC, SHRA_R_QB_DESC; 1203def SHRAV_R_QB : SHRAV_R_QB_ENC, SHRAV_R_QB_DESC; 1204def SHRL_PH : SHRL_PH_ENC, SHRL_PH_DESC; 1205def SHRLV_PH : SHRLV_PH_ENC, SHRLV_PH_DESC; 1206def APPEND : APPEND_ENC, APPEND_DESC; 1207def BALIGN : BALIGN_ENC, BALIGN_DESC; 1208def PREPEND : PREPEND_ENC, PREPEND_DESC; 1209 1210} 1211 1212// Pseudos. 1213def MULSAQ_S_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMULSAQ_S_W_PH, NoItinerary, 1214 MULSAQ_S_W_PH>; 1215def MAQ_S_W_PHL_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMAQ_S_W_PHL, NoItinerary, 1216 MAQ_S_W_PHL>; 1217def MAQ_S_W_PHR_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMAQ_S_W_PHR, NoItinerary, 1218 MAQ_S_W_PHR>; 1219def MAQ_SA_W_PHL_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMAQ_SA_W_PHL, NoItinerary, 1220 MAQ_SA_W_PHL>; 1221def MAQ_SA_W_PHR_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMAQ_SA_W_PHR, NoItinerary, 1222 MAQ_SA_W_PHR>; 1223def DPAU_H_QBL_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAU_H_QBL, NoItinerary, 1224 DPAU_H_QBL>; 1225def DPAU_H_QBR_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAU_H_QBR, NoItinerary, 1226 DPAU_H_QBR>; 1227def DPSU_H_QBL_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSU_H_QBL, NoItinerary, 1228 DPSU_H_QBL>; 1229def DPSU_H_QBR_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSU_H_QBR, NoItinerary, 1230 DPSU_H_QBR>; 1231def DPAQ_S_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAQ_S_W_PH, NoItinerary, 1232 DPAQ_S_W_PH>; 1233def DPSQ_S_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSQ_S_W_PH, NoItinerary, 1234 DPSQ_S_W_PH>; 1235def DPAQ_SA_L_W_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAQ_SA_L_W, NoItinerary, 1236 DPAQ_SA_L_W>; 1237def DPSQ_SA_L_W_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSQ_SA_L_W, NoItinerary, 1238 DPSQ_SA_L_W>; 1239 1240def MULT_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMULT, NoItinerary, MULT_DSP>, 1241 IsCommutable; 1242def MULTU_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMULTU, NoItinerary, MULTU_DSP>, 1243 IsCommutable; 1244def MADD_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMADD_DSP, NoItinerary, MADD_DSP>, 1245 IsCommutable, UseAC; 1246def MADDU_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMADDU_DSP, NoItinerary, MADDU_DSP>, 1247 IsCommutable, UseAC; 1248def MSUB_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMSUB_DSP, NoItinerary, MSUB_DSP>, 1249 UseAC; 1250def MSUBU_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMSUBU_DSP, NoItinerary, MSUBU_DSP>, 1251 UseAC; 1252 1253def SHILO_PSEUDO : SHILO_R1_PSEUDO_BASE<MipsSHILO, NoItinerary, SHILO>; 1254def SHILOV_PSEUDO : SHILO_R2_PSEUDO_BASE<MipsSHILO, NoItinerary, SHILOV>; 1255def MTHLIP_PSEUDO : SHILO_R2_PSEUDO_BASE<MipsMTHLIP, NoItinerary, MTHLIP>; 1256 1257let Predicates = [HasDSPR2] in { 1258 1259def DPA_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPA_W_PH, NoItinerary, DPA_W_PH>; 1260def DPS_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPS_W_PH, NoItinerary, DPS_W_PH>; 1261def DPAQX_S_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAQX_S_W_PH, NoItinerary, 1262 DPAQX_S_W_PH>; 1263def DPAQX_SA_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAQX_SA_W_PH, NoItinerary, 1264 DPAQX_SA_W_PH>; 1265def DPAX_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAX_W_PH, NoItinerary, 1266 DPAX_W_PH>; 1267def DPSX_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSX_W_PH, NoItinerary, 1268 DPSX_W_PH>; 1269def DPSQX_S_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSQX_S_W_PH, NoItinerary, 1270 DPSQX_S_W_PH>; 1271def DPSQX_SA_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSQX_SA_W_PH, NoItinerary, 1272 DPSQX_SA_W_PH>; 1273def MULSA_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMULSA_W_PH, NoItinerary, 1274 MULSA_W_PH>; 1275 1276} 1277 1278// Patterns. 1279class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> : 1280 Pat<pattern, result>, Requires<[pred]>; 1281 1282class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC, 1283 RegisterClass SrcRC> : 1284 DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))), 1285 (COPY_TO_REGCLASS SrcRC:$src, DstRC)>; 1286 1287def : BitconvertPat<i32, v2i16, CPURegs, DSPRegs>; 1288def : BitconvertPat<i32, v4i8, CPURegs, DSPRegs>; 1289def : BitconvertPat<v2i16, i32, DSPRegs, CPURegs>; 1290def : BitconvertPat<v4i8, i32, DSPRegs, CPURegs>; 1291 1292def : DSPPat<(v2i16 (load addr:$a)), 1293 (v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPRegs))>; 1294def : DSPPat<(v4i8 (load addr:$a)), 1295 (v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPRegs))>; 1296def : DSPPat<(store (v2i16 DSPRegs:$val), addr:$a), 1297 (SW (COPY_TO_REGCLASS DSPRegs:$val, CPURegs), addr:$a)>; 1298def : DSPPat<(store (v4i8 DSPRegs:$val), addr:$a), 1299 (SW (COPY_TO_REGCLASS DSPRegs:$val, CPURegs), addr:$a)>; 1300 1301// Extr patterns. 1302class EXTR_W_TY1_R2_Pat<SDPatternOperator OpNode, Instruction Instr> : 1303 DSPPat<(i32 (OpNode CPURegs:$rs)), (Instr AC0, CPURegs:$rs)>; 1304 1305class EXTR_W_TY1_R1_Pat<SDPatternOperator OpNode, Instruction Instr> : 1306 DSPPat<(i32 (OpNode immZExt5:$shift)), (Instr AC0, immZExt5:$shift)>; 1307 1308def : EXTR_W_TY1_R1_Pat<MipsEXTP, EXTP>; 1309def : EXTR_W_TY1_R2_Pat<MipsEXTP, EXTPV>; 1310def : EXTR_W_TY1_R1_Pat<MipsEXTPDP, EXTPDP>; 1311def : EXTR_W_TY1_R2_Pat<MipsEXTPDP, EXTPDPV>; 1312def : EXTR_W_TY1_R1_Pat<MipsEXTR_W, EXTR_W>; 1313def : EXTR_W_TY1_R2_Pat<MipsEXTR_W, EXTRV_W>; 1314def : EXTR_W_TY1_R1_Pat<MipsEXTR_R_W, EXTR_R_W>; 1315def : EXTR_W_TY1_R2_Pat<MipsEXTR_R_W, EXTRV_R_W>; 1316def : EXTR_W_TY1_R1_Pat<MipsEXTR_RS_W, EXTR_RS_W>; 1317def : EXTR_W_TY1_R2_Pat<MipsEXTR_RS_W, EXTRV_RS_W>; 1318def : EXTR_W_TY1_R1_Pat<MipsEXTR_S_H, EXTR_S_H>; 1319def : EXTR_W_TY1_R2_Pat<MipsEXTR_S_H, EXTRV_S_H>; 1320