MipsDSPInstrInfo.td revision fd89e6ffdab95ae6b4568b8a4153064952f61ea6 
1//===- MipsDSPInstrInfo.td - DSP ASE instructions -*- tablegen ------------*-=//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes Mips DSP ASE instructions.
11//
12//===----------------------------------------------------------------------===//
13
14// ImmLeaf
15def immZExt2 : ImmLeaf<i32, [{return isUInt<2>(Imm);}]>;
16def immZExt3 : ImmLeaf<i32, [{return isUInt<3>(Imm);}]>;
17def immZExt4 : ImmLeaf<i32, [{return isUInt<4>(Imm);}]>;
18def immZExt8 : ImmLeaf<i32, [{return isUInt<8>(Imm);}]>;
19def immZExt10 : ImmLeaf<i32, [{return isUInt<10>(Imm);}]>;
20def immSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}]>;
21
22// Mips-specific dsp nodes
23def SDT_MipsExtr : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>]>;
24
25class MipsDSPSideEffectBase<string Opc, SDTypeProfile Prof> :
26  SDNode<!strconcat("MipsISD::", Opc), Prof,
27         [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPSideEffect]>;
28
29def MipsEXTP : MipsDSPSideEffectBase<"EXTP", SDT_MipsExtr>;
30def MipsEXTPDP : MipsDSPSideEffectBase<"EXTPDP", SDT_MipsExtr>;
31def MipsEXTR_S_H : MipsDSPSideEffectBase<"EXTR_S_H", SDT_MipsExtr>;
32def MipsEXTR_W : MipsDSPSideEffectBase<"EXTR_W", SDT_MipsExtr>;
33def MipsEXTR_R_W : MipsDSPSideEffectBase<"EXTR_R_W", SDT_MipsExtr>;
34def MipsEXTR_RS_W : MipsDSPSideEffectBase<"EXTR_RS_W", SDT_MipsExtr>;
35
36// Instruction encoding.
37class EXTP_ENC : EXTR_W_TY1_FMT<0b00010>;
38class EXTPV_ENC : EXTR_W_TY1_FMT<0b00011>;
39class EXTPDP_ENC : EXTR_W_TY1_FMT<0b01010>;
40class EXTPDPV_ENC : EXTR_W_TY1_FMT<0b01011>;
41class EXTR_W_ENC : EXTR_W_TY1_FMT<0b00000>;
42class EXTRV_W_ENC : EXTR_W_TY1_FMT<0b00001>;
43class EXTR_R_W_ENC : EXTR_W_TY1_FMT<0b00100>;
44class EXTRV_R_W_ENC : EXTR_W_TY1_FMT<0b00101>;
45class EXTR_RS_W_ENC : EXTR_W_TY1_FMT<0b00110>;
46class EXTRV_RS_W_ENC : EXTR_W_TY1_FMT<0b00111>;
47class EXTR_S_H_ENC : EXTR_W_TY1_FMT<0b01110>;
48class EXTRV_S_H_ENC : EXTR_W_TY1_FMT<0b01111>;
49
50// Instruction desc.
51class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
52                              InstrItinClass itin> {
53  dag OutOperandList = (outs CPURegs:$rt);
54  dag InOperandList = (ins ACRegs:$ac, CPURegs:$shift_rs);
55  string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
56  InstrItinClass Itinerary = itin;
57  list<Register> Defs = [DSPCtrl];
58}
59
60class EXTR_W_TY1_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
61                              InstrItinClass itin> {
62  dag OutOperandList = (outs CPURegs:$rt);
63  dag InOperandList = (ins ACRegs:$ac, uimm16:$shift_rs);
64  string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
65  InstrItinClass Itinerary = itin;
66  list<Register> Defs = [DSPCtrl];
67}
68
69//===----------------------------------------------------------------------===//
70// MIPS DSP Rev 1
71//===----------------------------------------------------------------------===//
72
73// Extr
74class EXTP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extp", MipsEXTP, NoItinerary>;
75
76class EXTPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpv", MipsEXTP, NoItinerary>;
77
78class EXTPDP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extpdp", MipsEXTPDP, NoItinerary>;
79
80class EXTPDPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpdpv", MipsEXTPDP,
81                                             NoItinerary>;
82
83class EXTR_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr.w", MipsEXTR_W, NoItinerary>;
84
85class EXTRV_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv.w", MipsEXTR_W,
86                                             NoItinerary>;
87
88class EXTR_R_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_r.w", MipsEXTR_R_W,
89                                              NoItinerary>;
90
91class EXTRV_R_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_r.w", MipsEXTR_R_W,
92                                               NoItinerary>;
93
94class EXTR_RS_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_rs.w", MipsEXTR_RS_W,
95                                               NoItinerary>;
96
97class EXTRV_RS_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_rs.w", MipsEXTR_RS_W,
98                                                NoItinerary>;
99
100class EXTR_S_H_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_s.h", MipsEXTR_S_H,
101                                              NoItinerary>;
102
103class EXTRV_S_H_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_s.h", MipsEXTR_S_H,
104                                               NoItinerary>;
105
106// Instruction defs.
107// MIPS DSP Rev 1
108def EXTP : EXTP_ENC, EXTP_DESC;
109def EXTPV : EXTPV_ENC, EXTPV_DESC;
110def EXTPDP : EXTPDP_ENC, EXTPDP_DESC;
111def EXTPDPV : EXTPDPV_ENC, EXTPDPV_DESC;
112def EXTR_W : EXTR_W_ENC, EXTR_W_DESC;
113def EXTRV_W : EXTRV_W_ENC, EXTRV_W_DESC;
114def EXTR_R_W : EXTR_R_W_ENC, EXTR_R_W_DESC;
115def EXTRV_R_W : EXTRV_R_W_ENC, EXTRV_R_W_DESC;
116def EXTR_RS_W : EXTR_RS_W_ENC, EXTR_RS_W_DESC;
117def EXTRV_RS_W : EXTRV_RS_W_ENC, EXTRV_RS_W_DESC;
118def EXTR_S_H : EXTR_S_H_ENC, EXTR_S_H_DESC;
119def EXTRV_S_H : EXTRV_S_H_ENC, EXTRV_S_H_DESC;
120
121// Patterns.
122class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> :
123  Pat<pattern, result>, Requires<[pred]>;
124
125class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC,
126                    RegisterClass SrcRC> :
127   DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))),
128          (COPY_TO_REGCLASS SrcRC:$src, DstRC)>;
129
130def : BitconvertPat<i32, v2i16, CPURegs, DSPRegs>;
131def : BitconvertPat<i32, v4i8, CPURegs, DSPRegs>;
132def : BitconvertPat<v2i16, i32, DSPRegs, CPURegs>;
133def : BitconvertPat<v4i8, i32, DSPRegs, CPURegs>;
134
135def : DSPPat<(v2i16 (load addr:$a)),
136             (v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPRegs))>;
137def : DSPPat<(v4i8 (load addr:$a)),
138             (v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPRegs))>;
139def : DSPPat<(store (v2i16 DSPRegs:$val), addr:$a),
140             (SW (COPY_TO_REGCLASS DSPRegs:$val, CPURegs), addr:$a)>;
141def : DSPPat<(store (v4i8 DSPRegs:$val), addr:$a),
142             (SW (COPY_TO_REGCLASS DSPRegs:$val, CPURegs), addr:$a)>;
143
144// Extr patterns.
145class EXTR_W_TY1_R2_Pat<SDPatternOperator OpNode, Instruction Instr> :
146  DSPPat<(i32 (OpNode CPURegs:$rs)), (Instr AC0, CPURegs:$rs)>;
147
148class EXTR_W_TY1_R1_Pat<SDPatternOperator OpNode, Instruction Instr> :
149  DSPPat<(i32 (OpNode immZExt5:$shift)), (Instr AC0, immZExt5:$shift)>;
150
151def : EXTR_W_TY1_R1_Pat<MipsEXTP, EXTP>;
152def : EXTR_W_TY1_R2_Pat<MipsEXTP, EXTPV>;
153def : EXTR_W_TY1_R1_Pat<MipsEXTPDP, EXTPDP>;
154def : EXTR_W_TY1_R2_Pat<MipsEXTPDP, EXTPDPV>;
155def : EXTR_W_TY1_R1_Pat<MipsEXTR_W, EXTR_W>;
156def : EXTR_W_TY1_R2_Pat<MipsEXTR_W, EXTRV_W>;
157def : EXTR_W_TY1_R1_Pat<MipsEXTR_R_W, EXTR_R_W>;
158def : EXTR_W_TY1_R2_Pat<MipsEXTR_R_W, EXTRV_R_W>;
159def : EXTR_W_TY1_R1_Pat<MipsEXTR_RS_W, EXTR_RS_W>;
160def : EXTR_W_TY1_R2_Pat<MipsEXTR_RS_W, EXTRV_RS_W>;
161def : EXTR_W_TY1_R1_Pat<MipsEXTR_S_H, EXTR_S_H>;
162def : EXTR_W_TY1_R2_Pat<MipsEXTR_S_H, EXTRV_S_H>;
163