MipsFrameLowering.cpp revision b7dd9fc678ab4b4c57d333cd9940b0e0d7952ea6
1//===-- MipsFrameLowering.cpp - Mips Frame Information --------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips implementation of TargetFrameLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "MipsFrameLowering.h" 15#include "MipsAnalyzeImmediate.h" 16#include "MipsInstrInfo.h" 17#include "MipsMachineFunction.h" 18#include "MCTargetDesc/MipsBaseInfo.h" 19#include "llvm/Function.h" 20#include "llvm/CodeGen/MachineFrameInfo.h" 21#include "llvm/CodeGen/MachineFunction.h" 22#include "llvm/CodeGen/MachineInstrBuilder.h" 23#include "llvm/CodeGen/MachineModuleInfo.h" 24#include "llvm/CodeGen/MachineRegisterInfo.h" 25#include "llvm/Target/TargetData.h" 26#include "llvm/Target/TargetOptions.h" 27#include "llvm/Support/CommandLine.h" 28 29using namespace llvm; 30 31 32//===----------------------------------------------------------------------===// 33// 34// Stack Frame Processing methods 35// +----------------------------+ 36// 37// The stack is allocated decrementing the stack pointer on 38// the first instruction of a function prologue. Once decremented, 39// all stack references are done thought a positive offset 40// from the stack/frame pointer, so the stack is considering 41// to grow up! Otherwise terrible hacks would have to be made 42// to get this stack ABI compliant :) 43// 44// The stack frame required by the ABI (after call): 45// Offset 46// 47// 0 ---------- 48// 4 Args to pass 49// . saved $GP (used in PIC) 50// . Alloca allocations 51// . Local Area 52// . CPU "Callee Saved" Registers 53// . saved FP 54// . saved RA 55// . FPU "Callee Saved" Registers 56// StackSize ----------- 57// 58// Offset - offset from sp after stack allocation on function prologue 59// 60// The sp is the stack pointer subtracted/added from the stack size 61// at the Prologue/Epilogue 62// 63// References to the previous stack (to obtain arguments) are done 64// with offsets that exceeds the stack size: (stacksize+(4*(num_arg-1)) 65// 66// Examples: 67// - reference to the actual stack frame 68// for any local area var there is smt like : FI >= 0, StackOffset: 4 69// sw REGX, 4(SP) 70// 71// - reference to previous stack frame 72// suppose there's a load to the 5th arguments : FI < 0, StackOffset: 16. 73// The emitted instruction will be something like: 74// lw REGX, 16+StackSize(SP) 75// 76// Since the total stack size is unknown on LowerFormalArguments, all 77// stack references (ObjectOffset) created to reference the function 78// arguments, are negative numbers. This way, on eliminateFrameIndex it's 79// possible to detect those references and the offsets are adjusted to 80// their real location. 81// 82//===----------------------------------------------------------------------===// 83 84// hasFP - Return true if the specified function should have a dedicated frame 85// pointer register. This is true if the function has variable sized allocas or 86// if frame pointer elimination is disabled. 87bool MipsFrameLowering::hasFP(const MachineFunction &MF) const { 88 const MachineFrameInfo *MFI = MF.getFrameInfo(); 89 return MF.getTarget().Options.DisableFramePointerElim(MF) || 90 MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken(); 91} 92 93bool MipsFrameLowering::targetHandlesStackFrameRounding() const { 94 return true; 95} 96 97void MipsFrameLowering::emitPrologue(MachineFunction &MF) const { 98 MachineBasicBlock &MBB = MF.front(); 99 MachineFrameInfo *MFI = MF.getFrameInfo(); 100 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 101 const MipsRegisterInfo *RegInfo = 102 static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo()); 103 const MipsInstrInfo &TII = 104 *static_cast<const MipsInstrInfo*>(MF.getTarget().getInstrInfo()); 105 MachineBasicBlock::iterator MBBI = MBB.begin(); 106 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); 107 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP; 108 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP; 109 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; 110 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu; 111 unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu; 112 113 // First, compute final stack size. 114 unsigned StackAlign = getStackAlignment(); 115 uint64_t StackSize = RoundUpToAlignment(MFI->getStackSize(), StackAlign); 116 117 if (MipsFI->globalBaseRegSet()) 118 StackSize += MFI->getObjectOffset(MipsFI->getGlobalRegFI()) + StackAlign; 119 else 120 StackSize += RoundUpToAlignment(MipsFI->getMaxCallFrameSize(), StackAlign); 121 122 // Update stack size 123 MFI->setStackSize(StackSize); 124 125 // No need to allocate space on the stack. 126 if (StackSize == 0 && !MFI->adjustsStack()) return; 127 128 MachineModuleInfo &MMI = MF.getMMI(); 129 std::vector<MachineMove> &Moves = MMI.getFrameMoves(); 130 MachineLocation DstML, SrcML; 131 132 // Adjust stack. 133 if (isInt<16>(-StackSize)) {// addi sp, sp, (-stacksize) 134 if (STI.inMips16Mode()) 135 BuildMI(MBB, MBBI, dl, 136 TII.get(Mips::SaveRaF16)).addImm(StackSize); // cleanup 137 else 138 BuildMI(MBB, MBBI, dl, TII.get(ADDiu), SP).addReg(SP).addImm(-StackSize); 139 } 140 else { // Expand immediate that doesn't fit in 16-bit. 141 unsigned ATReg = STI.isABI_N64() ? Mips::AT_64 : Mips::AT; 142 143 MF.getInfo<MipsFunctionInfo>()->setEmitNOAT(); 144 Mips::loadImmediate(-StackSize, STI.isABI_N64(), TII, MBB, MBBI, dl, false, 145 0); 146 BuildMI(MBB, MBBI, dl, TII.get(ADDu), SP).addReg(SP).addReg(ATReg); 147 } 148 149 // emit ".cfi_def_cfa_offset StackSize" 150 MCSymbol *AdjustSPLabel = MMI.getContext().CreateTempSymbol(); 151 BuildMI(MBB, MBBI, dl, 152 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(AdjustSPLabel); 153 DstML = MachineLocation(MachineLocation::VirtualFP); 154 SrcML = MachineLocation(MachineLocation::VirtualFP, -StackSize); 155 Moves.push_back(MachineMove(AdjustSPLabel, DstML, SrcML)); 156 157 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 158 159 if (CSI.size()) { 160 // Find the instruction past the last instruction that saves a callee-saved 161 // register to the stack. 162 for (unsigned i = 0; i < CSI.size(); ++i) 163 ++MBBI; 164 165 // Iterate over list of callee-saved registers and emit .cfi_offset 166 // directives. 167 MCSymbol *CSLabel = MMI.getContext().CreateTempSymbol(); 168 BuildMI(MBB, MBBI, dl, 169 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel); 170 171 for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(), 172 E = CSI.end(); I != E; ++I) { 173 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx()); 174 unsigned Reg = I->getReg(); 175 176 // If Reg is a double precision register, emit two cfa_offsets, 177 // one for each of the paired single precision registers. 178 if (Mips::AFGR64RegClass.contains(Reg)) { 179 MachineLocation DstML0(MachineLocation::VirtualFP, Offset); 180 MachineLocation DstML1(MachineLocation::VirtualFP, Offset + 4); 181 MachineLocation SrcML0(RegInfo->getSubReg(Reg, Mips::sub_fpeven)); 182 MachineLocation SrcML1(RegInfo->getSubReg(Reg, Mips::sub_fpodd)); 183 184 if (!STI.isLittle()) 185 std::swap(SrcML0, SrcML1); 186 187 Moves.push_back(MachineMove(CSLabel, DstML0, SrcML0)); 188 Moves.push_back(MachineMove(CSLabel, DstML1, SrcML1)); 189 } else { 190 // Reg is either in CPURegs or FGR32. 191 DstML = MachineLocation(MachineLocation::VirtualFP, Offset); 192 SrcML = MachineLocation(Reg); 193 Moves.push_back(MachineMove(CSLabel, DstML, SrcML)); 194 } 195 } 196 } 197 198 // if framepointer enabled, set it to point to the stack pointer. 199 if (hasFP(MF)) { 200 // Insert instruction "move $fp, $sp" at this location. 201 BuildMI(MBB, MBBI, dl, TII.get(ADDu), FP).addReg(SP).addReg(ZERO); 202 203 // emit ".cfi_def_cfa_register $fp" 204 MCSymbol *SetFPLabel = MMI.getContext().CreateTempSymbol(); 205 BuildMI(MBB, MBBI, dl, 206 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(SetFPLabel); 207 DstML = MachineLocation(FP); 208 SrcML = MachineLocation(MachineLocation::VirtualFP); 209 Moves.push_back(MachineMove(SetFPLabel, DstML, SrcML)); 210 } 211} 212 213void MipsFrameLowering::emitEpilogue(MachineFunction &MF, 214 MachineBasicBlock &MBB) const { 215 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 216 MachineFrameInfo *MFI = MF.getFrameInfo(); 217 const MipsInstrInfo &TII = 218 *static_cast<const MipsInstrInfo*>(MF.getTarget().getInstrInfo()); 219 DebugLoc dl = MBBI->getDebugLoc(); 220 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP; 221 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP; 222 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; 223 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu; 224 unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu; 225 226 // if framepointer enabled, restore the stack pointer. 227 if (hasFP(MF)) { 228 // Find the first instruction that restores a callee-saved register. 229 MachineBasicBlock::iterator I = MBBI; 230 231 for (unsigned i = 0; i < MFI->getCalleeSavedInfo().size(); ++i) 232 --I; 233 234 // Insert instruction "move $sp, $fp" at this location. 235 BuildMI(MBB, I, dl, TII.get(ADDu), SP).addReg(FP).addReg(ZERO); 236 } 237 238 // Get the number of bytes from FrameInfo 239 uint64_t StackSize = MFI->getStackSize(); 240 241 if (!StackSize) 242 return; 243 244 // Adjust stack. 245 if (isInt<16>(StackSize)) { // addi sp, sp, (-stacksize) 246 if (STI.inMips16Mode()) 247 // assumes stacksize multiple of 8 248 BuildMI(MBB, MBBI, dl, 249 TII.get(Mips::RestoreRaF16)).addImm(StackSize); 250 else 251 BuildMI(MBB, MBBI, dl, TII.get(ADDiu), SP).addReg(SP).addImm(StackSize); 252 } 253 else { // Expand immediate that doesn't fit in 16-bit. 254 unsigned ATReg = STI.isABI_N64() ? Mips::AT_64 : Mips::AT; 255 256 MF.getInfo<MipsFunctionInfo>()->setEmitNOAT(); 257 Mips::loadImmediate(StackSize, STI.isABI_N64(), TII, MBB, MBBI, dl, false, 258 0); 259 BuildMI(MBB, MBBI, dl, TII.get(ADDu), SP).addReg(SP).addReg(ATReg); 260 } 261} 262 263void MipsFrameLowering:: 264processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 265 RegScavenger *RS) const { 266 MachineRegisterInfo &MRI = MF.getRegInfo(); 267 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP; 268 269 // FIXME: remove this code if register allocator can correctly mark 270 // $fp and $ra used or unused. 271 272 // Mark $fp and $ra as used or unused. 273 if (hasFP(MF)) 274 MRI.setPhysRegUsed(FP); 275} 276 277bool MipsFrameLowering:: 278spillCalleeSavedRegisters(MachineBasicBlock &MBB, 279 MachineBasicBlock::iterator MI, 280 const std::vector<CalleeSavedInfo> &CSI, 281 const TargetRegisterInfo *TRI) const { 282 MachineFunction *MF = MBB.getParent(); 283 MachineBasicBlock *EntryBlock = MF->begin(); 284 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); 285 286 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 287 // Add the callee-saved register as live-in. Do not add if the register is 288 // RA and return address is taken, because it has already been added in 289 // method MipsTargetLowering::LowerRETURNADDR. 290 // It's killed at the spill, unless the register is RA and return address 291 // is taken. 292 unsigned Reg = CSI[i].getReg(); 293 bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA || Reg == Mips::RA_64) 294 && MF->getFrameInfo()->isReturnAddressTaken(); 295 if (!IsRAAndRetAddrIsTaken) 296 EntryBlock->addLiveIn(Reg); 297 298 // Insert the spill to the stack frame. 299 bool IsKill = !IsRAAndRetAddrIsTaken; 300 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 301 TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, 302 CSI[i].getFrameIdx(), RC, TRI); 303 } 304 305 return true; 306} 307