MipsISelDAGToDAG.cpp revision 4782a6e06ad4c6227831b70bb76165bc7b14bff3 
1//===-- MipsISelDAGToDAG.cpp - A Dag to Dag Inst Selector for Mips --------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines an instruction selector for the MIPS target.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "mips-isel"
15#include "Mips.h"
16#include "MipsAnalyzeImmediate.h"
17#include "MipsMachineFunction.h"
18#include "MipsRegisterInfo.h"
19#include "MipsSubtarget.h"
20#include "MipsTargetMachine.h"
21#include "MCTargetDesc/MipsBaseInfo.h"
22#include "llvm/GlobalValue.h"
23#include "llvm/Instructions.h"
24#include "llvm/Intrinsics.h"
25#include "llvm/Support/CFG.h"
26#include "llvm/Type.h"
27#include "llvm/CodeGen/MachineConstantPool.h"
28#include "llvm/CodeGen/MachineFunction.h"
29#include "llvm/CodeGen/MachineFrameInfo.h"
30#include "llvm/CodeGen/MachineInstrBuilder.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/CodeGen/SelectionDAGISel.h"
33#include "llvm/CodeGen/SelectionDAGNodes.h"
34#include "llvm/Target/TargetMachine.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/raw_ostream.h"
38using namespace llvm;
39
40//===----------------------------------------------------------------------===//
41// Instruction Selector Implementation
42//===----------------------------------------------------------------------===//
43
44//===----------------------------------------------------------------------===//
45// MipsDAGToDAGISel - MIPS specific code to select MIPS machine
46// instructions for SelectionDAG operations.
47//===----------------------------------------------------------------------===//
48namespace {
49
50class MipsDAGToDAGISel : public SelectionDAGISel {
51
52  /// TM - Keep a reference to MipsTargetMachine.
53  MipsTargetMachine &TM;
54
55  /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
56  /// make the right decision when generating code for different targets.
57  const MipsSubtarget &Subtarget;
58
59public:
60  explicit MipsDAGToDAGISel(MipsTargetMachine &tm) :
61  SelectionDAGISel(tm),
62  TM(tm), Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
63
64  // Pass Name
65  virtual const char *getPassName() const {
66    return "MIPS DAG->DAG Pattern Instruction Selection";
67  }
68
69  virtual bool runOnMachineFunction(MachineFunction &MF);
70
71private:
72  // Include the pieces autogenerated from the target description.
73  #include "MipsGenDAGISel.inc"
74
75  /// getTargetMachine - Return a reference to the TargetMachine, casted
76  /// to the target-specific type.
77  const MipsTargetMachine &getTargetMachine() {
78    return static_cast<const MipsTargetMachine &>(TM);
79  }
80
81  /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
82  /// to the target-specific type.
83  const MipsInstrInfo *getInstrInfo() {
84    return getTargetMachine().getInstrInfo();
85  }
86
87  SDNode *getGlobalBaseReg();
88
89  std::pair<SDNode*, SDNode*> SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl,
90                                         EVT Ty, bool HasLo, bool HasHi);
91
92  SDNode *Select(SDNode *N);
93
94  // Complex Pattern.
95  bool SelectAddr(SDNode *Parent, SDValue N, SDValue &Base, SDValue &Offset);
96
97  // getImm - Return a target constant with the specified value.
98  inline SDValue getImm(const SDNode *Node, unsigned Imm) {
99    return CurDAG->getTargetConstant(Imm, Node->getValueType(0));
100  }
101
102  void ProcessFunctionAfterISel(MachineFunction &MF);
103  bool ReplaceUsesWithZeroReg(MachineRegisterInfo *MRI, const MachineInstr&);
104  void InitGlobalBaseReg(MachineFunction &MF);
105
106  virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
107                                            char ConstraintCode,
108                                            std::vector<SDValue> &OutOps);
109};
110
111}
112
113// Insert instructions to initialize the global base register in the
114// first MBB of the function. When the ABI is O32 and the relocation model is
115// PIC, the necessary instructions are emitted later to prevent optimization
116// passes from moving them.
117void MipsDAGToDAGISel::InitGlobalBaseReg(MachineFunction &MF) {
118  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
119
120  if (((MF.getTarget().getRelocationModel() == Reloc::Static) ||
121       Subtarget.inMips16Mode()) && !MipsFI->globalBaseRegSet())
122    return;
123
124  MachineBasicBlock &MBB = MF.front();
125  MachineBasicBlock::iterator I = MBB.begin();
126  MachineRegisterInfo &RegInfo = MF.getRegInfo();
127  const MipsRegisterInfo *TargetRegInfo = TM.getRegisterInfo();
128  const MipsInstrInfo *MII = TM.getInstrInfo();
129  const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
130  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
131  unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
132  int FI;  // should initialize this to some kind of null
133
134  if (!Subtarget.inMips16Mode())
135    FI= MipsFI->initGlobalRegFI();
136
137  const TargetRegisterClass *RC = Subtarget.isABI_N64() ?
138    (const TargetRegisterClass*)&Mips::CPU64RegsRegClass :
139    (const TargetRegisterClass*)&Mips::CPURegsRegClass;
140
141  V0 = RegInfo.createVirtualRegister(RC);
142  V1 = RegInfo.createVirtualRegister(RC);
143
144  if (Subtarget.isABI_N64()) {
145    MF.getRegInfo().addLiveIn(Mips::T9_64);
146    MBB.addLiveIn(Mips::T9_64);
147
148    // lui $v0, %hi(%neg(%gp_rel(fname)))
149    // daddu $v1, $v0, $t9
150    // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
151    const GlobalValue *FName = MF.getFunction();
152    BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
153      .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
154    BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
155      .addReg(Mips::T9_64);
156    BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
157      .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
158    MII->storeRegToStackSlot(MBB, I, GlobalBaseReg, false, FI, RC,
159                             TargetRegInfo);
160    return;
161  }
162
163  if (MF.getTarget().getRelocationModel() == Reloc::Static) {
164    // Set global register to __gnu_local_gp.
165    //
166    // lui   $v0, %hi(__gnu_local_gp)
167    // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
168    BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
169      .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI);
170    BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
171      .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO);
172    MII->storeRegToStackSlot(MBB, I, GlobalBaseReg, false, FI, RC,
173                             TargetRegInfo);
174    return;
175  }
176
177  MF.getRegInfo().addLiveIn(Mips::T9);
178  MBB.addLiveIn(Mips::T9);
179
180  if (Subtarget.isABI_N32()) {
181    // lui $v0, %hi(%neg(%gp_rel(fname)))
182    // addu $v1, $v0, $t9
183    // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
184    const GlobalValue *FName = MF.getFunction();
185    BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
186      .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
187    BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
188    BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
189      .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
190    MII->storeRegToStackSlot(MBB, I, GlobalBaseReg, false, FI, RC,
191                             TargetRegInfo);
192    return;
193  }
194
195  assert(Subtarget.isABI_O32());
196
197  if (Subtarget.inMips16Mode())
198    return; // no need to load GP. It can be calculated anywhere
199
200
201  // For O32 ABI, the following instruction sequence is emitted to initialize
202  // the global base register:
203  //
204  //  0. lui   $2, %hi(_gp_disp)
205  //  1. addiu $2, $2, %lo(_gp_disp)
206  //  2. addu  $globalbasereg, $2, $t9
207  //
208  // We emit only the last instruction here.
209  //
210  // GNU linker requires that the first two instructions appear at the beginning
211  // of a function and no instructions be inserted before or between them.
212  // The two instructions are emitted during lowering to MC layer in order to
213  // avoid any reordering.
214  //
215  // Register $2 (Mips::V0) is added to the list of live-in registers to ensure
216  // the value instruction 1 (addiu) defines is valid when instruction 2 (addu)
217  // reads it.
218  MF.getRegInfo().addLiveIn(Mips::V0);
219  MBB.addLiveIn(Mips::V0);
220  BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
221    .addReg(Mips::V0).addReg(Mips::T9);
222  MII->storeRegToStackSlot(MBB, I, GlobalBaseReg, false, FI, RC, TargetRegInfo);
223}
224
225bool MipsDAGToDAGISel::ReplaceUsesWithZeroReg(MachineRegisterInfo *MRI,
226                                              const MachineInstr& MI) {
227  unsigned DstReg = 0, ZeroReg = 0;
228
229  // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
230  if ((MI.getOpcode() == Mips::ADDiu) &&
231      (MI.getOperand(1).getReg() == Mips::ZERO) &&
232      (MI.getOperand(2).getImm() == 0)) {
233    DstReg = MI.getOperand(0).getReg();
234    ZeroReg = Mips::ZERO;
235  } else if ((MI.getOpcode() == Mips::DADDiu) &&
236             (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
237             (MI.getOperand(2).getImm() == 0)) {
238    DstReg = MI.getOperand(0).getReg();
239    ZeroReg = Mips::ZERO_64;
240  }
241
242  if (!DstReg)
243    return false;
244
245  // Replace uses with ZeroReg.
246  for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
247       E = MRI->use_end(); U != E; ++U) {
248    MachineOperand &MO = U.getOperand();
249    MachineInstr *MI = MO.getParent();
250
251    // Do not replace if it is a phi's operand or is tied to def operand.
252    if (MI->isPHI() || MI->isRegTiedToDefOperand(U.getOperandNo()) ||
253        MI->isPseudo())
254      continue;
255
256    MO.setReg(ZeroReg);
257  }
258
259  return true;
260}
261
262void MipsDAGToDAGISel::ProcessFunctionAfterISel(MachineFunction &MF) {
263  InitGlobalBaseReg(MF);
264
265  MachineRegisterInfo *MRI = &MF.getRegInfo();
266
267  for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end(); MFI != MFE;
268       ++MFI)
269    for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I)
270      ReplaceUsesWithZeroReg(MRI, *I);
271}
272
273bool MipsDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
274  bool Ret = SelectionDAGISel::runOnMachineFunction(MF);
275
276  ProcessFunctionAfterISel(MF);
277
278  return Ret;
279}
280
281/// getGlobalBaseReg - Output the instructions required to put the
282/// GOT address into a register.
283SDNode *MipsDAGToDAGISel::getGlobalBaseReg() {
284  unsigned GlobalBaseReg = MF->getInfo<MipsFunctionInfo>()->getGlobalBaseReg();
285  return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
286}
287
288/// ComplexPattern used on MipsInstrInfo
289/// Used on Mips Load/Store instructions
290bool MipsDAGToDAGISel::
291SelectAddr(SDNode *Parent, SDValue Addr, SDValue &Base, SDValue &Offset) {
292  EVT ValTy = Addr.getValueType();
293
294  // If Parent is an unaligned f32 load or store, select a (base + index)
295  // floating point load/store instruction (luxc1 or suxc1).
296  const LSBaseSDNode *LS = 0;
297
298  if (Parent && (LS = dyn_cast<LSBaseSDNode>(Parent))) {
299    EVT VT = LS->getMemoryVT();
300
301    if (VT.getSizeInBits() / 8 > LS->getAlignment()) {
302      assert(TLI.allowsUnalignedMemoryAccesses(VT) &&
303             "Unaligned loads/stores not supported for this type.");
304      if (VT == MVT::f32)
305        return false;
306    }
307  }
308
309  // if Address is FI, get the TargetFrameIndex.
310  if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
311    Base   = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
312    Offset = CurDAG->getTargetConstant(0, ValTy);
313    return true;
314  }
315
316  // on PIC code Load GA
317  if (Addr.getOpcode() == MipsISD::Wrapper) {
318    Base   = Addr.getOperand(0);
319    Offset = Addr.getOperand(1);
320    return true;
321  }
322
323  if (TM.getRelocationModel() != Reloc::PIC_) {
324    if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
325        Addr.getOpcode() == ISD::TargetGlobalAddress))
326      return false;
327  }
328
329  // Addresses of the form FI+const or FI|const
330  if (CurDAG->isBaseWithConstantOffset(Addr)) {
331    ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
332    if (isInt<16>(CN->getSExtValue())) {
333
334      // If the first operand is a FI, get the TargetFI Node
335      if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
336                                  (Addr.getOperand(0)))
337        Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
338      else
339        Base = Addr.getOperand(0);
340
341      Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
342      return true;
343    }
344  }
345
346  // Operand is a result from an ADD.
347  if (Addr.getOpcode() == ISD::ADD) {
348    // When loading from constant pools, load the lower address part in
349    // the instruction itself. Example, instead of:
350    //  lui $2, %hi($CPI1_0)
351    //  addiu $2, $2, %lo($CPI1_0)
352    //  lwc1 $f0, 0($2)
353    // Generate:
354    //  lui $2, %hi($CPI1_0)
355    //  lwc1 $f0, %lo($CPI1_0)($2)
356    if (Addr.getOperand(1).getOpcode() == MipsISD::Lo) {
357      SDValue LoVal = Addr.getOperand(1), Opnd0 = LoVal.getOperand(0);
358      if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
359          isa<JumpTableSDNode>(Opnd0)) {
360        Base = Addr.getOperand(0);
361        Offset = Opnd0;
362        return true;
363      }
364    }
365
366    // If an indexed floating point load/store can be emitted, return false.
367    if (LS &&
368        (LS->getMemoryVT() == MVT::f32 || LS->getMemoryVT() == MVT::f64) &&
369        Subtarget.hasMips32r2Or64())
370      return false;
371  }
372
373  Base   = Addr;
374  Offset = CurDAG->getTargetConstant(0, ValTy);
375  return true;
376}
377
378/// Select multiply instructions.
379std::pair<SDNode*, SDNode*>
380MipsDAGToDAGISel::SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl, EVT Ty,
381                             bool HasLo, bool HasHi) {
382  SDNode *Lo = 0, *Hi = 0;
383  SDNode *Mul = CurDAG->getMachineNode(Opc, dl, MVT::Glue, N->getOperand(0),
384                                       N->getOperand(1));
385  SDValue InFlag = SDValue(Mul, 0);
386
387  if (HasLo) {
388    Lo = CurDAG->getMachineNode(Ty == MVT::i32 ? Mips::MFLO : Mips::MFLO64, dl,
389                                Ty, MVT::Glue, InFlag);
390    InFlag = SDValue(Lo, 1);
391  }
392  if (HasHi)
393    Hi = CurDAG->getMachineNode(Ty == MVT::i32 ? Mips::MFHI : Mips::MFHI64, dl,
394                                Ty, InFlag);
395
396  return std::make_pair(Lo, Hi);
397}
398
399
400/// Select instructions not customized! Used for
401/// expanded, promoted and normal instructions
402SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
403  unsigned Opcode = Node->getOpcode();
404  DebugLoc dl = Node->getDebugLoc();
405
406  // Dump information about the Node being selected
407  DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
408
409  // If we have a custom node, we already have selected!
410  if (Node->isMachineOpcode()) {
411    DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
412    return NULL;
413  }
414
415  ///
416  // Instruction Selection not handled by the auto-generated
417  // tablegen selection should be handled here.
418  ///
419  EVT NodeTy = Node->getValueType(0);
420  unsigned MultOpc;
421
422  switch(Opcode) {
423  default: break;
424
425  case ISD::SUBE:
426  case ISD::ADDE: {
427    SDValue InFlag = Node->getOperand(2), CmpLHS;
428    unsigned Opc = InFlag.getOpcode(); (void)Opc;
429    assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
430            (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
431           "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
432
433    unsigned MOp;
434    if (Opcode == ISD::ADDE) {
435      CmpLHS = InFlag.getValue(0);
436      MOp = Mips::ADDu;
437    } else {
438      CmpLHS = InFlag.getOperand(0);
439      MOp = Mips::SUBu;
440    }
441
442    SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
443
444    SDValue LHS = Node->getOperand(0);
445    SDValue RHS = Node->getOperand(1);
446
447    EVT VT = LHS.getValueType();
448    SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, dl, VT, Ops, 2);
449    SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT,
450                                              SDValue(Carry,0), RHS);
451
452    return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue,
453                                LHS, SDValue(AddCarry,0));
454  }
455
456  /// Mul with two results
457  case ISD::SMUL_LOHI:
458  case ISD::UMUL_LOHI: {
459    if (NodeTy == MVT::i32)
460      MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT);
461    else
462      MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::DMULTu : Mips::DMULT);
463
464    std::pair<SDNode*, SDNode*> LoHi = SelectMULT(Node, MultOpc, dl, NodeTy,
465                                                  true, true);
466
467    if (!SDValue(Node, 0).use_empty())
468      ReplaceUses(SDValue(Node, 0), SDValue(LoHi.first, 0));
469
470    if (!SDValue(Node, 1).use_empty())
471      ReplaceUses(SDValue(Node, 1), SDValue(LoHi.second, 0));
472
473    return NULL;
474  }
475
476  /// Special Muls
477  case ISD::MUL: {
478    // Mips32 has a 32-bit three operand mul instruction.
479    if (Subtarget.hasMips32() && NodeTy == MVT::i32)
480      break;
481    return SelectMULT(Node, NodeTy == MVT::i32 ? Mips::MULT : Mips::DMULT,
482                      dl, NodeTy, true, false).first;
483  }
484  case ISD::MULHS:
485  case ISD::MULHU: {
486    if (NodeTy == MVT::i32)
487      MultOpc = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
488    else
489      MultOpc = (Opcode == ISD::MULHU ? Mips::DMULTu : Mips::DMULT);
490
491    return SelectMULT(Node, MultOpc, dl, NodeTy, false, true).second;
492  }
493
494  // Get target GOT address.
495  case ISD::GLOBAL_OFFSET_TABLE:
496    return getGlobalBaseReg();
497
498  case ISD::ConstantFP: {
499    ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
500    if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
501      if (Subtarget.hasMips64()) {
502        SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
503                                              Mips::ZERO_64, MVT::i64);
504        return CurDAG->getMachineNode(Mips::DMTC1, dl, MVT::f64, Zero);
505      }
506
507      SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
508                                            Mips::ZERO, MVT::i32);
509      return CurDAG->getMachineNode(Mips::BuildPairF64, dl, MVT::f64, Zero,
510                                    Zero);
511    }
512    break;
513  }
514
515  case ISD::Constant: {
516    const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
517    unsigned Size = CN->getValueSizeInBits(0);
518
519    if (Size == 32)
520      break;
521
522    MipsAnalyzeImmediate AnalyzeImm;
523    int64_t Imm = CN->getSExtValue();
524
525    const MipsAnalyzeImmediate::InstSeq &Seq =
526      AnalyzeImm.Analyze(Imm, Size, false);
527
528    MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
529    DebugLoc DL = CN->getDebugLoc();
530    SDNode *RegOpnd;
531    SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
532                                                MVT::i64);
533
534    // The first instruction can be a LUi which is different from other
535    // instructions (ADDiu, ORI and SLL) in that it does not have a register
536    // operand.
537    if (Inst->Opc == Mips::LUi64)
538      RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
539    else
540      RegOpnd =
541        CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
542                               CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
543                               ImmOpnd);
544
545    // The remaining instructions in the sequence are handled here.
546    for (++Inst; Inst != Seq.end(); ++Inst) {
547      ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
548                                          MVT::i64);
549      RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
550                                       SDValue(RegOpnd, 0), ImmOpnd);
551    }
552
553    return RegOpnd;
554  }
555
556  case MipsISD::ThreadPointer: {
557    EVT PtrVT = TLI.getPointerTy();
558    unsigned RdhwrOpc, SrcReg, DestReg;
559
560    if (PtrVT == MVT::i32) {
561      RdhwrOpc = Mips::RDHWR;
562      SrcReg = Mips::HWR29;
563      DestReg = Mips::V1;
564    } else {
565      RdhwrOpc = Mips::RDHWR64;
566      SrcReg = Mips::HWR29_64;
567      DestReg = Mips::V1_64;
568    }
569
570    SDNode *Rdhwr =
571      CurDAG->getMachineNode(RdhwrOpc, Node->getDebugLoc(),
572                             Node->getValueType(0),
573                             CurDAG->getRegister(SrcReg, PtrVT));
574    SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, DestReg,
575                                         SDValue(Rdhwr, 0));
576    SDValue ResNode = CurDAG->getCopyFromReg(Chain, dl, DestReg, PtrVT);
577    ReplaceUses(SDValue(Node, 0), ResNode);
578    return ResNode.getNode();
579  }
580  }
581
582  // Select the default instruction
583  SDNode *ResNode = SelectCode(Node);
584
585  DEBUG(errs() << "=> ");
586  if (ResNode == NULL || ResNode == Node)
587    DEBUG(Node->dump(CurDAG));
588  else
589    DEBUG(ResNode->dump(CurDAG));
590  DEBUG(errs() << "\n");
591  return ResNode;
592}
593
594bool MipsDAGToDAGISel::
595SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
596                             std::vector<SDValue> &OutOps) {
597  assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
598  OutOps.push_back(Op);
599  return false;
600}
601
602/// createMipsISelDag - This pass converts a legalized DAG into a
603/// MIPS-specific DAG, ready for instruction scheduling.
604FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) {
605  return new MipsDAGToDAGISel(TM);
606}
607