MipsISelDAGToDAG.cpp revision 5a7dd43f045f2f78adc81b497c5d78bd9da0884e 
1//===-- MipsISelDAGToDAG.cpp - A Dag to Dag Inst Selector for Mips --------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines an instruction selector for the MIPS target.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "mips-isel"
15#include "Mips.h"
16#include "MipsAnalyzeImmediate.h"
17#include "MipsMachineFunction.h"
18#include "MipsRegisterInfo.h"
19#include "MipsSubtarget.h"
20#include "MipsTargetMachine.h"
21#include "MCTargetDesc/MipsBaseInfo.h"
22#include "llvm/GlobalValue.h"
23#include "llvm/Instructions.h"
24#include "llvm/Intrinsics.h"
25#include "llvm/Support/CFG.h"
26#include "llvm/Type.h"
27#include "llvm/CodeGen/MachineConstantPool.h"
28#include "llvm/CodeGen/MachineFunction.h"
29#include "llvm/CodeGen/MachineFrameInfo.h"
30#include "llvm/CodeGen/MachineInstrBuilder.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/CodeGen/SelectionDAGISel.h"
33#include "llvm/CodeGen/SelectionDAGNodes.h"
34#include "llvm/Target/TargetMachine.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/raw_ostream.h"
38using namespace llvm;
39
40//===----------------------------------------------------------------------===//
41// Instruction Selector Implementation
42//===----------------------------------------------------------------------===//
43
44//===----------------------------------------------------------------------===//
45// MipsDAGToDAGISel - MIPS specific code to select MIPS machine
46// instructions for SelectionDAG operations.
47//===----------------------------------------------------------------------===//
48namespace {
49
50class MipsDAGToDAGISel : public SelectionDAGISel {
51
52  /// TM - Keep a reference to MipsTargetMachine.
53  MipsTargetMachine &TM;
54
55  /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
56  /// make the right decision when generating code for different targets.
57  const MipsSubtarget &Subtarget;
58
59public:
60  explicit MipsDAGToDAGISel(MipsTargetMachine &tm) :
61  SelectionDAGISel(tm),
62  TM(tm), Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
63
64  // Pass Name
65  virtual const char *getPassName() const {
66    return "MIPS DAG->DAG Pattern Instruction Selection";
67  }
68
69  virtual bool runOnMachineFunction(MachineFunction &MF);
70
71private:
72  // Include the pieces autogenerated from the target description.
73  #include "MipsGenDAGISel.inc"
74
75  /// getTargetMachine - Return a reference to the TargetMachine, casted
76  /// to the target-specific type.
77  const MipsTargetMachine &getTargetMachine() {
78    return static_cast<const MipsTargetMachine &>(TM);
79  }
80
81  /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
82  /// to the target-specific type.
83  const MipsInstrInfo *getInstrInfo() {
84    return getTargetMachine().getInstrInfo();
85  }
86
87  SDNode *getGlobalBaseReg();
88
89  std::pair<SDNode*, SDNode*> SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl,
90                                         EVT Ty, bool HasLo, bool HasHi);
91
92  SDNode *Select(SDNode *N);
93
94  // Complex Pattern.
95  bool SelectAddr(SDNode *Parent, SDValue N, SDValue &Base, SDValue &Offset);
96
97  // getImm - Return a target constant with the specified value.
98  inline SDValue getImm(const SDNode *Node, unsigned Imm) {
99    return CurDAG->getTargetConstant(Imm, Node->getValueType(0));
100  }
101
102  void ProcessFunctionAfterISel(MachineFunction &MF);
103  bool ReplaceUsesWithZeroReg(MachineRegisterInfo *MRI, const MachineInstr&);
104  void InitGlobalBaseReg(MachineFunction &MF);
105
106  virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
107                                            char ConstraintCode,
108                                            std::vector<SDValue> &OutOps);
109};
110
111}
112
113// Insert instructions to initialize the global base register in the
114// first MBB of the function. When the ABI is O32 and the relocation model is
115// PIC, the necessary instructions are emitted later to prevent optimization
116// passes from moving them.
117void MipsDAGToDAGISel::InitGlobalBaseReg(MachineFunction &MF) {
118  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
119
120  if (!MipsFI->globalBaseRegSet())
121    return;
122
123  MachineBasicBlock &MBB = MF.front();
124  MachineBasicBlock::iterator I = MBB.begin();
125  MachineRegisterInfo &RegInfo = MF.getRegInfo();
126  const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
127  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
128  unsigned V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg();
129  const TargetRegisterClass *RC;
130
131  if (Subtarget.isABI_N64())
132    RC = (const TargetRegisterClass*)&Mips::CPU64RegsRegClass;
133  else if (Subtarget.inMips16Mode())
134    RC = (const TargetRegisterClass*)&Mips::CPU16RegsRegClass;
135  else
136    RC = (const TargetRegisterClass*)&Mips::CPURegsRegClass;
137
138  V0 = RegInfo.createVirtualRegister(RC);
139  V1 = RegInfo.createVirtualRegister(RC);
140  V2 = RegInfo.createVirtualRegister(RC);
141
142  if (Subtarget.isABI_N64()) {
143    MF.getRegInfo().addLiveIn(Mips::T9_64);
144    MBB.addLiveIn(Mips::T9_64);
145
146    // lui $v0, %hi(%neg(%gp_rel(fname)))
147    // daddu $v1, $v0, $t9
148    // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
149    const GlobalValue *FName = MF.getFunction();
150    BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
151      .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
152    BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
153      .addReg(Mips::T9_64);
154    BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
155      .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
156    return;
157  }
158
159  if (Subtarget.inMips16Mode()) {
160    BuildMI(MBB, I, DL, TII.get(Mips::LiRxImmX16), V0)
161      .addExternalSymbol("_gp_disp", MipsII::MO_ABS_HI);
162    BuildMI(MBB, I, DL, TII.get(Mips::AddiuRxPcImmX16), V1)
163      .addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO);
164    BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16);
165    BuildMI(MBB, I, DL, TII.get(Mips::AdduRxRyRz16), GlobalBaseReg)
166      .addReg(V1).addReg(V2);
167    return;
168  }
169
170  if (MF.getTarget().getRelocationModel() == Reloc::Static) {
171    // Set global register to __gnu_local_gp.
172    //
173    // lui   $v0, %hi(__gnu_local_gp)
174    // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
175    BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
176      .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI);
177    BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
178      .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO);
179    return;
180  }
181
182  MF.getRegInfo().addLiveIn(Mips::T9);
183  MBB.addLiveIn(Mips::T9);
184
185  if (Subtarget.isABI_N32()) {
186    // lui $v0, %hi(%neg(%gp_rel(fname)))
187    // addu $v1, $v0, $t9
188    // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
189    const GlobalValue *FName = MF.getFunction();
190    BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
191      .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
192    BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
193    BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
194      .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
195    return;
196  }
197
198  assert(Subtarget.isABI_O32());
199
200  // For O32 ABI, the following instruction sequence is emitted to initialize
201  // the global base register:
202  //
203  //  0. lui   $2, %hi(_gp_disp)
204  //  1. addiu $2, $2, %lo(_gp_disp)
205  //  2. addu  $globalbasereg, $2, $t9
206  //
207  // We emit only the last instruction here.
208  //
209  // GNU linker requires that the first two instructions appear at the beginning
210  // of a function and no instructions be inserted before or between them.
211  // The two instructions are emitted during lowering to MC layer in order to
212  // avoid any reordering.
213  //
214  // Register $2 (Mips::V0) is added to the list of live-in registers to ensure
215  // the value instruction 1 (addiu) defines is valid when instruction 2 (addu)
216  // reads it.
217  MF.getRegInfo().addLiveIn(Mips::V0);
218  MBB.addLiveIn(Mips::V0);
219  BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
220    .addReg(Mips::V0).addReg(Mips::T9);
221}
222
223bool MipsDAGToDAGISel::ReplaceUsesWithZeroReg(MachineRegisterInfo *MRI,
224                                              const MachineInstr& MI) {
225  unsigned DstReg = 0, ZeroReg = 0;
226
227  // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
228  if ((MI.getOpcode() == Mips::ADDiu) &&
229      (MI.getOperand(1).getReg() == Mips::ZERO) &&
230      (MI.getOperand(2).getImm() == 0)) {
231    DstReg = MI.getOperand(0).getReg();
232    ZeroReg = Mips::ZERO;
233  } else if ((MI.getOpcode() == Mips::DADDiu) &&
234             (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
235             (MI.getOperand(2).getImm() == 0)) {
236    DstReg = MI.getOperand(0).getReg();
237    ZeroReg = Mips::ZERO_64;
238  }
239
240  if (!DstReg)
241    return false;
242
243  // Replace uses with ZeroReg.
244  for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
245       E = MRI->use_end(); U != E;) {
246    MachineOperand &MO = U.getOperand();
247    unsigned OpNo = U.getOperandNo();
248    MachineInstr *MI = MO.getParent();
249    ++U;
250
251    // Do not replace if it is a phi's operand or is tied to def operand.
252    if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo())
253      continue;
254
255    MO.setReg(ZeroReg);
256  }
257
258  return true;
259}
260
261void MipsDAGToDAGISel::ProcessFunctionAfterISel(MachineFunction &MF) {
262  InitGlobalBaseReg(MF);
263
264  MachineRegisterInfo *MRI = &MF.getRegInfo();
265
266  for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end(); MFI != MFE;
267       ++MFI)
268    for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I)
269      ReplaceUsesWithZeroReg(MRI, *I);
270}
271
272bool MipsDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
273  bool Ret = SelectionDAGISel::runOnMachineFunction(MF);
274
275  ProcessFunctionAfterISel(MF);
276
277  return Ret;
278}
279
280/// getGlobalBaseReg - Output the instructions required to put the
281/// GOT address into a register.
282SDNode *MipsDAGToDAGISel::getGlobalBaseReg() {
283  unsigned GlobalBaseReg = MF->getInfo<MipsFunctionInfo>()->getGlobalBaseReg();
284  return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
285}
286
287/// ComplexPattern used on MipsInstrInfo
288/// Used on Mips Load/Store instructions
289bool MipsDAGToDAGISel::
290SelectAddr(SDNode *Parent, SDValue Addr, SDValue &Base, SDValue &Offset) {
291  EVT ValTy = Addr.getValueType();
292
293  // if Address is FI, get the TargetFrameIndex.
294  if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
295    Base   = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
296    Offset = CurDAG->getTargetConstant(0, ValTy);
297    return true;
298  }
299
300  // on PIC code Load GA
301  if (Addr.getOpcode() == MipsISD::Wrapper) {
302    Base   = Addr.getOperand(0);
303    Offset = Addr.getOperand(1);
304    return true;
305  }
306
307  if (TM.getRelocationModel() != Reloc::PIC_) {
308    if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
309        Addr.getOpcode() == ISD::TargetGlobalAddress))
310      return false;
311  }
312
313  // Addresses of the form FI+const or FI|const
314  if (CurDAG->isBaseWithConstantOffset(Addr)) {
315    ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
316    if (isInt<16>(CN->getSExtValue())) {
317
318      // If the first operand is a FI, get the TargetFI Node
319      if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
320                                  (Addr.getOperand(0)))
321        Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
322      else
323        Base = Addr.getOperand(0);
324
325      Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
326      return true;
327    }
328  }
329
330  // Operand is a result from an ADD.
331  if (Addr.getOpcode() == ISD::ADD) {
332    // When loading from constant pools, load the lower address part in
333    // the instruction itself. Example, instead of:
334    //  lui $2, %hi($CPI1_0)
335    //  addiu $2, $2, %lo($CPI1_0)
336    //  lwc1 $f0, 0($2)
337    // Generate:
338    //  lui $2, %hi($CPI1_0)
339    //  lwc1 $f0, %lo($CPI1_0)($2)
340    if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
341        Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
342      SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
343      if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
344          isa<JumpTableSDNode>(Opnd0)) {
345        Base = Addr.getOperand(0);
346        Offset = Opnd0;
347        return true;
348      }
349    }
350
351    // If an indexed floating point load/store can be emitted, return false.
352    const LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(Parent);
353
354    if (LS &&
355        (LS->getMemoryVT() == MVT::f32 || LS->getMemoryVT() == MVT::f64) &&
356        Subtarget.hasMips32r2Or64())
357      return false;
358  }
359
360  Base   = Addr;
361  Offset = CurDAG->getTargetConstant(0, ValTy);
362  return true;
363}
364
365/// Select multiply instructions.
366std::pair<SDNode*, SDNode*>
367MipsDAGToDAGISel::SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl, EVT Ty,
368                             bool HasLo, bool HasHi) {
369  SDNode *Lo = 0, *Hi = 0;
370  SDNode *Mul = CurDAG->getMachineNode(Opc, dl, MVT::Glue, N->getOperand(0),
371                                       N->getOperand(1));
372  SDValue InFlag = SDValue(Mul, 0);
373
374  if (HasLo) {
375    Lo = CurDAG->getMachineNode(Ty == MVT::i32 ? Mips::MFLO : Mips::MFLO64, dl,
376                                Ty, MVT::Glue, InFlag);
377    InFlag = SDValue(Lo, 1);
378  }
379  if (HasHi)
380    Hi = CurDAG->getMachineNode(Ty == MVT::i32 ? Mips::MFHI : Mips::MFHI64, dl,
381                                Ty, InFlag);
382
383  return std::make_pair(Lo, Hi);
384}
385
386
387/// Select instructions not customized! Used for
388/// expanded, promoted and normal instructions
389SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
390  unsigned Opcode = Node->getOpcode();
391  DebugLoc dl = Node->getDebugLoc();
392
393  // Dump information about the Node being selected
394  DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
395
396  // If we have a custom node, we already have selected!
397  if (Node->isMachineOpcode()) {
398    DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
399    return NULL;
400  }
401
402  ///
403  // Instruction Selection not handled by the auto-generated
404  // tablegen selection should be handled here.
405  ///
406  EVT NodeTy = Node->getValueType(0);
407  unsigned MultOpc;
408
409  switch(Opcode) {
410  default: break;
411
412  case ISD::SUBE:
413  case ISD::ADDE: {
414    SDValue InFlag = Node->getOperand(2), CmpLHS;
415    unsigned Opc = InFlag.getOpcode(); (void)Opc;
416    assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
417            (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
418           "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
419
420    unsigned MOp;
421    if (Opcode == ISD::ADDE) {
422      CmpLHS = InFlag.getValue(0);
423      MOp = Mips::ADDu;
424    } else {
425      CmpLHS = InFlag.getOperand(0);
426      MOp = Mips::SUBu;
427    }
428
429    SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
430
431    SDValue LHS = Node->getOperand(0);
432    SDValue RHS = Node->getOperand(1);
433
434    EVT VT = LHS.getValueType();
435    SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, dl, VT, Ops, 2);
436    SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT,
437                                              SDValue(Carry,0), RHS);
438
439    return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue,
440                                LHS, SDValue(AddCarry,0));
441  }
442
443  /// Mul with two results
444  case ISD::SMUL_LOHI:
445  case ISD::UMUL_LOHI: {
446    if (NodeTy == MVT::i32)
447      MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT);
448    else
449      MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::DMULTu : Mips::DMULT);
450
451    std::pair<SDNode*, SDNode*> LoHi = SelectMULT(Node, MultOpc, dl, NodeTy,
452                                                  true, true);
453
454    if (!SDValue(Node, 0).use_empty())
455      ReplaceUses(SDValue(Node, 0), SDValue(LoHi.first, 0));
456
457    if (!SDValue(Node, 1).use_empty())
458      ReplaceUses(SDValue(Node, 1), SDValue(LoHi.second, 0));
459
460    return NULL;
461  }
462
463  /// Special Muls
464  case ISD::MUL: {
465    // Mips32 has a 32-bit three operand mul instruction.
466    if (Subtarget.hasMips32() && NodeTy == MVT::i32)
467      break;
468    return SelectMULT(Node, NodeTy == MVT::i32 ? Mips::MULT : Mips::DMULT,
469                      dl, NodeTy, true, false).first;
470  }
471  case ISD::MULHS:
472  case ISD::MULHU: {
473    if (NodeTy == MVT::i32)
474      MultOpc = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
475    else
476      MultOpc = (Opcode == ISD::MULHU ? Mips::DMULTu : Mips::DMULT);
477
478    return SelectMULT(Node, MultOpc, dl, NodeTy, false, true).second;
479  }
480
481  // Get target GOT address.
482  case ISD::GLOBAL_OFFSET_TABLE:
483    return getGlobalBaseReg();
484
485  case ISD::ConstantFP: {
486    ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
487    if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
488      if (Subtarget.hasMips64()) {
489        SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
490                                              Mips::ZERO_64, MVT::i64);
491        return CurDAG->getMachineNode(Mips::DMTC1, dl, MVT::f64, Zero);
492      }
493
494      SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
495                                            Mips::ZERO, MVT::i32);
496      return CurDAG->getMachineNode(Mips::BuildPairF64, dl, MVT::f64, Zero,
497                                    Zero);
498    }
499    break;
500  }
501
502  case ISD::Constant: {
503    const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
504    unsigned Size = CN->getValueSizeInBits(0);
505
506    if (Size == 32)
507      break;
508
509    MipsAnalyzeImmediate AnalyzeImm;
510    int64_t Imm = CN->getSExtValue();
511
512    const MipsAnalyzeImmediate::InstSeq &Seq =
513      AnalyzeImm.Analyze(Imm, Size, false);
514
515    MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
516    DebugLoc DL = CN->getDebugLoc();
517    SDNode *RegOpnd;
518    SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
519                                                MVT::i64);
520
521    // The first instruction can be a LUi which is different from other
522    // instructions (ADDiu, ORI and SLL) in that it does not have a register
523    // operand.
524    if (Inst->Opc == Mips::LUi64)
525      RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
526    else
527      RegOpnd =
528        CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
529                               CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
530                               ImmOpnd);
531
532    // The remaining instructions in the sequence are handled here.
533    for (++Inst; Inst != Seq.end(); ++Inst) {
534      ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
535                                          MVT::i64);
536      RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
537                                       SDValue(RegOpnd, 0), ImmOpnd);
538    }
539
540    return RegOpnd;
541  }
542
543#ifndef NDEBUG
544  case ISD::LOAD:
545  case ISD::STORE:
546    assert(cast<MemSDNode>(Node)->getMemoryVT().getSizeInBits() / 8 <=
547           cast<MemSDNode>(Node)->getAlignment() &&
548           "Unexpected unaligned loads/stores.");
549    break;
550#endif
551
552  case MipsISD::ThreadPointer: {
553    EVT PtrVT = TLI.getPointerTy();
554    unsigned RdhwrOpc, SrcReg, DestReg;
555
556    if (PtrVT == MVT::i32) {
557      RdhwrOpc = Mips::RDHWR;
558      SrcReg = Mips::HWR29;
559      DestReg = Mips::V1;
560    } else {
561      RdhwrOpc = Mips::RDHWR64;
562      SrcReg = Mips::HWR29_64;
563      DestReg = Mips::V1_64;
564    }
565
566    SDNode *Rdhwr =
567      CurDAG->getMachineNode(RdhwrOpc, Node->getDebugLoc(),
568                             Node->getValueType(0),
569                             CurDAG->getRegister(SrcReg, PtrVT));
570    SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, DestReg,
571                                         SDValue(Rdhwr, 0));
572    SDValue ResNode = CurDAG->getCopyFromReg(Chain, dl, DestReg, PtrVT);
573    ReplaceUses(SDValue(Node, 0), ResNode);
574    return ResNode.getNode();
575  }
576  }
577
578  // Select the default instruction
579  SDNode *ResNode = SelectCode(Node);
580
581  DEBUG(errs() << "=> ");
582  if (ResNode == NULL || ResNode == Node)
583    DEBUG(Node->dump(CurDAG));
584  else
585    DEBUG(ResNode->dump(CurDAG));
586  DEBUG(errs() << "\n");
587  return ResNode;
588}
589
590bool MipsDAGToDAGISel::
591SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
592                             std::vector<SDValue> &OutOps) {
593  assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
594  OutOps.push_back(Op);
595  return false;
596}
597
598/// createMipsISelDag - This pass converts a legalized DAG into a
599/// MIPS-specific DAG, ready for instruction scheduling.
600FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) {
601  return new MipsDAGToDAGISel(TM);
602}
603