MipsISelDAGToDAG.cpp revision c8a1fa77a73e7c885035421712ceba951f9024cb
1//===-- MipsISelDAGToDAG.cpp - A Dag to Dag Inst Selector for Mips --------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines an instruction selector for the MIPS target. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "mips-isel" 15#include "MipsISelDAGToDAG.h" 16#include "Mips16ISelDAGToDAG.h" 17#include "MipsSEISelDAGToDAG.h" 18#include "Mips.h" 19#include "MCTargetDesc/MipsBaseInfo.h" 20#include "MipsMachineFunction.h" 21#include "MipsRegisterInfo.h" 22#include "llvm/CodeGen/MachineConstantPool.h" 23#include "llvm/CodeGen/MachineFrameInfo.h" 24#include "llvm/CodeGen/MachineFunction.h" 25#include "llvm/CodeGen/MachineInstrBuilder.h" 26#include "llvm/CodeGen/MachineRegisterInfo.h" 27#include "llvm/CodeGen/SelectionDAGNodes.h" 28#include "llvm/IR/GlobalValue.h" 29#include "llvm/IR/Instructions.h" 30#include "llvm/IR/Intrinsics.h" 31#include "llvm/IR/Type.h" 32#include "llvm/Support/CFG.h" 33#include "llvm/Support/Debug.h" 34#include "llvm/Support/ErrorHandling.h" 35#include "llvm/Support/raw_ostream.h" 36#include "llvm/Target/TargetMachine.h" 37using namespace llvm; 38 39//===----------------------------------------------------------------------===// 40// Instruction Selector Implementation 41//===----------------------------------------------------------------------===// 42 43//===----------------------------------------------------------------------===// 44// MipsDAGToDAGISel - MIPS specific code to select MIPS machine 45// instructions for SelectionDAG operations. 46//===----------------------------------------------------------------------===// 47 48bool MipsDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) { 49 bool Ret = SelectionDAGISel::runOnMachineFunction(MF); 50 51 processFunctionAfterISel(MF); 52 53 return Ret; 54} 55 56/// getGlobalBaseReg - Output the instructions required to put the 57/// GOT address into a register. 58SDNode *MipsDAGToDAGISel::getGlobalBaseReg() { 59 unsigned GlobalBaseReg = MF->getInfo<MipsFunctionInfo>()->getGlobalBaseReg(); 60 return CurDAG->getRegister(GlobalBaseReg, 61 getTargetLowering()->getPointerTy()).getNode(); 62} 63 64/// ComplexPattern used on MipsInstrInfo 65/// Used on Mips Load/Store instructions 66bool MipsDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base, 67 SDValue &Offset) const { 68 llvm_unreachable("Unimplemented function."); 69 return false; 70} 71 72bool MipsDAGToDAGISel::selectAddrRegReg(SDValue Addr, SDValue &Base, 73 SDValue &Offset) const { 74 llvm_unreachable("Unimplemented function."); 75 return false; 76} 77 78bool MipsDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base, 79 SDValue &Offset) const { 80 llvm_unreachable("Unimplemented function."); 81 return false; 82} 83 84bool MipsDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base, 85 SDValue &Offset) const { 86 llvm_unreachable("Unimplemented function."); 87 return false; 88} 89 90bool MipsDAGToDAGISel::selectIntAddrMM(SDValue Addr, SDValue &Base, 91 SDValue &Offset) const { 92 llvm_unreachable("Unimplemented function."); 93 return false; 94} 95 96bool MipsDAGToDAGISel::selectAddr16(SDNode *Parent, SDValue N, SDValue &Base, 97 SDValue &Offset, SDValue &Alias) { 98 llvm_unreachable("Unimplemented function."); 99 return false; 100} 101 102bool MipsDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm) const { 103 llvm_unreachable("Unimplemented function."); 104 return false; 105} 106 107bool MipsDAGToDAGISel::selectVSplatUimm1(SDValue N, SDValue &Imm) const { 108 llvm_unreachable("Unimplemented function."); 109 return false; 110} 111 112bool MipsDAGToDAGISel::selectVSplatUimm2(SDValue N, SDValue &Imm) const { 113 llvm_unreachable("Unimplemented function."); 114 return false; 115} 116 117bool MipsDAGToDAGISel::selectVSplatUimm3(SDValue N, SDValue &Imm) const { 118 llvm_unreachable("Unimplemented function."); 119 return false; 120} 121 122bool MipsDAGToDAGISel::selectVSplatUimm4(SDValue N, SDValue &Imm) const { 123 llvm_unreachable("Unimplemented function."); 124 return false; 125} 126 127bool MipsDAGToDAGISel::selectVSplatUimm5(SDValue N, SDValue &Imm) const { 128 llvm_unreachable("Unimplemented function."); 129 return false; 130} 131 132bool MipsDAGToDAGISel::selectVSplatUimm6(SDValue N, SDValue &Imm) const { 133 llvm_unreachable("Unimplemented function."); 134 return false; 135} 136 137bool MipsDAGToDAGISel::selectVSplatUimm8(SDValue N, SDValue &Imm) const { 138 llvm_unreachable("Unimplemented function."); 139 return false; 140} 141 142bool MipsDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &Imm) const { 143 llvm_unreachable("Unimplemented function."); 144 return false; 145} 146 147bool MipsDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const { 148 llvm_unreachable("Unimplemented function."); 149 return false; 150} 151 152/// Select instructions not customized! Used for 153/// expanded, promoted and normal instructions 154SDNode* MipsDAGToDAGISel::Select(SDNode *Node) { 155 unsigned Opcode = Node->getOpcode(); 156 157 // Dump information about the Node being selected 158 DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n"); 159 160 // If we have a custom node, we already have selected! 161 if (Node->isMachineOpcode()) { 162 DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n"); 163 Node->setNodeId(-1); 164 return NULL; 165 } 166 167 // See if subclasses can handle this node. 168 std::pair<bool, SDNode*> Ret = selectNode(Node); 169 170 if (Ret.first) 171 return Ret.second; 172 173 switch(Opcode) { 174 default: break; 175 176 // Get target GOT address. 177 case ISD::GLOBAL_OFFSET_TABLE: 178 return getGlobalBaseReg(); 179 180#ifndef NDEBUG 181 case ISD::LOAD: 182 case ISD::STORE: 183 assert(cast<MemSDNode>(Node)->getMemoryVT().getSizeInBits() / 8 <= 184 cast<MemSDNode>(Node)->getAlignment() && 185 "Unexpected unaligned loads/stores."); 186 break; 187#endif 188 } 189 190 // Select the default instruction 191 SDNode *ResNode = SelectCode(Node); 192 193 DEBUG(errs() << "=> "); 194 if (ResNode == NULL || ResNode == Node) 195 DEBUG(Node->dump(CurDAG)); 196 else 197 DEBUG(ResNode->dump(CurDAG)); 198 DEBUG(errs() << "\n"); 199 return ResNode; 200} 201 202bool MipsDAGToDAGISel:: 203SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, 204 std::vector<SDValue> &OutOps) { 205 assert(ConstraintCode == 'm' && "unexpected asm memory constraint"); 206 OutOps.push_back(Op); 207 return false; 208} 209 210/// createMipsISelDag - This pass converts a legalized DAG into a 211/// MIPS-specific DAG, ready for instruction scheduling. 212FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) { 213 if (TM.getSubtargetImpl()->inMips16Mode()) 214 return llvm::createMips16ISelDag(TM); 215 216 return llvm::createMipsSEISelDag(TM); 217} 218