MipsISelLowering.cpp revision 8163ca76f0b0d336c5436364ffb3b85be1162e7a
1//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that Mips uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "mips-lower" 16#include "MipsISelLowering.h" 17#include "InstPrinter/MipsInstPrinter.h" 18#include "MCTargetDesc/MipsBaseInfo.h" 19#include "MipsMachineFunction.h" 20#include "MipsSubtarget.h" 21#include "MipsTargetMachine.h" 22#include "MipsTargetObjectFile.h" 23#include "llvm/ADT/Statistic.h" 24#include "llvm/CallingConv.h" 25#include "llvm/CodeGen/CallingConvLower.h" 26#include "llvm/CodeGen/MachineFrameInfo.h" 27#include "llvm/CodeGen/MachineFunction.h" 28#include "llvm/CodeGen/MachineInstrBuilder.h" 29#include "llvm/CodeGen/MachineRegisterInfo.h" 30#include "llvm/CodeGen/SelectionDAGISel.h" 31#include "llvm/CodeGen/ValueTypes.h" 32#include "llvm/DerivedTypes.h" 33#include "llvm/Function.h" 34#include "llvm/GlobalVariable.h" 35#include "llvm/Intrinsics.h" 36#include "llvm/Support/CommandLine.h" 37#include "llvm/Support/Debug.h" 38#include "llvm/Support/ErrorHandling.h" 39#include "llvm/Support/raw_ostream.h" 40 41using namespace llvm; 42 43STATISTIC(NumTailCalls, "Number of tail calls"); 44 45static cl::opt<bool> 46EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden, 47 cl::desc("MIPS: Enable tail calls."), cl::init(false)); 48 49static cl::opt<bool> 50LargeGOT("mxgot", cl::Hidden, 51 cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false)); 52 53static const uint16_t O32IntRegs[4] = { 54 Mips::A0, Mips::A1, Mips::A2, Mips::A3 55}; 56 57static const uint16_t Mips64IntRegs[8] = { 58 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, 59 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64 60}; 61 62static const uint16_t Mips64DPRegs[8] = { 63 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, 64 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64 65}; 66 67// If I is a shifted mask, set the size (Size) and the first bit of the 68// mask (Pos), and return true. 69// For example, if I is 0x003ff800, (Pos, Size) = (11, 11). 70static bool IsShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { 71 if (!isShiftedMask_64(I)) 72 return false; 73 74 Size = CountPopulation_64(I); 75 Pos = CountTrailingZeros_64(I); 76 return true; 77} 78 79static SDValue GetGlobalReg(SelectionDAG &DAG, EVT Ty) { 80 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>(); 81 return DAG.getRegister(FI->getGlobalBaseReg(), Ty); 82} 83 84static SDValue getTargetNode(SDValue Op, SelectionDAG &DAG, unsigned Flag) { 85 EVT Ty = Op.getValueType(); 86 87 if (GlobalAddressSDNode *N = dyn_cast<GlobalAddressSDNode>(Op)) 88 return DAG.getTargetGlobalAddress(N->getGlobal(), Op.getDebugLoc(), Ty, 0, 89 Flag); 90 if (ExternalSymbolSDNode *N = dyn_cast<ExternalSymbolSDNode>(Op)) 91 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag); 92 if (BlockAddressSDNode *N = dyn_cast<BlockAddressSDNode>(Op)) 93 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag); 94 if (JumpTableSDNode *N = dyn_cast<JumpTableSDNode>(Op)) 95 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag); 96 if (ConstantPoolSDNode *N = dyn_cast<ConstantPoolSDNode>(Op)) 97 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(), 98 N->getOffset(), Flag); 99 100 llvm_unreachable("Unexpected node type."); 101 return SDValue(); 102} 103 104static SDValue getAddrNonPIC(SDValue Op, SelectionDAG &DAG) { 105 DebugLoc DL = Op.getDebugLoc(); 106 EVT Ty = Op.getValueType(); 107 SDValue Hi = getTargetNode(Op, DAG, MipsII::MO_ABS_HI); 108 SDValue Lo = getTargetNode(Op, DAG, MipsII::MO_ABS_LO); 109 return DAG.getNode(ISD::ADD, DL, Ty, 110 DAG.getNode(MipsISD::Hi, DL, Ty, Hi), 111 DAG.getNode(MipsISD::Lo, DL, Ty, Lo)); 112} 113 114static SDValue getAddrLocal(SDValue Op, SelectionDAG &DAG, bool HasMips64) { 115 DebugLoc DL = Op.getDebugLoc(); 116 EVT Ty = Op.getValueType(); 117 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT; 118 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, GetGlobalReg(DAG, Ty), 119 getTargetNode(Op, DAG, GOTFlag)); 120 SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT, 121 MachinePointerInfo::getGOT(), false, false, false, 122 0); 123 unsigned LoFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO; 124 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty, getTargetNode(Op, DAG, LoFlag)); 125 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo); 126} 127 128static SDValue getAddrGlobal(SDValue Op, SelectionDAG &DAG, unsigned Flag) { 129 DebugLoc DL = Op.getDebugLoc(); 130 EVT Ty = Op.getValueType(); 131 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, GetGlobalReg(DAG, Ty), 132 getTargetNode(Op, DAG, Flag)); 133 return DAG.getLoad(Ty, DL, DAG.getEntryNode(), Tgt, 134 MachinePointerInfo::getGOT(), false, false, false, 0); 135} 136 137static SDValue getAddrGlobalLargeGOT(SDValue Op, SelectionDAG &DAG, 138 unsigned HiFlag, unsigned LoFlag) { 139 DebugLoc DL = Op.getDebugLoc(); 140 EVT Ty = Op.getValueType(); 141 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, Ty, getTargetNode(Op, DAG, HiFlag)); 142 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, GetGlobalReg(DAG, Ty)); 143 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi, 144 getTargetNode(Op, DAG, LoFlag)); 145 return DAG.getLoad(Ty, DL, DAG.getEntryNode(), Wrapper, 146 MachinePointerInfo::getGOT(), false, false, false, 0); 147} 148 149const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 150 switch (Opcode) { 151 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 152 case MipsISD::TailCall: return "MipsISD::TailCall"; 153 case MipsISD::Hi: return "MipsISD::Hi"; 154 case MipsISD::Lo: return "MipsISD::Lo"; 155 case MipsISD::GPRel: return "MipsISD::GPRel"; 156 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; 157 case MipsISD::Ret: return "MipsISD::Ret"; 158 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 159 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 160 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 161 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 162 case MipsISD::FPRound: return "MipsISD::FPRound"; 163 case MipsISD::MAdd: return "MipsISD::MAdd"; 164 case MipsISD::MAddu: return "MipsISD::MAddu"; 165 case MipsISD::MSub: return "MipsISD::MSub"; 166 case MipsISD::MSubu: return "MipsISD::MSubu"; 167 case MipsISD::DivRem: return "MipsISD::DivRem"; 168 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 169 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 170 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 171 case MipsISD::Wrapper: return "MipsISD::Wrapper"; 172 case MipsISD::Sync: return "MipsISD::Sync"; 173 case MipsISD::Ext: return "MipsISD::Ext"; 174 case MipsISD::Ins: return "MipsISD::Ins"; 175 case MipsISD::LWL: return "MipsISD::LWL"; 176 case MipsISD::LWR: return "MipsISD::LWR"; 177 case MipsISD::SWL: return "MipsISD::SWL"; 178 case MipsISD::SWR: return "MipsISD::SWR"; 179 case MipsISD::LDL: return "MipsISD::LDL"; 180 case MipsISD::LDR: return "MipsISD::LDR"; 181 case MipsISD::SDL: return "MipsISD::SDL"; 182 case MipsISD::SDR: return "MipsISD::SDR"; 183 case MipsISD::EXTP: return "MipsISD::EXTP"; 184 case MipsISD::EXTPDP: return "MipsISD::EXTPDP"; 185 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H"; 186 case MipsISD::EXTR_W: return "MipsISD::EXTR_W"; 187 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W"; 188 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W"; 189 case MipsISD::SHILO: return "MipsISD::SHILO"; 190 case MipsISD::MTHLIP: return "MipsISD::MTHLIP"; 191 case MipsISD::MULT: return "MipsISD::MULT"; 192 case MipsISD::MULTU: return "MipsISD::MULTU"; 193 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSPDSP"; 194 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP"; 195 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP"; 196 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP"; 197 default: return NULL; 198 } 199} 200 201MipsTargetLowering:: 202MipsTargetLowering(MipsTargetMachine &TM) 203 : TargetLowering(TM, new MipsTargetObjectFile()), 204 Subtarget(&TM.getSubtarget<MipsSubtarget>()), 205 HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()), 206 IsO32(Subtarget->isABI_O32()) { 207 208 // Mips does not have i1 type, so use i32 for 209 // setcc operations results (slt, sgt, ...). 210 setBooleanContents(ZeroOrOneBooleanContent); 211 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct? 212 213 // Set up the register classes 214 addRegisterClass(MVT::i32, &Mips::CPURegsRegClass); 215 216 if (HasMips64) 217 addRegisterClass(MVT::i64, &Mips::CPU64RegsRegClass); 218 219 if (Subtarget->inMips16Mode()) { 220 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass); 221 } 222 223 if (Subtarget->hasDSP()) { 224 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8}; 225 226 for (unsigned i = 0; i < array_lengthof(VecTys); ++i) { 227 addRegisterClass(VecTys[i], &Mips::DSPRegsRegClass); 228 229 // Expand all builtin opcodes. 230 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc) 231 setOperationAction(Opc, VecTys[i], Expand); 232 233 setOperationAction(ISD::LOAD, VecTys[i], Legal); 234 setOperationAction(ISD::STORE, VecTys[i], Legal); 235 setOperationAction(ISD::BITCAST, VecTys[i], Legal); 236 } 237 } 238 239 if (!TM.Options.UseSoftFloat) { 240 addRegisterClass(MVT::f32, &Mips::FGR32RegClass); 241 242 // When dealing with single precision only, use libcalls 243 if (!Subtarget->isSingleFloat()) { 244 if (HasMips64) 245 addRegisterClass(MVT::f64, &Mips::FGR64RegClass); 246 else 247 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass); 248 } 249 } 250 251 // Load extented operations for i1 types must be promoted 252 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 253 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 254 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 255 256 // MIPS doesn't have extending float->double load/store 257 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 258 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 259 260 // Used by legalize types to correctly generate the setcc result. 261 // Without this, every float setcc comes with a AND/OR with the result, 262 // we don't want this, since the fpcmp result goes to a flag register, 263 // which is used implicitly by brcond and select operations. 264 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 265 266 // Mips Custom Operations 267 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 268 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 269 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 270 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 271 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 272 setOperationAction(ISD::SELECT, MVT::f32, Custom); 273 setOperationAction(ISD::SELECT, MVT::f64, Custom); 274 setOperationAction(ISD::SELECT, MVT::i32, Custom); 275 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 276 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 277 setOperationAction(ISD::SETCC, MVT::f32, Custom); 278 setOperationAction(ISD::SETCC, MVT::f64, Custom); 279 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 280 setOperationAction(ISD::VASTART, MVT::Other, Custom); 281 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 282 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 283 if (Subtarget->inMips16Mode()) { 284 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); 285 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand); 286 } 287 else { 288 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom); 289 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); 290 } 291 if (!Subtarget->inMips16Mode()) { 292 setOperationAction(ISD::LOAD, MVT::i32, Custom); 293 setOperationAction(ISD::STORE, MVT::i32, Custom); 294 } 295 296 if (!TM.Options.NoNaNsFPMath) { 297 setOperationAction(ISD::FABS, MVT::f32, Custom); 298 setOperationAction(ISD::FABS, MVT::f64, Custom); 299 } 300 301 if (HasMips64) { 302 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 303 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 304 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 305 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 306 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 307 setOperationAction(ISD::SELECT, MVT::i64, Custom); 308 setOperationAction(ISD::LOAD, MVT::i64, Custom); 309 setOperationAction(ISD::STORE, MVT::i64, Custom); 310 } 311 312 if (!HasMips64) { 313 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 314 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 315 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 316 } 317 318 setOperationAction(ISD::ADD, MVT::i32, Custom); 319 if (HasMips64) 320 setOperationAction(ISD::ADD, MVT::i64, Custom); 321 322 setOperationAction(ISD::SDIV, MVT::i32, Expand); 323 setOperationAction(ISD::SREM, MVT::i32, Expand); 324 setOperationAction(ISD::UDIV, MVT::i32, Expand); 325 setOperationAction(ISD::UREM, MVT::i32, Expand); 326 setOperationAction(ISD::SDIV, MVT::i64, Expand); 327 setOperationAction(ISD::SREM, MVT::i64, Expand); 328 setOperationAction(ISD::UDIV, MVT::i64, Expand); 329 setOperationAction(ISD::UREM, MVT::i64, Expand); 330 331 // Operations not directly supported by Mips. 332 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 333 setOperationAction(ISD::BR_CC, MVT::Other, Expand); 334 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 335 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 336 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 337 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 338 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 339 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 340 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 341 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 342 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 343 setOperationAction(ISD::CTTZ, MVT::i64, Expand); 344 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 345 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 346 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 347 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 348 setOperationAction(ISD::ROTL, MVT::i32, Expand); 349 setOperationAction(ISD::ROTL, MVT::i64, Expand); 350 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 351 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 352 353 if (!Subtarget->hasMips32r2()) 354 setOperationAction(ISD::ROTR, MVT::i32, Expand); 355 356 if (!Subtarget->hasMips64r2()) 357 setOperationAction(ISD::ROTR, MVT::i64, Expand); 358 359 setOperationAction(ISD::FSIN, MVT::f32, Expand); 360 setOperationAction(ISD::FSIN, MVT::f64, Expand); 361 setOperationAction(ISD::FCOS, MVT::f32, Expand); 362 setOperationAction(ISD::FCOS, MVT::f64, Expand); 363 setOperationAction(ISD::FPOWI, MVT::f32, Expand); 364 setOperationAction(ISD::FPOW, MVT::f32, Expand); 365 setOperationAction(ISD::FPOW, MVT::f64, Expand); 366 setOperationAction(ISD::FLOG, MVT::f32, Expand); 367 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 368 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 369 setOperationAction(ISD::FEXP, MVT::f32, Expand); 370 setOperationAction(ISD::FMA, MVT::f32, Expand); 371 setOperationAction(ISD::FMA, MVT::f64, Expand); 372 setOperationAction(ISD::FREM, MVT::f32, Expand); 373 setOperationAction(ISD::FREM, MVT::f64, Expand); 374 375 if (!TM.Options.NoNaNsFPMath) { 376 setOperationAction(ISD::FNEG, MVT::f32, Expand); 377 setOperationAction(ISD::FNEG, MVT::f64, Expand); 378 } 379 380 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 381 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 382 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 383 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 384 385 setOperationAction(ISD::VAARG, MVT::Other, Expand); 386 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 387 setOperationAction(ISD::VAEND, MVT::Other, Expand); 388 389 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom); 390 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom); 391 392 // Use the default for now 393 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 394 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 395 396 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); 397 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); 398 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); 399 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); 400 401 if (Subtarget->inMips16Mode()) { 402 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand); 403 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand); 404 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand); 405 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand); 406 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand); 407 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand); 408 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand); 409 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand); 410 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand); 411 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand); 412 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand); 413 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand); 414 } 415 416 setInsertFencesForAtomic(true); 417 418 if (!Subtarget->hasSEInReg()) { 419 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 420 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 421 } 422 423 if (!Subtarget->hasBitCount()) { 424 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 425 setOperationAction(ISD::CTLZ, MVT::i64, Expand); 426 } 427 428 if (!Subtarget->hasSwap()) { 429 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 430 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 431 } 432 433 if (HasMips64) { 434 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom); 435 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom); 436 setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom); 437 setTruncStoreAction(MVT::i64, MVT::i32, Custom); 438 } 439 440 setTargetDAGCombine(ISD::ADDE); 441 setTargetDAGCombine(ISD::SUBE); 442 setTargetDAGCombine(ISD::SDIVREM); 443 setTargetDAGCombine(ISD::UDIVREM); 444 setTargetDAGCombine(ISD::SELECT); 445 setTargetDAGCombine(ISD::AND); 446 setTargetDAGCombine(ISD::OR); 447 setTargetDAGCombine(ISD::ADD); 448 449 setMinFunctionAlignment(HasMips64 ? 3 : 2); 450 451 setStackPointerRegisterToSaveRestore(IsN64 ? Mips::SP_64 : Mips::SP); 452 computeRegisterProperties(); 453 454 setExceptionPointerRegister(IsN64 ? Mips::A0_64 : Mips::A0); 455 setExceptionSelectorRegister(IsN64 ? Mips::A1_64 : Mips::A1); 456 457 maxStoresPerMemcpy = 16; 458} 459 460bool 461MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const { 462 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy; 463 464 if (Subtarget->inMips16Mode()) 465 return false; 466 467 switch (SVT) { 468 case MVT::i64: 469 case MVT::i32: 470 if (Fast) 471 *Fast = true; 472 return true; 473 default: 474 return false; 475 } 476} 477 478EVT MipsTargetLowering::getSetCCResultType(EVT VT) const { 479 return MVT::i32; 480} 481 482// SelectMadd - 483// Transforms a subgraph in CurDAG if the following pattern is found: 484// (addc multLo, Lo0), (adde multHi, Hi0), 485// where, 486// multHi/Lo: product of multiplication 487// Lo0: initial value of Lo register 488// Hi0: initial value of Hi register 489// Return true if pattern matching was successful. 490static bool SelectMadd(SDNode *ADDENode, SelectionDAG *CurDAG) { 491 // ADDENode's second operand must be a flag output of an ADDC node in order 492 // for the matching to be successful. 493 SDNode *ADDCNode = ADDENode->getOperand(2).getNode(); 494 495 if (ADDCNode->getOpcode() != ISD::ADDC) 496 return false; 497 498 SDValue MultHi = ADDENode->getOperand(0); 499 SDValue MultLo = ADDCNode->getOperand(0); 500 SDNode *MultNode = MultHi.getNode(); 501 unsigned MultOpc = MultHi.getOpcode(); 502 503 // MultHi and MultLo must be generated by the same node, 504 if (MultLo.getNode() != MultNode) 505 return false; 506 507 // and it must be a multiplication. 508 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 509 return false; 510 511 // MultLo amd MultHi must be the first and second output of MultNode 512 // respectively. 513 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 514 return false; 515 516 // Transform this to a MADD only if ADDENode and ADDCNode are the only users 517 // of the values of MultNode, in which case MultNode will be removed in later 518 // phases. 519 // If there exist users other than ADDENode or ADDCNode, this function returns 520 // here, which will result in MultNode being mapped to a single MULT 521 // instruction node rather than a pair of MULT and MADD instructions being 522 // produced. 523 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 524 return false; 525 526 SDValue Chain = CurDAG->getEntryNode(); 527 DebugLoc dl = ADDENode->getDebugLoc(); 528 529 // create MipsMAdd(u) node 530 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd; 531 532 SDValue MAdd = CurDAG->getNode(MultOpc, dl, MVT::Glue, 533 MultNode->getOperand(0),// Factor 0 534 MultNode->getOperand(1),// Factor 1 535 ADDCNode->getOperand(1),// Lo0 536 ADDENode->getOperand(1));// Hi0 537 538 // create CopyFromReg nodes 539 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32, 540 MAdd); 541 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl, 542 Mips::HI, MVT::i32, 543 CopyFromLo.getValue(2)); 544 545 // replace uses of adde and addc here 546 if (!SDValue(ADDCNode, 0).use_empty()) 547 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo); 548 549 if (!SDValue(ADDENode, 0).use_empty()) 550 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi); 551 552 return true; 553} 554 555// SelectMsub - 556// Transforms a subgraph in CurDAG if the following pattern is found: 557// (addc Lo0, multLo), (sube Hi0, multHi), 558// where, 559// multHi/Lo: product of multiplication 560// Lo0: initial value of Lo register 561// Hi0: initial value of Hi register 562// Return true if pattern matching was successful. 563static bool SelectMsub(SDNode *SUBENode, SelectionDAG *CurDAG) { 564 // SUBENode's second operand must be a flag output of an SUBC node in order 565 // for the matching to be successful. 566 SDNode *SUBCNode = SUBENode->getOperand(2).getNode(); 567 568 if (SUBCNode->getOpcode() != ISD::SUBC) 569 return false; 570 571 SDValue MultHi = SUBENode->getOperand(1); 572 SDValue MultLo = SUBCNode->getOperand(1); 573 SDNode *MultNode = MultHi.getNode(); 574 unsigned MultOpc = MultHi.getOpcode(); 575 576 // MultHi and MultLo must be generated by the same node, 577 if (MultLo.getNode() != MultNode) 578 return false; 579 580 // and it must be a multiplication. 581 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 582 return false; 583 584 // MultLo amd MultHi must be the first and second output of MultNode 585 // respectively. 586 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 587 return false; 588 589 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users 590 // of the values of MultNode, in which case MultNode will be removed in later 591 // phases. 592 // If there exist users other than SUBENode or SUBCNode, this function returns 593 // here, which will result in MultNode being mapped to a single MULT 594 // instruction node rather than a pair of MULT and MSUB instructions being 595 // produced. 596 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 597 return false; 598 599 SDValue Chain = CurDAG->getEntryNode(); 600 DebugLoc dl = SUBENode->getDebugLoc(); 601 602 // create MipsSub(u) node 603 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub; 604 605 SDValue MSub = CurDAG->getNode(MultOpc, dl, MVT::Glue, 606 MultNode->getOperand(0),// Factor 0 607 MultNode->getOperand(1),// Factor 1 608 SUBCNode->getOperand(0),// Lo0 609 SUBENode->getOperand(0));// Hi0 610 611 // create CopyFromReg nodes 612 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32, 613 MSub); 614 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl, 615 Mips::HI, MVT::i32, 616 CopyFromLo.getValue(2)); 617 618 // replace uses of sube and subc here 619 if (!SDValue(SUBCNode, 0).use_empty()) 620 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo); 621 622 if (!SDValue(SUBENode, 0).use_empty()) 623 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi); 624 625 return true; 626} 627 628static SDValue PerformADDECombine(SDNode *N, SelectionDAG &DAG, 629 TargetLowering::DAGCombinerInfo &DCI, 630 const MipsSubtarget *Subtarget) { 631 if (DCI.isBeforeLegalize()) 632 return SDValue(); 633 634 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 && 635 SelectMadd(N, &DAG)) 636 return SDValue(N, 0); 637 638 return SDValue(); 639} 640 641static SDValue PerformSUBECombine(SDNode *N, SelectionDAG &DAG, 642 TargetLowering::DAGCombinerInfo &DCI, 643 const MipsSubtarget *Subtarget) { 644 if (DCI.isBeforeLegalize()) 645 return SDValue(); 646 647 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 && 648 SelectMsub(N, &DAG)) 649 return SDValue(N, 0); 650 651 return SDValue(); 652} 653 654static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG &DAG, 655 TargetLowering::DAGCombinerInfo &DCI, 656 const MipsSubtarget *Subtarget) { 657 if (DCI.isBeforeLegalizeOps()) 658 return SDValue(); 659 660 EVT Ty = N->getValueType(0); 661 unsigned LO = (Ty == MVT::i32) ? Mips::LO : Mips::LO64; 662 unsigned HI = (Ty == MVT::i32) ? Mips::HI : Mips::HI64; 663 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem : 664 MipsISD::DivRemU; 665 DebugLoc dl = N->getDebugLoc(); 666 667 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue, 668 N->getOperand(0), N->getOperand(1)); 669 SDValue InChain = DAG.getEntryNode(); 670 SDValue InGlue = DivRem; 671 672 // insert MFLO 673 if (N->hasAnyUseOfValue(0)) { 674 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, LO, Ty, 675 InGlue); 676 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 677 InChain = CopyFromLo.getValue(1); 678 InGlue = CopyFromLo.getValue(2); 679 } 680 681 // insert MFHI 682 if (N->hasAnyUseOfValue(1)) { 683 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl, 684 HI, Ty, InGlue); 685 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 686 } 687 688 return SDValue(); 689} 690 691static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) { 692 switch (CC) { 693 default: llvm_unreachable("Unknown fp condition code!"); 694 case ISD::SETEQ: 695 case ISD::SETOEQ: return Mips::FCOND_OEQ; 696 case ISD::SETUNE: return Mips::FCOND_UNE; 697 case ISD::SETLT: 698 case ISD::SETOLT: return Mips::FCOND_OLT; 699 case ISD::SETGT: 700 case ISD::SETOGT: return Mips::FCOND_OGT; 701 case ISD::SETLE: 702 case ISD::SETOLE: return Mips::FCOND_OLE; 703 case ISD::SETGE: 704 case ISD::SETOGE: return Mips::FCOND_OGE; 705 case ISD::SETULT: return Mips::FCOND_ULT; 706 case ISD::SETULE: return Mips::FCOND_ULE; 707 case ISD::SETUGT: return Mips::FCOND_UGT; 708 case ISD::SETUGE: return Mips::FCOND_UGE; 709 case ISD::SETUO: return Mips::FCOND_UN; 710 case ISD::SETO: return Mips::FCOND_OR; 711 case ISD::SETNE: 712 case ISD::SETONE: return Mips::FCOND_ONE; 713 case ISD::SETUEQ: return Mips::FCOND_UEQ; 714 } 715} 716 717 718// Returns true if condition code has to be inverted. 719static bool InvertFPCondCode(Mips::CondCode CC) { 720 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 721 return false; 722 723 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 724 "Illegal Condition Code"); 725 726 return true; 727} 728 729// Creates and returns an FPCmp node from a setcc node. 730// Returns Op if setcc is not a floating point comparison. 731static SDValue CreateFPCmp(SelectionDAG &DAG, const SDValue &Op) { 732 // must be a SETCC node 733 if (Op.getOpcode() != ISD::SETCC) 734 return Op; 735 736 SDValue LHS = Op.getOperand(0); 737 738 if (!LHS.getValueType().isFloatingPoint()) 739 return Op; 740 741 SDValue RHS = Op.getOperand(1); 742 DebugLoc dl = Op.getDebugLoc(); 743 744 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 745 // node if necessary. 746 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 747 748 return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS, 749 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32)); 750} 751 752// Creates and returns a CMovFPT/F node. 753static SDValue CreateCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, 754 SDValue False, DebugLoc DL) { 755 bool invert = InvertFPCondCode((Mips::CondCode) 756 cast<ConstantSDNode>(Cond.getOperand(2)) 757 ->getSExtValue()); 758 759 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 760 True.getValueType(), True, False, Cond); 761} 762 763static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 764 TargetLowering::DAGCombinerInfo &DCI, 765 const MipsSubtarget *Subtarget) { 766 if (DCI.isBeforeLegalizeOps()) 767 return SDValue(); 768 769 SDValue SetCC = N->getOperand(0); 770 771 if ((SetCC.getOpcode() != ISD::SETCC) || 772 !SetCC.getOperand(0).getValueType().isInteger()) 773 return SDValue(); 774 775 SDValue False = N->getOperand(2); 776 EVT FalseTy = False.getValueType(); 777 778 if (!FalseTy.isInteger()) 779 return SDValue(); 780 781 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(False); 782 783 if (!CN || CN->getZExtValue()) 784 return SDValue(); 785 786 const DebugLoc DL = N->getDebugLoc(); 787 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 788 SDValue True = N->getOperand(1); 789 790 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 791 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 792 793 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); 794} 795 796static SDValue PerformANDCombine(SDNode *N, SelectionDAG &DAG, 797 TargetLowering::DAGCombinerInfo &DCI, 798 const MipsSubtarget *Subtarget) { 799 // Pattern match EXT. 800 // $dst = and ((sra or srl) $src , pos), (2**size - 1) 801 // => ext $dst, $src, size, pos 802 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2()) 803 return SDValue(); 804 805 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1); 806 unsigned ShiftRightOpc = ShiftRight.getOpcode(); 807 808 // Op's first operand must be a shift right. 809 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL) 810 return SDValue(); 811 812 // The second operand of the shift must be an immediate. 813 ConstantSDNode *CN; 814 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1)))) 815 return SDValue(); 816 817 uint64_t Pos = CN->getZExtValue(); 818 uint64_t SMPos, SMSize; 819 820 // Op's second operand must be a shifted mask. 821 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) || 822 !IsShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 823 return SDValue(); 824 825 // Return if the shifted mask does not start at bit 0 or the sum of its size 826 // and Pos exceeds the word's size. 827 EVT ValTy = N->getValueType(0); 828 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits()) 829 return SDValue(); 830 831 return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), ValTy, 832 ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32), 833 DAG.getConstant(SMSize, MVT::i32)); 834} 835 836static SDValue PerformORCombine(SDNode *N, SelectionDAG &DAG, 837 TargetLowering::DAGCombinerInfo &DCI, 838 const MipsSubtarget *Subtarget) { 839 // Pattern match INS. 840 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), 841 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 842 // => ins $dst, $src, size, pos, $src1 843 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2()) 844 return SDValue(); 845 846 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); 847 uint64_t SMPos0, SMSize0, SMPos1, SMSize1; 848 ConstantSDNode *CN; 849 850 // See if Op's first operand matches (and $src1 , mask0). 851 if (And0.getOpcode() != ISD::AND) 852 return SDValue(); 853 854 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) || 855 !IsShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0)) 856 return SDValue(); 857 858 // See if Op's second operand matches (and (shl $src, pos), mask1). 859 if (And1.getOpcode() != ISD::AND) 860 return SDValue(); 861 862 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || 863 !IsShiftedMask(CN->getZExtValue(), SMPos1, SMSize1)) 864 return SDValue(); 865 866 // The shift masks must have the same position and size. 867 if (SMPos0 != SMPos1 || SMSize0 != SMSize1) 868 return SDValue(); 869 870 SDValue Shl = And1.getOperand(0); 871 if (Shl.getOpcode() != ISD::SHL) 872 return SDValue(); 873 874 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1)))) 875 return SDValue(); 876 877 unsigned Shamt = CN->getZExtValue(); 878 879 // Return if the shift amount and the first bit position of mask are not the 880 // same. 881 EVT ValTy = N->getValueType(0); 882 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits())) 883 return SDValue(); 884 885 return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), ValTy, Shl.getOperand(0), 886 DAG.getConstant(SMPos0, MVT::i32), 887 DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0)); 888} 889 890static SDValue PerformADDCombine(SDNode *N, SelectionDAG &DAG, 891 TargetLowering::DAGCombinerInfo &DCI, 892 const MipsSubtarget *Subtarget) { 893 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) 894 895 if (DCI.isBeforeLegalizeOps()) 896 return SDValue(); 897 898 SDValue Add = N->getOperand(1); 899 900 if (Add.getOpcode() != ISD::ADD) 901 return SDValue(); 902 903 SDValue Lo = Add.getOperand(1); 904 905 if ((Lo.getOpcode() != MipsISD::Lo) || 906 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable)) 907 return SDValue(); 908 909 EVT ValTy = N->getValueType(0); 910 DebugLoc DL = N->getDebugLoc(); 911 912 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0), 913 Add.getOperand(0)); 914 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo); 915} 916 917SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 918 const { 919 SelectionDAG &DAG = DCI.DAG; 920 unsigned opc = N->getOpcode(); 921 922 switch (opc) { 923 default: break; 924 case ISD::ADDE: 925 return PerformADDECombine(N, DAG, DCI, Subtarget); 926 case ISD::SUBE: 927 return PerformSUBECombine(N, DAG, DCI, Subtarget); 928 case ISD::SDIVREM: 929 case ISD::UDIVREM: 930 return PerformDivRemCombine(N, DAG, DCI, Subtarget); 931 case ISD::SELECT: 932 return PerformSELECTCombine(N, DAG, DCI, Subtarget); 933 case ISD::AND: 934 return PerformANDCombine(N, DAG, DCI, Subtarget); 935 case ISD::OR: 936 return PerformORCombine(N, DAG, DCI, Subtarget); 937 case ISD::ADD: 938 return PerformADDCombine(N, DAG, DCI, Subtarget); 939 } 940 941 return SDValue(); 942} 943 944void 945MipsTargetLowering::LowerOperationWrapper(SDNode *N, 946 SmallVectorImpl<SDValue> &Results, 947 SelectionDAG &DAG) const { 948 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 949 950 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I) 951 Results.push_back(Res.getValue(I)); 952} 953 954void 955MipsTargetLowering::ReplaceNodeResults(SDNode *N, 956 SmallVectorImpl<SDValue> &Results, 957 SelectionDAG &DAG) const { 958 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 959 960 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I) 961 Results.push_back(Res.getValue(I)); 962} 963 964SDValue MipsTargetLowering:: 965LowerOperation(SDValue Op, SelectionDAG &DAG) const 966{ 967 switch (Op.getOpcode()) 968 { 969 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 970 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 971 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 972 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 973 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 974 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 975 case ISD::SELECT: return LowerSELECT(Op, DAG); 976 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 977 case ISD::SETCC: return LowerSETCC(Op, DAG); 978 case ISD::VASTART: return LowerVASTART(Op, DAG); 979 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 980 case ISD::FABS: return LowerFABS(Op, DAG); 981 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 982 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 983 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG); 984 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG); 985 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG); 986 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG, true); 987 case ISD::SRL_PARTS: return LowerShiftRightParts(Op, DAG, false); 988 case ISD::LOAD: return LowerLOAD(Op, DAG); 989 case ISD::STORE: return LowerSTORE(Op, DAG); 990 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 991 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG); 992 case ISD::ADD: return LowerADD(Op, DAG); 993 } 994 return SDValue(); 995} 996 997//===----------------------------------------------------------------------===// 998// Lower helper functions 999//===----------------------------------------------------------------------===// 1000 1001// AddLiveIn - This helper function adds the specified physical register to the 1002// MachineFunction as a live in value. It also creates a corresponding 1003// virtual register for it. 1004static unsigned 1005AddLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) 1006{ 1007 assert(RC->contains(PReg) && "Not the correct regclass!"); 1008 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 1009 MF.getRegInfo().addLiveIn(PReg, VReg); 1010 return VReg; 1011} 1012 1013// Get fp branch code (not opcode) from condition code. 1014static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) { 1015 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 1016 return Mips::BRANCH_T; 1017 1018 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 1019 "Invalid CondCode."); 1020 1021 return Mips::BRANCH_F; 1022} 1023 1024/* 1025static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB, 1026 DebugLoc dl, 1027 const MipsSubtarget *Subtarget, 1028 const TargetInstrInfo *TII, 1029 bool isFPCmp, unsigned Opc) { 1030 // There is no need to expand CMov instructions if target has 1031 // conditional moves. 1032 if (Subtarget->hasCondMov()) 1033 return BB; 1034 1035 // To "insert" a SELECT_CC instruction, we actually have to insert the 1036 // diamond control-flow pattern. The incoming instruction knows the 1037 // destination vreg to set, the condition code register to branch on, the 1038 // true/false values to select between, and a branch opcode to use. 1039 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1040 MachineFunction::iterator It = BB; 1041 ++It; 1042 1043 // thisMBB: 1044 // ... 1045 // TrueVal = ... 1046 // setcc r1, r2, r3 1047 // bNE r1, r0, copy1MBB 1048 // fallthrough --> copy0MBB 1049 MachineBasicBlock *thisMBB = BB; 1050 MachineFunction *F = BB->getParent(); 1051 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 1052 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 1053 F->insert(It, copy0MBB); 1054 F->insert(It, sinkMBB); 1055 1056 // Transfer the remainder of BB and its successor edges to sinkMBB. 1057 sinkMBB->splice(sinkMBB->begin(), BB, 1058 llvm::next(MachineBasicBlock::iterator(MI)), 1059 BB->end()); 1060 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 1061 1062 // Next, add the true and fallthrough blocks as its successors. 1063 BB->addSuccessor(copy0MBB); 1064 BB->addSuccessor(sinkMBB); 1065 1066 // Emit the right instruction according to the type of the operands compared 1067 if (isFPCmp) 1068 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB); 1069 else 1070 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg()) 1071 .addReg(Mips::ZERO).addMBB(sinkMBB); 1072 1073 // copy0MBB: 1074 // %FalseValue = ... 1075 // # fallthrough to sinkMBB 1076 BB = copy0MBB; 1077 1078 // Update machine-CFG edges 1079 BB->addSuccessor(sinkMBB); 1080 1081 // sinkMBB: 1082 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 1083 // ... 1084 BB = sinkMBB; 1085 1086 if (isFPCmp) 1087 BuildMI(*BB, BB->begin(), dl, 1088 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 1089 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB) 1090 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB); 1091 else 1092 BuildMI(*BB, BB->begin(), dl, 1093 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 1094 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB) 1095 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB); 1096 1097 MI->eraseFromParent(); // The pseudo instruction is gone now. 1098 return BB; 1099} 1100*/ 1101 1102MachineBasicBlock * 1103MipsTargetLowering::EmitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{ 1104 // $bb: 1105 // bposge32_pseudo $vr0 1106 // => 1107 // $bb: 1108 // bposge32 $tbb 1109 // $fbb: 1110 // li $vr2, 0 1111 // b $sink 1112 // $tbb: 1113 // li $vr1, 1 1114 // $sink: 1115 // $vr0 = phi($vr2, $fbb, $vr1, $tbb) 1116 1117 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 1118 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1119 const TargetRegisterClass *RC = &Mips::CPURegsRegClass; 1120 DebugLoc DL = MI->getDebugLoc(); 1121 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1122 MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB)); 1123 MachineFunction *F = BB->getParent(); 1124 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB); 1125 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB); 1126 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB); 1127 F->insert(It, FBB); 1128 F->insert(It, TBB); 1129 F->insert(It, Sink); 1130 1131 // Transfer the remainder of BB and its successor edges to Sink. 1132 Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)), 1133 BB->end()); 1134 Sink->transferSuccessorsAndUpdatePHIs(BB); 1135 1136 // Add successors. 1137 BB->addSuccessor(FBB); 1138 BB->addSuccessor(TBB); 1139 FBB->addSuccessor(Sink); 1140 TBB->addSuccessor(Sink); 1141 1142 // Insert the real bposge32 instruction to $BB. 1143 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB); 1144 1145 // Fill $FBB. 1146 unsigned VR2 = RegInfo.createVirtualRegister(RC); 1147 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2) 1148 .addReg(Mips::ZERO).addImm(0); 1149 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink); 1150 1151 // Fill $TBB. 1152 unsigned VR1 = RegInfo.createVirtualRegister(RC); 1153 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1) 1154 .addReg(Mips::ZERO).addImm(1); 1155 1156 // Insert phi function to $Sink. 1157 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI), 1158 MI->getOperand(0).getReg()) 1159 .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB); 1160 1161 MI->eraseFromParent(); // The pseudo instruction is gone now. 1162 return Sink; 1163} 1164 1165MachineBasicBlock * 1166MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 1167 MachineBasicBlock *BB) const { 1168 switch (MI->getOpcode()) { 1169 default: llvm_unreachable("Unexpected instr type to insert"); 1170 case Mips::ATOMIC_LOAD_ADD_I8: 1171 case Mips::ATOMIC_LOAD_ADD_I8_P8: 1172 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu); 1173 case Mips::ATOMIC_LOAD_ADD_I16: 1174 case Mips::ATOMIC_LOAD_ADD_I16_P8: 1175 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu); 1176 case Mips::ATOMIC_LOAD_ADD_I32: 1177 case Mips::ATOMIC_LOAD_ADD_I32_P8: 1178 return EmitAtomicBinary(MI, BB, 4, Mips::ADDu); 1179 case Mips::ATOMIC_LOAD_ADD_I64: 1180 case Mips::ATOMIC_LOAD_ADD_I64_P8: 1181 return EmitAtomicBinary(MI, BB, 8, Mips::DADDu); 1182 1183 case Mips::ATOMIC_LOAD_AND_I8: 1184 case Mips::ATOMIC_LOAD_AND_I8_P8: 1185 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::AND); 1186 case Mips::ATOMIC_LOAD_AND_I16: 1187 case Mips::ATOMIC_LOAD_AND_I16_P8: 1188 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::AND); 1189 case Mips::ATOMIC_LOAD_AND_I32: 1190 case Mips::ATOMIC_LOAD_AND_I32_P8: 1191 return EmitAtomicBinary(MI, BB, 4, Mips::AND); 1192 case Mips::ATOMIC_LOAD_AND_I64: 1193 case Mips::ATOMIC_LOAD_AND_I64_P8: 1194 return EmitAtomicBinary(MI, BB, 8, Mips::AND64); 1195 1196 case Mips::ATOMIC_LOAD_OR_I8: 1197 case Mips::ATOMIC_LOAD_OR_I8_P8: 1198 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::OR); 1199 case Mips::ATOMIC_LOAD_OR_I16: 1200 case Mips::ATOMIC_LOAD_OR_I16_P8: 1201 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::OR); 1202 case Mips::ATOMIC_LOAD_OR_I32: 1203 case Mips::ATOMIC_LOAD_OR_I32_P8: 1204 return EmitAtomicBinary(MI, BB, 4, Mips::OR); 1205 case Mips::ATOMIC_LOAD_OR_I64: 1206 case Mips::ATOMIC_LOAD_OR_I64_P8: 1207 return EmitAtomicBinary(MI, BB, 8, Mips::OR64); 1208 1209 case Mips::ATOMIC_LOAD_XOR_I8: 1210 case Mips::ATOMIC_LOAD_XOR_I8_P8: 1211 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::XOR); 1212 case Mips::ATOMIC_LOAD_XOR_I16: 1213 case Mips::ATOMIC_LOAD_XOR_I16_P8: 1214 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::XOR); 1215 case Mips::ATOMIC_LOAD_XOR_I32: 1216 case Mips::ATOMIC_LOAD_XOR_I32_P8: 1217 return EmitAtomicBinary(MI, BB, 4, Mips::XOR); 1218 case Mips::ATOMIC_LOAD_XOR_I64: 1219 case Mips::ATOMIC_LOAD_XOR_I64_P8: 1220 return EmitAtomicBinary(MI, BB, 8, Mips::XOR64); 1221 1222 case Mips::ATOMIC_LOAD_NAND_I8: 1223 case Mips::ATOMIC_LOAD_NAND_I8_P8: 1224 return EmitAtomicBinaryPartword(MI, BB, 1, 0, true); 1225 case Mips::ATOMIC_LOAD_NAND_I16: 1226 case Mips::ATOMIC_LOAD_NAND_I16_P8: 1227 return EmitAtomicBinaryPartword(MI, BB, 2, 0, true); 1228 case Mips::ATOMIC_LOAD_NAND_I32: 1229 case Mips::ATOMIC_LOAD_NAND_I32_P8: 1230 return EmitAtomicBinary(MI, BB, 4, 0, true); 1231 case Mips::ATOMIC_LOAD_NAND_I64: 1232 case Mips::ATOMIC_LOAD_NAND_I64_P8: 1233 return EmitAtomicBinary(MI, BB, 8, 0, true); 1234 1235 case Mips::ATOMIC_LOAD_SUB_I8: 1236 case Mips::ATOMIC_LOAD_SUB_I8_P8: 1237 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu); 1238 case Mips::ATOMIC_LOAD_SUB_I16: 1239 case Mips::ATOMIC_LOAD_SUB_I16_P8: 1240 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu); 1241 case Mips::ATOMIC_LOAD_SUB_I32: 1242 case Mips::ATOMIC_LOAD_SUB_I32_P8: 1243 return EmitAtomicBinary(MI, BB, 4, Mips::SUBu); 1244 case Mips::ATOMIC_LOAD_SUB_I64: 1245 case Mips::ATOMIC_LOAD_SUB_I64_P8: 1246 return EmitAtomicBinary(MI, BB, 8, Mips::DSUBu); 1247 1248 case Mips::ATOMIC_SWAP_I8: 1249 case Mips::ATOMIC_SWAP_I8_P8: 1250 return EmitAtomicBinaryPartword(MI, BB, 1, 0); 1251 case Mips::ATOMIC_SWAP_I16: 1252 case Mips::ATOMIC_SWAP_I16_P8: 1253 return EmitAtomicBinaryPartword(MI, BB, 2, 0); 1254 case Mips::ATOMIC_SWAP_I32: 1255 case Mips::ATOMIC_SWAP_I32_P8: 1256 return EmitAtomicBinary(MI, BB, 4, 0); 1257 case Mips::ATOMIC_SWAP_I64: 1258 case Mips::ATOMIC_SWAP_I64_P8: 1259 return EmitAtomicBinary(MI, BB, 8, 0); 1260 1261 case Mips::ATOMIC_CMP_SWAP_I8: 1262 case Mips::ATOMIC_CMP_SWAP_I8_P8: 1263 return EmitAtomicCmpSwapPartword(MI, BB, 1); 1264 case Mips::ATOMIC_CMP_SWAP_I16: 1265 case Mips::ATOMIC_CMP_SWAP_I16_P8: 1266 return EmitAtomicCmpSwapPartword(MI, BB, 2); 1267 case Mips::ATOMIC_CMP_SWAP_I32: 1268 case Mips::ATOMIC_CMP_SWAP_I32_P8: 1269 return EmitAtomicCmpSwap(MI, BB, 4); 1270 case Mips::ATOMIC_CMP_SWAP_I64: 1271 case Mips::ATOMIC_CMP_SWAP_I64_P8: 1272 return EmitAtomicCmpSwap(MI, BB, 8); 1273 case Mips::BPOSGE32_PSEUDO: 1274 return EmitBPOSGE32(MI, BB); 1275 } 1276} 1277 1278// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 1279// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 1280MachineBasicBlock * 1281MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 1282 unsigned Size, unsigned BinOpcode, 1283 bool Nand) const { 1284 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary."); 1285 1286 MachineFunction *MF = BB->getParent(); 1287 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1288 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1289 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1290 DebugLoc dl = MI->getDebugLoc(); 1291 unsigned LL, SC, AND, NOR, ZERO, BEQ; 1292 1293 if (Size == 4) { 1294 LL = IsN64 ? Mips::LL_P8 : Mips::LL; 1295 SC = IsN64 ? Mips::SC_P8 : Mips::SC; 1296 AND = Mips::AND; 1297 NOR = Mips::NOR; 1298 ZERO = Mips::ZERO; 1299 BEQ = Mips::BEQ; 1300 } 1301 else { 1302 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD; 1303 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD; 1304 AND = Mips::AND64; 1305 NOR = Mips::NOR64; 1306 ZERO = Mips::ZERO_64; 1307 BEQ = Mips::BEQ64; 1308 } 1309 1310 unsigned OldVal = MI->getOperand(0).getReg(); 1311 unsigned Ptr = MI->getOperand(1).getReg(); 1312 unsigned Incr = MI->getOperand(2).getReg(); 1313 1314 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1315 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1316 unsigned Success = RegInfo.createVirtualRegister(RC); 1317 1318 // insert new blocks after the current block 1319 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1320 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1321 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1322 MachineFunction::iterator It = BB; 1323 ++It; 1324 MF->insert(It, loopMBB); 1325 MF->insert(It, exitMBB); 1326 1327 // Transfer the remainder of BB and its successor edges to exitMBB. 1328 exitMBB->splice(exitMBB->begin(), BB, 1329 llvm::next(MachineBasicBlock::iterator(MI)), 1330 BB->end()); 1331 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1332 1333 // thisMBB: 1334 // ... 1335 // fallthrough --> loopMBB 1336 BB->addSuccessor(loopMBB); 1337 loopMBB->addSuccessor(loopMBB); 1338 loopMBB->addSuccessor(exitMBB); 1339 1340 // loopMBB: 1341 // ll oldval, 0(ptr) 1342 // <binop> storeval, oldval, incr 1343 // sc success, storeval, 0(ptr) 1344 // beq success, $0, loopMBB 1345 BB = loopMBB; 1346 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(Ptr).addImm(0); 1347 if (Nand) { 1348 // and andres, oldval, incr 1349 // nor storeval, $0, andres 1350 BuildMI(BB, dl, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr); 1351 BuildMI(BB, dl, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes); 1352 } else if (BinOpcode) { 1353 // <binop> storeval, oldval, incr 1354 BuildMI(BB, dl, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr); 1355 } else { 1356 StoreVal = Incr; 1357 } 1358 BuildMI(BB, dl, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0); 1359 BuildMI(BB, dl, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB); 1360 1361 MI->eraseFromParent(); // The instruction is gone now. 1362 1363 return exitMBB; 1364} 1365 1366MachineBasicBlock * 1367MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI, 1368 MachineBasicBlock *BB, 1369 unsigned Size, unsigned BinOpcode, 1370 bool Nand) const { 1371 assert((Size == 1 || Size == 2) && 1372 "Unsupported size for EmitAtomicBinaryPartial."); 1373 1374 MachineFunction *MF = BB->getParent(); 1375 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1376 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1377 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1378 DebugLoc dl = MI->getDebugLoc(); 1379 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL; 1380 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC; 1381 1382 unsigned Dest = MI->getOperand(0).getReg(); 1383 unsigned Ptr = MI->getOperand(1).getReg(); 1384 unsigned Incr = MI->getOperand(2).getReg(); 1385 1386 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 1387 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1388 unsigned Mask = RegInfo.createVirtualRegister(RC); 1389 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1390 unsigned NewVal = RegInfo.createVirtualRegister(RC); 1391 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1392 unsigned Incr2 = RegInfo.createVirtualRegister(RC); 1393 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 1394 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1395 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1396 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1397 unsigned BinOpRes = RegInfo.createVirtualRegister(RC); 1398 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1399 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1400 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1401 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1402 unsigned SllRes = RegInfo.createVirtualRegister(RC); 1403 unsigned Success = RegInfo.createVirtualRegister(RC); 1404 1405 // insert new blocks after the current block 1406 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1407 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1408 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1409 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1410 MachineFunction::iterator It = BB; 1411 ++It; 1412 MF->insert(It, loopMBB); 1413 MF->insert(It, sinkMBB); 1414 MF->insert(It, exitMBB); 1415 1416 // Transfer the remainder of BB and its successor edges to exitMBB. 1417 exitMBB->splice(exitMBB->begin(), BB, 1418 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1419 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1420 1421 BB->addSuccessor(loopMBB); 1422 loopMBB->addSuccessor(loopMBB); 1423 loopMBB->addSuccessor(sinkMBB); 1424 sinkMBB->addSuccessor(exitMBB); 1425 1426 // thisMBB: 1427 // addiu masklsb2,$0,-4 # 0xfffffffc 1428 // and alignedaddr,ptr,masklsb2 1429 // andi ptrlsb2,ptr,3 1430 // sll shiftamt,ptrlsb2,3 1431 // ori maskupper,$0,255 # 0xff 1432 // sll mask,maskupper,shiftamt 1433 // nor mask2,$0,mask 1434 // sll incr2,incr,shiftamt 1435 1436 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1437 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2) 1438 .addReg(Mips::ZERO).addImm(-4); 1439 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr) 1440 .addReg(Ptr).addReg(MaskLSB2); 1441 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1442 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1443 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper) 1444 .addReg(Mips::ZERO).addImm(MaskImm); 1445 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask) 1446 .addReg(ShiftAmt).addReg(MaskUpper); 1447 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1448 BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr); 1449 1450 // atomic.load.binop 1451 // loopMBB: 1452 // ll oldval,0(alignedaddr) 1453 // binop binopres,oldval,incr2 1454 // and newval,binopres,mask 1455 // and maskedoldval0,oldval,mask2 1456 // or storeval,maskedoldval0,newval 1457 // sc success,storeval,0(alignedaddr) 1458 // beq success,$0,loopMBB 1459 1460 // atomic.swap 1461 // loopMBB: 1462 // ll oldval,0(alignedaddr) 1463 // and newval,incr2,mask 1464 // and maskedoldval0,oldval,mask2 1465 // or storeval,maskedoldval0,newval 1466 // sc success,storeval,0(alignedaddr) 1467 // beq success,$0,loopMBB 1468 1469 BB = loopMBB; 1470 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1471 if (Nand) { 1472 // and andres, oldval, incr2 1473 // nor binopres, $0, andres 1474 // and newval, binopres, mask 1475 BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2); 1476 BuildMI(BB, dl, TII->get(Mips::NOR), BinOpRes) 1477 .addReg(Mips::ZERO).addReg(AndRes); 1478 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1479 } else if (BinOpcode) { 1480 // <binop> binopres, oldval, incr2 1481 // and newval, binopres, mask 1482 BuildMI(BB, dl, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2); 1483 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1484 } else {// atomic.swap 1485 // and newval, incr2, mask 1486 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask); 1487 } 1488 1489 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0) 1490 .addReg(OldVal).addReg(Mask2); 1491 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal) 1492 .addReg(MaskedOldVal0).addReg(NewVal); 1493 BuildMI(BB, dl, TII->get(SC), Success) 1494 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1495 BuildMI(BB, dl, TII->get(Mips::BEQ)) 1496 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB); 1497 1498 // sinkMBB: 1499 // and maskedoldval1,oldval,mask 1500 // srl srlres,maskedoldval1,shiftamt 1501 // sll sllres,srlres,24 1502 // sra dest,sllres,24 1503 BB = sinkMBB; 1504 int64_t ShiftImm = (Size == 1) ? 24 : 16; 1505 1506 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1) 1507 .addReg(OldVal).addReg(Mask); 1508 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes) 1509 .addReg(ShiftAmt).addReg(MaskedOldVal1); 1510 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes) 1511 .addReg(SrlRes).addImm(ShiftImm); 1512 BuildMI(BB, dl, TII->get(Mips::SRA), Dest) 1513 .addReg(SllRes).addImm(ShiftImm); 1514 1515 MI->eraseFromParent(); // The instruction is gone now. 1516 1517 return exitMBB; 1518} 1519 1520MachineBasicBlock * 1521MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI, 1522 MachineBasicBlock *BB, 1523 unsigned Size) const { 1524 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap."); 1525 1526 MachineFunction *MF = BB->getParent(); 1527 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1528 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1529 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1530 DebugLoc dl = MI->getDebugLoc(); 1531 unsigned LL, SC, ZERO, BNE, BEQ; 1532 1533 if (Size == 4) { 1534 LL = IsN64 ? Mips::LL_P8 : Mips::LL; 1535 SC = IsN64 ? Mips::SC_P8 : Mips::SC; 1536 ZERO = Mips::ZERO; 1537 BNE = Mips::BNE; 1538 BEQ = Mips::BEQ; 1539 } 1540 else { 1541 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD; 1542 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD; 1543 ZERO = Mips::ZERO_64; 1544 BNE = Mips::BNE64; 1545 BEQ = Mips::BEQ64; 1546 } 1547 1548 unsigned Dest = MI->getOperand(0).getReg(); 1549 unsigned Ptr = MI->getOperand(1).getReg(); 1550 unsigned OldVal = MI->getOperand(2).getReg(); 1551 unsigned NewVal = MI->getOperand(3).getReg(); 1552 1553 unsigned Success = RegInfo.createVirtualRegister(RC); 1554 1555 // insert new blocks after the current block 1556 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1557 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1558 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1559 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1560 MachineFunction::iterator It = BB; 1561 ++It; 1562 MF->insert(It, loop1MBB); 1563 MF->insert(It, loop2MBB); 1564 MF->insert(It, exitMBB); 1565 1566 // Transfer the remainder of BB and its successor edges to exitMBB. 1567 exitMBB->splice(exitMBB->begin(), BB, 1568 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1569 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1570 1571 // thisMBB: 1572 // ... 1573 // fallthrough --> loop1MBB 1574 BB->addSuccessor(loop1MBB); 1575 loop1MBB->addSuccessor(exitMBB); 1576 loop1MBB->addSuccessor(loop2MBB); 1577 loop2MBB->addSuccessor(loop1MBB); 1578 loop2MBB->addSuccessor(exitMBB); 1579 1580 // loop1MBB: 1581 // ll dest, 0(ptr) 1582 // bne dest, oldval, exitMBB 1583 BB = loop1MBB; 1584 BuildMI(BB, dl, TII->get(LL), Dest).addReg(Ptr).addImm(0); 1585 BuildMI(BB, dl, TII->get(BNE)) 1586 .addReg(Dest).addReg(OldVal).addMBB(exitMBB); 1587 1588 // loop2MBB: 1589 // sc success, newval, 0(ptr) 1590 // beq success, $0, loop1MBB 1591 BB = loop2MBB; 1592 BuildMI(BB, dl, TII->get(SC), Success) 1593 .addReg(NewVal).addReg(Ptr).addImm(0); 1594 BuildMI(BB, dl, TII->get(BEQ)) 1595 .addReg(Success).addReg(ZERO).addMBB(loop1MBB); 1596 1597 MI->eraseFromParent(); // The instruction is gone now. 1598 1599 return exitMBB; 1600} 1601 1602MachineBasicBlock * 1603MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI, 1604 MachineBasicBlock *BB, 1605 unsigned Size) const { 1606 assert((Size == 1 || Size == 2) && 1607 "Unsupported size for EmitAtomicCmpSwapPartial."); 1608 1609 MachineFunction *MF = BB->getParent(); 1610 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1611 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1612 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1613 DebugLoc dl = MI->getDebugLoc(); 1614 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL; 1615 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC; 1616 1617 unsigned Dest = MI->getOperand(0).getReg(); 1618 unsigned Ptr = MI->getOperand(1).getReg(); 1619 unsigned CmpVal = MI->getOperand(2).getReg(); 1620 unsigned NewVal = MI->getOperand(3).getReg(); 1621 1622 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 1623 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1624 unsigned Mask = RegInfo.createVirtualRegister(RC); 1625 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1626 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC); 1627 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1628 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1629 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC); 1630 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 1631 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1632 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1633 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC); 1634 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC); 1635 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1636 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1637 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1638 unsigned SllRes = RegInfo.createVirtualRegister(RC); 1639 unsigned Success = RegInfo.createVirtualRegister(RC); 1640 1641 // insert new blocks after the current block 1642 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1643 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1644 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1645 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1646 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1647 MachineFunction::iterator It = BB; 1648 ++It; 1649 MF->insert(It, loop1MBB); 1650 MF->insert(It, loop2MBB); 1651 MF->insert(It, sinkMBB); 1652 MF->insert(It, exitMBB); 1653 1654 // Transfer the remainder of BB and its successor edges to exitMBB. 1655 exitMBB->splice(exitMBB->begin(), BB, 1656 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1657 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1658 1659 BB->addSuccessor(loop1MBB); 1660 loop1MBB->addSuccessor(sinkMBB); 1661 loop1MBB->addSuccessor(loop2MBB); 1662 loop2MBB->addSuccessor(loop1MBB); 1663 loop2MBB->addSuccessor(sinkMBB); 1664 sinkMBB->addSuccessor(exitMBB); 1665 1666 // FIXME: computation of newval2 can be moved to loop2MBB. 1667 // thisMBB: 1668 // addiu masklsb2,$0,-4 # 0xfffffffc 1669 // and alignedaddr,ptr,masklsb2 1670 // andi ptrlsb2,ptr,3 1671 // sll shiftamt,ptrlsb2,3 1672 // ori maskupper,$0,255 # 0xff 1673 // sll mask,maskupper,shiftamt 1674 // nor mask2,$0,mask 1675 // andi maskedcmpval,cmpval,255 1676 // sll shiftedcmpval,maskedcmpval,shiftamt 1677 // andi maskednewval,newval,255 1678 // sll shiftednewval,maskednewval,shiftamt 1679 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1680 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2) 1681 .addReg(Mips::ZERO).addImm(-4); 1682 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr) 1683 .addReg(Ptr).addReg(MaskLSB2); 1684 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1685 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1686 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper) 1687 .addReg(Mips::ZERO).addImm(MaskImm); 1688 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask) 1689 .addReg(ShiftAmt).addReg(MaskUpper); 1690 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1691 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedCmpVal) 1692 .addReg(CmpVal).addImm(MaskImm); 1693 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedCmpVal) 1694 .addReg(ShiftAmt).addReg(MaskedCmpVal); 1695 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedNewVal) 1696 .addReg(NewVal).addImm(MaskImm); 1697 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedNewVal) 1698 .addReg(ShiftAmt).addReg(MaskedNewVal); 1699 1700 // loop1MBB: 1701 // ll oldval,0(alginedaddr) 1702 // and maskedoldval0,oldval,mask 1703 // bne maskedoldval0,shiftedcmpval,sinkMBB 1704 BB = loop1MBB; 1705 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1706 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0) 1707 .addReg(OldVal).addReg(Mask); 1708 BuildMI(BB, dl, TII->get(Mips::BNE)) 1709 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB); 1710 1711 // loop2MBB: 1712 // and maskedoldval1,oldval,mask2 1713 // or storeval,maskedoldval1,shiftednewval 1714 // sc success,storeval,0(alignedaddr) 1715 // beq success,$0,loop1MBB 1716 BB = loop2MBB; 1717 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1) 1718 .addReg(OldVal).addReg(Mask2); 1719 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal) 1720 .addReg(MaskedOldVal1).addReg(ShiftedNewVal); 1721 BuildMI(BB, dl, TII->get(SC), Success) 1722 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1723 BuildMI(BB, dl, TII->get(Mips::BEQ)) 1724 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB); 1725 1726 // sinkMBB: 1727 // srl srlres,maskedoldval0,shiftamt 1728 // sll sllres,srlres,24 1729 // sra dest,sllres,24 1730 BB = sinkMBB; 1731 int64_t ShiftImm = (Size == 1) ? 24 : 16; 1732 1733 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes) 1734 .addReg(ShiftAmt).addReg(MaskedOldVal0); 1735 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes) 1736 .addReg(SrlRes).addImm(ShiftImm); 1737 BuildMI(BB, dl, TII->get(Mips::SRA), Dest) 1738 .addReg(SllRes).addImm(ShiftImm); 1739 1740 MI->eraseFromParent(); // The instruction is gone now. 1741 1742 return exitMBB; 1743} 1744 1745//===----------------------------------------------------------------------===// 1746// Misc Lower Operation implementation 1747//===----------------------------------------------------------------------===// 1748SDValue MipsTargetLowering:: 1749LowerBRCOND(SDValue Op, SelectionDAG &DAG) const 1750{ 1751 // The first operand is the chain, the second is the condition, the third is 1752 // the block to branch to if the condition is true. 1753 SDValue Chain = Op.getOperand(0); 1754 SDValue Dest = Op.getOperand(2); 1755 DebugLoc dl = Op.getDebugLoc(); 1756 1757 SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1)); 1758 1759 // Return if flag is not set by a floating point comparison. 1760 if (CondRes.getOpcode() != MipsISD::FPCmp) 1761 return Op; 1762 1763 SDValue CCNode = CondRes.getOperand(2); 1764 Mips::CondCode CC = 1765 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 1766 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32); 1767 1768 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode, 1769 Dest, CondRes); 1770} 1771 1772SDValue MipsTargetLowering:: 1773LowerSELECT(SDValue Op, SelectionDAG &DAG) const 1774{ 1775 SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0)); 1776 1777 // Return if flag is not set by a floating point comparison. 1778 if (Cond.getOpcode() != MipsISD::FPCmp) 1779 return Op; 1780 1781 return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 1782 Op.getDebugLoc()); 1783} 1784 1785SDValue MipsTargetLowering:: 1786LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const 1787{ 1788 DebugLoc DL = Op.getDebugLoc(); 1789 EVT Ty = Op.getOperand(0).getValueType(); 1790 SDValue Cond = DAG.getNode(ISD::SETCC, DL, getSetCCResultType(Ty), 1791 Op.getOperand(0), Op.getOperand(1), 1792 Op.getOperand(4)); 1793 1794 return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2), 1795 Op.getOperand(3)); 1796} 1797 1798SDValue MipsTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 1799 SDValue Cond = CreateFPCmp(DAG, Op); 1800 1801 assert(Cond.getOpcode() == MipsISD::FPCmp && 1802 "Floating point operand expected."); 1803 1804 SDValue True = DAG.getConstant(1, MVT::i32); 1805 SDValue False = DAG.getConstant(0, MVT::i32); 1806 1807 return CreateCMovFP(DAG, Cond, True, False, Op.getDebugLoc()); 1808} 1809 1810SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op, 1811 SelectionDAG &DAG) const { 1812 // FIXME there isn't actually debug info here 1813 DebugLoc dl = Op.getDebugLoc(); 1814 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 1815 1816 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) { 1817 const MipsTargetObjectFile &TLOF = 1818 (const MipsTargetObjectFile&)getObjFileLowering(); 1819 1820 // %gp_rel relocation 1821 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) { 1822 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1823 MipsII::MO_GPREL); 1824 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, 1825 DAG.getVTList(MVT::i32), &GA, 1); 1826 SDValue GPReg = DAG.getRegister(Mips::GP, MVT::i32); 1827 return DAG.getNode(ISD::ADD, dl, MVT::i32, GPReg, GPRelNode); 1828 } 1829 1830 // %hi/%lo relocation 1831 return getAddrNonPIC(Op, DAG); 1832 } 1833 1834 if (GV->hasInternalLinkage() || (GV->hasLocalLinkage() && !isa<Function>(GV))) 1835 return getAddrLocal(Op, DAG, HasMips64); 1836 1837 if (LargeGOT) 1838 return getAddrGlobalLargeGOT(Op, DAG, MipsII::MO_GOT_HI16, 1839 MipsII::MO_GOT_LO16); 1840 1841 return getAddrGlobal(Op, DAG, 1842 HasMips64 ? MipsII::MO_GOT_DISP : MipsII::MO_GOT16); 1843} 1844 1845SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op, 1846 SelectionDAG &DAG) const { 1847 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) 1848 return getAddrNonPIC(Op, DAG); 1849 1850 return getAddrLocal(Op, DAG, HasMips64); 1851} 1852 1853SDValue MipsTargetLowering:: 1854LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 1855{ 1856 // If the relocation model is PIC, use the General Dynamic TLS Model or 1857 // Local Dynamic TLS model, otherwise use the Initial Exec or 1858 // Local Exec TLS Model. 1859 1860 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1861 DebugLoc dl = GA->getDebugLoc(); 1862 const GlobalValue *GV = GA->getGlobal(); 1863 EVT PtrVT = getPointerTy(); 1864 1865 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 1866 1867 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) { 1868 // General Dynamic and Local Dynamic TLS Model. 1869 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM 1870 : MipsII::MO_TLSGD; 1871 1872 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, Flag); 1873 SDValue Argument = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, 1874 GetGlobalReg(DAG, PtrVT), TGA); 1875 unsigned PtrSize = PtrVT.getSizeInBits(); 1876 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize); 1877 1878 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT); 1879 1880 ArgListTy Args; 1881 ArgListEntry Entry; 1882 Entry.Node = Argument; 1883 Entry.Ty = PtrTy; 1884 Args.push_back(Entry); 1885 1886 TargetLowering::CallLoweringInfo CLI(DAG.getEntryNode(), PtrTy, 1887 false, false, false, false, 0, CallingConv::C, 1888 /*isTailCall=*/false, /*doesNotRet=*/false, 1889 /*isReturnValueUsed=*/true, 1890 TlsGetAddr, Args, DAG, dl); 1891 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 1892 1893 SDValue Ret = CallResult.first; 1894 1895 if (model != TLSModel::LocalDynamic) 1896 return Ret; 1897 1898 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1899 MipsII::MO_DTPREL_HI); 1900 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi); 1901 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1902 MipsII::MO_DTPREL_LO); 1903 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo); 1904 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Ret); 1905 return DAG.getNode(ISD::ADD, dl, PtrVT, Add, Lo); 1906 } 1907 1908 SDValue Offset; 1909 if (model == TLSModel::InitialExec) { 1910 // Initial Exec TLS Model 1911 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1912 MipsII::MO_GOTTPREL); 1913 TGA = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, GetGlobalReg(DAG, PtrVT), 1914 TGA); 1915 Offset = DAG.getLoad(PtrVT, dl, 1916 DAG.getEntryNode(), TGA, MachinePointerInfo(), 1917 false, false, false, 0); 1918 } else { 1919 // Local Exec TLS Model 1920 assert(model == TLSModel::LocalExec); 1921 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1922 MipsII::MO_TPREL_HI); 1923 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1924 MipsII::MO_TPREL_LO); 1925 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi); 1926 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo); 1927 Offset = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); 1928 } 1929 1930 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, dl, PtrVT); 1931 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 1932} 1933 1934SDValue MipsTargetLowering:: 1935LowerJumpTable(SDValue Op, SelectionDAG &DAG) const 1936{ 1937 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) 1938 return getAddrNonPIC(Op, DAG); 1939 1940 return getAddrLocal(Op, DAG, HasMips64); 1941} 1942 1943SDValue MipsTargetLowering:: 1944LowerConstantPool(SDValue Op, SelectionDAG &DAG) const 1945{ 1946 // gp_rel relocation 1947 // FIXME: we should reference the constant pool using small data sections, 1948 // but the asm printer currently doesn't support this feature without 1949 // hacking it. This feature should come soon so we can uncomment the 1950 // stuff below. 1951 //if (IsInSmallSection(C->getType())) { 1952 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP); 1953 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); 1954 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode); 1955 1956 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) 1957 return getAddrNonPIC(Op, DAG); 1958 1959 return getAddrLocal(Op, DAG, HasMips64); 1960} 1961 1962SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 1963 MachineFunction &MF = DAG.getMachineFunction(); 1964 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 1965 1966 DebugLoc dl = Op.getDebugLoc(); 1967 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1968 getPointerTy()); 1969 1970 // vastart just stores the address of the VarArgsFrameIndex slot into the 1971 // memory location argument. 1972 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1973 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1), 1974 MachinePointerInfo(SV), false, false, 0); 1975} 1976 1977static SDValue LowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasR2) { 1978 EVT TyX = Op.getOperand(0).getValueType(); 1979 EVT TyY = Op.getOperand(1).getValueType(); 1980 SDValue Const1 = DAG.getConstant(1, MVT::i32); 1981 SDValue Const31 = DAG.getConstant(31, MVT::i32); 1982 DebugLoc DL = Op.getDebugLoc(); 1983 SDValue Res; 1984 1985 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 1986 // to i32. 1987 SDValue X = (TyX == MVT::f32) ? 1988 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 1989 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 1990 Const1); 1991 SDValue Y = (TyY == MVT::f32) ? 1992 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) : 1993 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1), 1994 Const1); 1995 1996 if (HasR2) { 1997 // ext E, Y, 31, 1 ; extract bit31 of Y 1998 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X 1999 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1); 2000 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X); 2001 } else { 2002 // sll SllX, X, 1 2003 // srl SrlX, SllX, 1 2004 // srl SrlY, Y, 31 2005 // sll SllY, SrlX, 31 2006 // or Or, SrlX, SllY 2007 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 2008 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 2009 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); 2010 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31); 2011 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY); 2012 } 2013 2014 if (TyX == MVT::f32) 2015 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res); 2016 2017 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2018 Op.getOperand(0), DAG.getConstant(0, MVT::i32)); 2019 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 2020} 2021 2022static SDValue LowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasR2) { 2023 unsigned WidthX = Op.getOperand(0).getValueSizeInBits(); 2024 unsigned WidthY = Op.getOperand(1).getValueSizeInBits(); 2025 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY); 2026 SDValue Const1 = DAG.getConstant(1, MVT::i32); 2027 DebugLoc DL = Op.getDebugLoc(); 2028 2029 // Bitcast to integer nodes. 2030 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0)); 2031 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1)); 2032 2033 if (HasR2) { 2034 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y 2035 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X 2036 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y, 2037 DAG.getConstant(WidthY - 1, MVT::i32), Const1); 2038 2039 if (WidthX > WidthY) 2040 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E); 2041 else if (WidthY > WidthX) 2042 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E); 2043 2044 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E, 2045 DAG.getConstant(WidthX - 1, MVT::i32), Const1, X); 2046 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I); 2047 } 2048 2049 // (d)sll SllX, X, 1 2050 // (d)srl SrlX, SllX, 1 2051 // (d)srl SrlY, Y, width(Y)-1 2052 // (d)sll SllY, SrlX, width(Y)-1 2053 // or Or, SrlX, SllY 2054 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1); 2055 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); 2056 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, 2057 DAG.getConstant(WidthY - 1, MVT::i32)); 2058 2059 if (WidthX > WidthY) 2060 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY); 2061 else if (WidthY > WidthX) 2062 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY); 2063 2064 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY, 2065 DAG.getConstant(WidthX - 1, MVT::i32)); 2066 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY); 2067 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or); 2068} 2069 2070SDValue 2071MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 2072 if (Subtarget->hasMips64()) 2073 return LowerFCOPYSIGN64(Op, DAG, Subtarget->hasMips32r2()); 2074 2075 return LowerFCOPYSIGN32(Op, DAG, Subtarget->hasMips32r2()); 2076} 2077 2078static SDValue LowerFABS32(SDValue Op, SelectionDAG &DAG, bool HasR2) { 2079 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32); 2080 DebugLoc DL = Op.getDebugLoc(); 2081 2082 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 2083 // to i32. 2084 SDValue X = (Op.getValueType() == MVT::f32) ? 2085 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 2086 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 2087 Const1); 2088 2089 // Clear MSB. 2090 if (HasR2) 2091 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, 2092 DAG.getRegister(Mips::ZERO, MVT::i32), 2093 DAG.getConstant(31, MVT::i32), Const1, X); 2094 else { 2095 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 2096 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 2097 } 2098 2099 if (Op.getValueType() == MVT::f32) 2100 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res); 2101 2102 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2103 Op.getOperand(0), DAG.getConstant(0, MVT::i32)); 2104 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 2105} 2106 2107static SDValue LowerFABS64(SDValue Op, SelectionDAG &DAG, bool HasR2) { 2108 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32); 2109 DebugLoc DL = Op.getDebugLoc(); 2110 2111 // Bitcast to integer node. 2112 SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0)); 2113 2114 // Clear MSB. 2115 if (HasR2) 2116 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64, 2117 DAG.getRegister(Mips::ZERO_64, MVT::i64), 2118 DAG.getConstant(63, MVT::i32), Const1, X); 2119 else { 2120 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1); 2121 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1); 2122 } 2123 2124 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res); 2125} 2126 2127SDValue 2128MipsTargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const { 2129 if (Subtarget->hasMips64() && (Op.getValueType() == MVT::f64)) 2130 return LowerFABS64(Op, DAG, Subtarget->hasMips32r2()); 2131 2132 return LowerFABS32(Op, DAG, Subtarget->hasMips32r2()); 2133} 2134 2135SDValue MipsTargetLowering:: 2136LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 2137 // check the depth 2138 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 2139 "Frame address can only be determined for current frame."); 2140 2141 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2142 MFI->setFrameAddressIsTaken(true); 2143 EVT VT = Op.getValueType(); 2144 DebugLoc dl = Op.getDebugLoc(); 2145 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 2146 IsN64 ? Mips::FP_64 : Mips::FP, VT); 2147 return FrameAddr; 2148} 2149 2150SDValue MipsTargetLowering::LowerRETURNADDR(SDValue Op, 2151 SelectionDAG &DAG) const { 2152 // check the depth 2153 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 2154 "Return address can be determined only for current frame."); 2155 2156 MachineFunction &MF = DAG.getMachineFunction(); 2157 MachineFrameInfo *MFI = MF.getFrameInfo(); 2158 MVT VT = Op.getSimpleValueType(); 2159 unsigned RA = IsN64 ? Mips::RA_64 : Mips::RA; 2160 MFI->setReturnAddressIsTaken(true); 2161 2162 // Return RA, which contains the return address. Mark it an implicit live-in. 2163 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); 2164 return DAG.getCopyFromReg(DAG.getEntryNode(), Op.getDebugLoc(), Reg, VT); 2165} 2166 2167// TODO: set SType according to the desired memory barrier behavior. 2168SDValue 2169MipsTargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const { 2170 unsigned SType = 0; 2171 DebugLoc dl = Op.getDebugLoc(); 2172 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0), 2173 DAG.getConstant(SType, MVT::i32)); 2174} 2175 2176SDValue MipsTargetLowering::LowerATOMIC_FENCE(SDValue Op, 2177 SelectionDAG &DAG) const { 2178 // FIXME: Need pseudo-fence for 'singlethread' fences 2179 // FIXME: Set SType for weaker fences where supported/appropriate. 2180 unsigned SType = 0; 2181 DebugLoc dl = Op.getDebugLoc(); 2182 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0), 2183 DAG.getConstant(SType, MVT::i32)); 2184} 2185 2186SDValue MipsTargetLowering::LowerShiftLeftParts(SDValue Op, 2187 SelectionDAG &DAG) const { 2188 DebugLoc DL = Op.getDebugLoc(); 2189 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2190 SDValue Shamt = Op.getOperand(2); 2191 2192 // if shamt < 32: 2193 // lo = (shl lo, shamt) 2194 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt)) 2195 // else: 2196 // lo = 0 2197 // hi = (shl lo, shamt[4:0]) 2198 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2199 DAG.getConstant(-1, MVT::i32)); 2200 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, 2201 DAG.getConstant(1, MVT::i32)); 2202 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo, 2203 Not); 2204 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt); 2205 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo); 2206 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt); 2207 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2208 DAG.getConstant(0x20, MVT::i32)); 2209 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, 2210 DAG.getConstant(0, MVT::i32), ShiftLeftLo); 2211 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or); 2212 2213 SDValue Ops[2] = {Lo, Hi}; 2214 return DAG.getMergeValues(Ops, 2, DL); 2215} 2216 2217SDValue MipsTargetLowering::LowerShiftRightParts(SDValue Op, SelectionDAG &DAG, 2218 bool IsSRA) const { 2219 DebugLoc DL = Op.getDebugLoc(); 2220 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2221 SDValue Shamt = Op.getOperand(2); 2222 2223 // if shamt < 32: 2224 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt)) 2225 // if isSRA: 2226 // hi = (sra hi, shamt) 2227 // else: 2228 // hi = (srl hi, shamt) 2229 // else: 2230 // if isSRA: 2231 // lo = (sra hi, shamt[4:0]) 2232 // hi = (sra hi, 31) 2233 // else: 2234 // lo = (srl hi, shamt[4:0]) 2235 // hi = 0 2236 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2237 DAG.getConstant(-1, MVT::i32)); 2238 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, 2239 DAG.getConstant(1, MVT::i32)); 2240 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not); 2241 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt); 2242 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo); 2243 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32, 2244 Hi, Shamt); 2245 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2246 DAG.getConstant(0x20, MVT::i32)); 2247 SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi, 2248 DAG.getConstant(31, MVT::i32)); 2249 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or); 2250 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, 2251 IsSRA ? Shift31 : DAG.getConstant(0, MVT::i32), 2252 ShiftRightHi); 2253 2254 SDValue Ops[2] = {Lo, Hi}; 2255 return DAG.getMergeValues(Ops, 2, DL); 2256} 2257 2258static SDValue CreateLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, 2259 SDValue Chain, SDValue Src, unsigned Offset) { 2260 SDValue Ptr = LD->getBasePtr(); 2261 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT(); 2262 EVT BasePtrVT = Ptr.getValueType(); 2263 DebugLoc DL = LD->getDebugLoc(); 2264 SDVTList VTList = DAG.getVTList(VT, MVT::Other); 2265 2266 if (Offset) 2267 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2268 DAG.getConstant(Offset, BasePtrVT)); 2269 2270 SDValue Ops[] = { Chain, Ptr, Src }; 2271 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT, 2272 LD->getMemOperand()); 2273} 2274 2275// Expand an unaligned 32 or 64-bit integer load node. 2276SDValue MipsTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const { 2277 LoadSDNode *LD = cast<LoadSDNode>(Op); 2278 EVT MemVT = LD->getMemoryVT(); 2279 2280 // Return if load is aligned or if MemVT is neither i32 nor i64. 2281 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) || 2282 ((MemVT != MVT::i32) && (MemVT != MVT::i64))) 2283 return SDValue(); 2284 2285 bool IsLittle = Subtarget->isLittle(); 2286 EVT VT = Op.getValueType(); 2287 ISD::LoadExtType ExtType = LD->getExtensionType(); 2288 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT); 2289 2290 assert((VT == MVT::i32) || (VT == MVT::i64)); 2291 2292 // Expand 2293 // (set dst, (i64 (load baseptr))) 2294 // to 2295 // (set tmp, (ldl (add baseptr, 7), undef)) 2296 // (set dst, (ldr baseptr, tmp)) 2297 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) { 2298 SDValue LDL = CreateLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef, 2299 IsLittle ? 7 : 0); 2300 return CreateLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL, 2301 IsLittle ? 0 : 7); 2302 } 2303 2304 SDValue LWL = CreateLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, 2305 IsLittle ? 3 : 0); 2306 SDValue LWR = CreateLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, 2307 IsLittle ? 0 : 3); 2308 2309 // Expand 2310 // (set dst, (i32 (load baseptr))) or 2311 // (set dst, (i64 (sextload baseptr))) or 2312 // (set dst, (i64 (extload baseptr))) 2313 // to 2314 // (set tmp, (lwl (add baseptr, 3), undef)) 2315 // (set dst, (lwr baseptr, tmp)) 2316 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) || 2317 (ExtType == ISD::EXTLOAD)) 2318 return LWR; 2319 2320 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)); 2321 2322 // Expand 2323 // (set dst, (i64 (zextload baseptr))) 2324 // to 2325 // (set tmp0, (lwl (add baseptr, 3), undef)) 2326 // (set tmp1, (lwr baseptr, tmp0)) 2327 // (set tmp2, (shl tmp1, 32)) 2328 // (set dst, (srl tmp2, 32)) 2329 DebugLoc DL = LD->getDebugLoc(); 2330 SDValue Const32 = DAG.getConstant(32, MVT::i32); 2331 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); 2332 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); 2333 SDValue Ops[] = { SRL, LWR.getValue(1) }; 2334 return DAG.getMergeValues(Ops, 2, DL); 2335} 2336 2337static SDValue CreateStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, 2338 SDValue Chain, unsigned Offset) { 2339 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue(); 2340 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType(); 2341 DebugLoc DL = SD->getDebugLoc(); 2342 SDVTList VTList = DAG.getVTList(MVT::Other); 2343 2344 if (Offset) 2345 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2346 DAG.getConstant(Offset, BasePtrVT)); 2347 2348 SDValue Ops[] = { Chain, Value, Ptr }; 2349 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT, 2350 SD->getMemOperand()); 2351} 2352 2353// Expand an unaligned 32 or 64-bit integer store node. 2354SDValue MipsTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const { 2355 StoreSDNode *SD = cast<StoreSDNode>(Op); 2356 EVT MemVT = SD->getMemoryVT(); 2357 2358 // Return if store is aligned or if MemVT is neither i32 nor i64. 2359 if ((SD->getAlignment() >= MemVT.getSizeInBits() / 8) || 2360 ((MemVT != MVT::i32) && (MemVT != MVT::i64))) 2361 return SDValue(); 2362 2363 bool IsLittle = Subtarget->isLittle(); 2364 SDValue Value = SD->getValue(), Chain = SD->getChain(); 2365 EVT VT = Value.getValueType(); 2366 2367 // Expand 2368 // (store val, baseptr) or 2369 // (truncstore val, baseptr) 2370 // to 2371 // (swl val, (add baseptr, 3)) 2372 // (swr val, baseptr) 2373 if ((VT == MVT::i32) || SD->isTruncatingStore()) { 2374 SDValue SWL = CreateStoreLR(MipsISD::SWL, DAG, SD, Chain, 2375 IsLittle ? 3 : 0); 2376 return CreateStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); 2377 } 2378 2379 assert(VT == MVT::i64); 2380 2381 // Expand 2382 // (store val, baseptr) 2383 // to 2384 // (sdl val, (add baseptr, 7)) 2385 // (sdr val, baseptr) 2386 SDValue SDL = CreateStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0); 2387 return CreateStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7); 2388} 2389 2390// This function expands mips intrinsic nodes which have 64-bit input operands 2391// or output values. 2392// 2393// out64 = intrinsic-node in64 2394// => 2395// lo = copy (extract-element (in64, 0)) 2396// hi = copy (extract-element (in64, 1)) 2397// mips-specific-node 2398// v0 = copy lo 2399// v1 = copy hi 2400// out64 = merge-values (v0, v1) 2401// 2402static SDValue LowerDSPIntr(SDValue Op, SelectionDAG &DAG, 2403 unsigned Opc, bool HasI64In, bool HasI64Out) { 2404 DebugLoc DL = Op.getDebugLoc(); 2405 bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other; 2406 SDValue Chain = HasChainIn ? Op->getOperand(0) : DAG.getEntryNode(); 2407 SmallVector<SDValue, 3> Ops; 2408 2409 if (HasI64In) { 2410 SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, 2411 Op->getOperand(1 + HasChainIn), 2412 DAG.getConstant(0, MVT::i32)); 2413 SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, 2414 Op->getOperand(1 + HasChainIn), 2415 DAG.getConstant(1, MVT::i32)); 2416 2417 Chain = DAG.getCopyToReg(Chain, DL, Mips::LO, InLo, SDValue()); 2418 Chain = DAG.getCopyToReg(Chain, DL, Mips::HI, InHi, Chain.getValue(1)); 2419 2420 Ops.push_back(Chain); 2421 Ops.append(Op->op_begin() + HasChainIn + 2, Op->op_end()); 2422 Ops.push_back(Chain.getValue(1)); 2423 } else { 2424 Ops.push_back(Chain); 2425 Ops.append(Op->op_begin() + HasChainIn + 1, Op->op_end()); 2426 } 2427 2428 if (!HasI64Out) 2429 return DAG.getNode(Opc, DL, Op->value_begin(), Op->getNumValues(), 2430 Ops.begin(), Ops.size()); 2431 2432 SDValue Intr = DAG.getNode(Opc, DL, DAG.getVTList(MVT::Other, MVT::Glue), 2433 Ops.begin(), Ops.size()); 2434 SDValue OutLo = DAG.getCopyFromReg(Intr.getValue(0), DL, Mips::LO, MVT::i32, 2435 Intr.getValue(1)); 2436 SDValue OutHi = DAG.getCopyFromReg(OutLo.getValue(1), DL, Mips::HI, MVT::i32, 2437 OutLo.getValue(2)); 2438 SDValue Out = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, OutLo, OutHi); 2439 2440 if (!HasChainIn) 2441 return Out; 2442 2443 SDValue Vals[] = { Out, OutHi.getValue(1) }; 2444 return DAG.getMergeValues(Vals, 2, DL); 2445} 2446 2447SDValue MipsTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, 2448 SelectionDAG &DAG) const { 2449 switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) { 2450 default: 2451 return SDValue(); 2452 case Intrinsic::mips_shilo: 2453 return LowerDSPIntr(Op, DAG, MipsISD::SHILO, true, true); 2454 case Intrinsic::mips_dpau_h_qbl: 2455 return LowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL, true, true); 2456 case Intrinsic::mips_dpau_h_qbr: 2457 return LowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR, true, true); 2458 case Intrinsic::mips_dpsu_h_qbl: 2459 return LowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL, true, true); 2460 case Intrinsic::mips_dpsu_h_qbr: 2461 return LowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR, true, true); 2462 case Intrinsic::mips_dpa_w_ph: 2463 return LowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH, true, true); 2464 case Intrinsic::mips_dps_w_ph: 2465 return LowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH, true, true); 2466 case Intrinsic::mips_dpax_w_ph: 2467 return LowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH, true, true); 2468 case Intrinsic::mips_dpsx_w_ph: 2469 return LowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH, true, true); 2470 case Intrinsic::mips_mulsa_w_ph: 2471 return LowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH, true, true); 2472 case Intrinsic::mips_mult: 2473 return LowerDSPIntr(Op, DAG, MipsISD::MULT, false, true); 2474 case Intrinsic::mips_multu: 2475 return LowerDSPIntr(Op, DAG, MipsISD::MULTU, false, true); 2476 case Intrinsic::mips_madd: 2477 return LowerDSPIntr(Op, DAG, MipsISD::MADD_DSP, true, true); 2478 case Intrinsic::mips_maddu: 2479 return LowerDSPIntr(Op, DAG, MipsISD::MADDU_DSP, true, true); 2480 case Intrinsic::mips_msub: 2481 return LowerDSPIntr(Op, DAG, MipsISD::MSUB_DSP, true, true); 2482 case Intrinsic::mips_msubu: 2483 return LowerDSPIntr(Op, DAG, MipsISD::MSUBU_DSP, true, true); 2484 } 2485} 2486 2487SDValue MipsTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, 2488 SelectionDAG &DAG) const { 2489 switch (cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue()) { 2490 default: 2491 return SDValue(); 2492 case Intrinsic::mips_extp: 2493 return LowerDSPIntr(Op, DAG, MipsISD::EXTP, true, false); 2494 case Intrinsic::mips_extpdp: 2495 return LowerDSPIntr(Op, DAG, MipsISD::EXTPDP, true, false); 2496 case Intrinsic::mips_extr_w: 2497 return LowerDSPIntr(Op, DAG, MipsISD::EXTR_W, true, false); 2498 case Intrinsic::mips_extr_r_w: 2499 return LowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W, true, false); 2500 case Intrinsic::mips_extr_rs_w: 2501 return LowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W, true, false); 2502 case Intrinsic::mips_extr_s_h: 2503 return LowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H, true, false); 2504 case Intrinsic::mips_mthlip: 2505 return LowerDSPIntr(Op, DAG, MipsISD::MTHLIP, true, true); 2506 case Intrinsic::mips_mulsaq_s_w_ph: 2507 return LowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH, true, true); 2508 case Intrinsic::mips_maq_s_w_phl: 2509 return LowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL, true, true); 2510 case Intrinsic::mips_maq_s_w_phr: 2511 return LowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR, true, true); 2512 case Intrinsic::mips_maq_sa_w_phl: 2513 return LowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL, true, true); 2514 case Intrinsic::mips_maq_sa_w_phr: 2515 return LowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR, true, true); 2516 case Intrinsic::mips_dpaq_s_w_ph: 2517 return LowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH, true, true); 2518 case Intrinsic::mips_dpsq_s_w_ph: 2519 return LowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH, true, true); 2520 case Intrinsic::mips_dpaq_sa_l_w: 2521 return LowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W, true, true); 2522 case Intrinsic::mips_dpsq_sa_l_w: 2523 return LowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W, true, true); 2524 case Intrinsic::mips_dpaqx_s_w_ph: 2525 return LowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH, true, true); 2526 case Intrinsic::mips_dpaqx_sa_w_ph: 2527 return LowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH, true, true); 2528 case Intrinsic::mips_dpsqx_s_w_ph: 2529 return LowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH, true, true); 2530 case Intrinsic::mips_dpsqx_sa_w_ph: 2531 return LowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH, true, true); 2532 } 2533} 2534 2535SDValue MipsTargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const { 2536 if (Op->getOperand(0).getOpcode() != ISD::FRAMEADDR 2537 || cast<ConstantSDNode> 2538 (Op->getOperand(0).getOperand(0))->getZExtValue() != 0 2539 || Op->getOperand(1).getOpcode() != ISD::FRAME_TO_ARGS_OFFSET) 2540 return SDValue(); 2541 2542 // The pattern 2543 // (add (frameaddr 0), (frame_to_args_offset)) 2544 // results from lowering llvm.eh.dwarf.cfa intrinsic. Transform it to 2545 // (add FrameObject, 0) 2546 // where FrameObject is a fixed StackObject with offset 0 which points to 2547 // the old stack pointer. 2548 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2549 EVT ValTy = Op->getValueType(0); 2550 int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false); 2551 SDValue InArgsAddr = DAG.getFrameIndex(FI, ValTy); 2552 return DAG.getNode(ISD::ADD, Op->getDebugLoc(), ValTy, InArgsAddr, 2553 DAG.getConstant(0, ValTy)); 2554} 2555 2556//===----------------------------------------------------------------------===// 2557// Calling Convention Implementation 2558//===----------------------------------------------------------------------===// 2559 2560//===----------------------------------------------------------------------===// 2561// TODO: Implement a generic logic using tblgen that can support this. 2562// Mips O32 ABI rules: 2563// --- 2564// i32 - Passed in A0, A1, A2, A3 and stack 2565// f32 - Only passed in f32 registers if no int reg has been used yet to hold 2566// an argument. Otherwise, passed in A1, A2, A3 and stack. 2567// f64 - Only passed in two aliased f32 registers if no int reg has been used 2568// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 2569// not used, it must be shadowed. If only A3 is avaiable, shadow it and 2570// go to stack. 2571// 2572// For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 2573//===----------------------------------------------------------------------===// 2574 2575static bool CC_MipsO32(unsigned ValNo, MVT ValVT, 2576 MVT LocVT, CCValAssign::LocInfo LocInfo, 2577 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2578 2579 static const unsigned IntRegsSize=4, FloatRegsSize=2; 2580 2581 static const uint16_t IntRegs[] = { 2582 Mips::A0, Mips::A1, Mips::A2, Mips::A3 2583 }; 2584 static const uint16_t F32Regs[] = { 2585 Mips::F12, Mips::F14 2586 }; 2587 static const uint16_t F64Regs[] = { 2588 Mips::D6, Mips::D7 2589 }; 2590 2591 // Do not process byval args here. 2592 if (ArgFlags.isByVal()) 2593 return true; 2594 2595 // Promote i8 and i16 2596 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 2597 LocVT = MVT::i32; 2598 if (ArgFlags.isSExt()) 2599 LocInfo = CCValAssign::SExt; 2600 else if (ArgFlags.isZExt()) 2601 LocInfo = CCValAssign::ZExt; 2602 else 2603 LocInfo = CCValAssign::AExt; 2604 } 2605 2606 unsigned Reg; 2607 2608 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 2609 // is true: function is vararg, argument is 3rd or higher, there is previous 2610 // argument which is not f32 or f64. 2611 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 2612 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo; 2613 unsigned OrigAlign = ArgFlags.getOrigAlign(); 2614 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8); 2615 2616 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 2617 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2618 // If this is the first part of an i64 arg, 2619 // the allocated register must be either A0 or A2. 2620 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 2621 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2622 LocVT = MVT::i32; 2623 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 2624 // Allocate int register and shadow next int register. If first 2625 // available register is Mips::A1 or Mips::A3, shadow it too. 2626 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2627 if (Reg == Mips::A1 || Reg == Mips::A3) 2628 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2629 State.AllocateReg(IntRegs, IntRegsSize); 2630 LocVT = MVT::i32; 2631 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 2632 // we are guaranteed to find an available float register 2633 if (ValVT == MVT::f32) { 2634 Reg = State.AllocateReg(F32Regs, FloatRegsSize); 2635 // Shadow int register 2636 State.AllocateReg(IntRegs, IntRegsSize); 2637 } else { 2638 Reg = State.AllocateReg(F64Regs, FloatRegsSize); 2639 // Shadow int registers 2640 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize); 2641 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 2642 State.AllocateReg(IntRegs, IntRegsSize); 2643 State.AllocateReg(IntRegs, IntRegsSize); 2644 } 2645 } else 2646 llvm_unreachable("Cannot handle this ValVT."); 2647 2648 if (!Reg) { 2649 unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3, 2650 OrigAlign); 2651 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 2652 } else 2653 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2654 2655 return false; 2656} 2657 2658#include "MipsGenCallingConv.inc" 2659 2660//===----------------------------------------------------------------------===// 2661// Call Calling Convention Implementation 2662//===----------------------------------------------------------------------===// 2663 2664static const unsigned O32IntRegsSize = 4; 2665 2666// Return next O32 integer argument register. 2667static unsigned getNextIntArgReg(unsigned Reg) { 2668 assert((Reg == Mips::A0) || (Reg == Mips::A2)); 2669 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3; 2670} 2671 2672/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2673/// for tail call optimization. 2674bool MipsTargetLowering:: 2675IsEligibleForTailCallOptimization(const MipsCC &MipsCCInfo, 2676 unsigned NextStackOffset, 2677 const MipsFunctionInfo& FI) const { 2678 if (!EnableMipsTailCalls) 2679 return false; 2680 2681 // No tail call optimization for mips16. 2682 if (Subtarget->inMips16Mode()) 2683 return false; 2684 2685 // Return false if either the callee or caller has a byval argument. 2686 if (MipsCCInfo.hasByValArg() || FI.hasByvalArg()) 2687 return false; 2688 2689 // Return true if the callee's argument area is no larger than the 2690 // caller's. 2691 return NextStackOffset <= FI.getIncomingArgSize(); 2692} 2693 2694SDValue 2695MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset, 2696 SDValue Chain, SDValue Arg, DebugLoc DL, 2697 bool IsTailCall, SelectionDAG &DAG) const { 2698 if (!IsTailCall) { 2699 SDValue PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, 2700 DAG.getIntPtrConstant(Offset)); 2701 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), false, 2702 false, 0); 2703 } 2704 2705 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2706 int FI = MFI->CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false); 2707 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2708 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(), 2709 /*isVolatile=*/ true, false, 0); 2710} 2711 2712/// LowerCall - functions arguments are copied from virtual regs to 2713/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 2714SDValue 2715MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 2716 SmallVectorImpl<SDValue> &InVals) const { 2717 SelectionDAG &DAG = CLI.DAG; 2718 DebugLoc &dl = CLI.DL; 2719 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; 2720 SmallVector<SDValue, 32> &OutVals = CLI.OutVals; 2721 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; 2722 SDValue Chain = CLI.Chain; 2723 SDValue Callee = CLI.Callee; 2724 bool &isTailCall = CLI.IsTailCall; 2725 CallingConv::ID CallConv = CLI.CallConv; 2726 bool isVarArg = CLI.IsVarArg; 2727 2728 MachineFunction &MF = DAG.getMachineFunction(); 2729 MachineFrameInfo *MFI = MF.getFrameInfo(); 2730 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering(); 2731 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 2732 2733 // Analyze operands of the call, assigning locations to each operand. 2734 SmallVector<CCValAssign, 16> ArgLocs; 2735 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2736 getTargetMachine(), ArgLocs, *DAG.getContext()); 2737 MipsCC MipsCCInfo(CallConv, isVarArg, IsO32, CCInfo); 2738 2739 MipsCCInfo.analyzeCallOperands(Outs); 2740 2741 // Get a count of how many bytes are to be pushed on the stack. 2742 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 2743 2744 // Check if it's really possible to do a tail call. 2745 if (isTailCall) 2746 isTailCall = 2747 IsEligibleForTailCallOptimization(MipsCCInfo, NextStackOffset, 2748 *MF.getInfo<MipsFunctionInfo>()); 2749 2750 if (isTailCall) 2751 ++NumTailCalls; 2752 2753 // Chain is the output chain of the last Load/Store or CopyToReg node. 2754 // ByValChain is the output chain of the last Memcpy node created for copying 2755 // byval arguments to the stack. 2756 unsigned StackAlignment = TFL->getStackAlignment(); 2757 NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment); 2758 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true); 2759 2760 if (!isTailCall) 2761 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal); 2762 2763 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, 2764 IsN64 ? Mips::SP_64 : Mips::SP, 2765 getPointerTy()); 2766 2767 // With EABI is it possible to have 16 args on registers. 2768 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass; 2769 SmallVector<SDValue, 8> MemOpChains; 2770 MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin(); 2771 2772 // Walk the register/memloc assignments, inserting copies/loads. 2773 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2774 SDValue Arg = OutVals[i]; 2775 CCValAssign &VA = ArgLocs[i]; 2776 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); 2777 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2778 2779 // ByVal Arg. 2780 if (Flags.isByVal()) { 2781 assert(Flags.getByValSize() && 2782 "ByVal args of size 0 should have been ignored by front-end."); 2783 assert(ByValArg != MipsCCInfo.byval_end()); 2784 assert(!isTailCall && 2785 "Do not tail-call optimize if there is a byval argument."); 2786 passByValArg(Chain, dl, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg, 2787 MipsCCInfo, *ByValArg, Flags, Subtarget->isLittle()); 2788 ++ByValArg; 2789 continue; 2790 } 2791 2792 // Promote the value if needed. 2793 switch (VA.getLocInfo()) { 2794 default: llvm_unreachable("Unknown loc info!"); 2795 case CCValAssign::Full: 2796 if (VA.isRegLoc()) { 2797 if ((ValVT == MVT::f32 && LocVT == MVT::i32) || 2798 (ValVT == MVT::f64 && LocVT == MVT::i64)) 2799 Arg = DAG.getNode(ISD::BITCAST, dl, LocVT, Arg); 2800 else if (ValVT == MVT::f64 && LocVT == MVT::i32) { 2801 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 2802 Arg, DAG.getConstant(0, MVT::i32)); 2803 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 2804 Arg, DAG.getConstant(1, MVT::i32)); 2805 if (!Subtarget->isLittle()) 2806 std::swap(Lo, Hi); 2807 unsigned LocRegLo = VA.getLocReg(); 2808 unsigned LocRegHigh = getNextIntArgReg(LocRegLo); 2809 RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); 2810 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); 2811 continue; 2812 } 2813 } 2814 break; 2815 case CCValAssign::SExt: 2816 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, LocVT, Arg); 2817 break; 2818 case CCValAssign::ZExt: 2819 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, LocVT, Arg); 2820 break; 2821 case CCValAssign::AExt: 2822 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, LocVT, Arg); 2823 break; 2824 } 2825 2826 // Arguments that can be passed on register must be kept at 2827 // RegsToPass vector 2828 if (VA.isRegLoc()) { 2829 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2830 continue; 2831 } 2832 2833 // Register can't get to this point... 2834 assert(VA.isMemLoc()); 2835 2836 // emit ISD::STORE whichs stores the 2837 // parameter value to a stack Location 2838 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(), 2839 Chain, Arg, dl, isTailCall, DAG)); 2840 } 2841 2842 // Transform all store nodes into one single node because all store 2843 // nodes are independent of each other. 2844 if (!MemOpChains.empty()) 2845 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2846 &MemOpChains[0], MemOpChains.size()); 2847 2848 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 2849 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 2850 // node so that legalize doesn't hack it. 2851 bool IsPICCall = (IsN64 || IsPIC); // true if calls are translated to jalr $25 2852 bool GlobalOrExternal = false; 2853 SDValue CalleeLo; 2854 2855 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2856 if (IsPICCall) { 2857 if (G->getGlobal()->hasInternalLinkage()) 2858 Callee = getAddrLocal(Callee, DAG, HasMips64); 2859 else if (LargeGOT) 2860 Callee = getAddrGlobalLargeGOT(Callee, DAG, MipsII::MO_CALL_HI16, 2861 MipsII::MO_CALL_LO16); 2862 else 2863 Callee = getAddrGlobal(Callee, DAG, MipsII::MO_GOT_CALL); 2864 } else 2865 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 0, 2866 MipsII::MO_NO_FLAG); 2867 GlobalOrExternal = true; 2868 } 2869 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2870 if (!IsN64 && !IsPIC) // !N64 && static 2871 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2872 MipsII::MO_NO_FLAG); 2873 else if (LargeGOT) 2874 Callee = getAddrGlobalLargeGOT(Callee, DAG, MipsII::MO_CALL_HI16, 2875 MipsII::MO_CALL_LO16); 2876 else if (HasMips64) 2877 Callee = getAddrGlobal(Callee, DAG, MipsII::MO_GOT_DISP); 2878 else // O32 & PIC 2879 Callee = getAddrGlobal(Callee, DAG, MipsII::MO_GOT_CALL); 2880 2881 GlobalOrExternal = true; 2882 } 2883 2884 SDValue InFlag; 2885 2886 // T9 register operand. 2887 SDValue T9; 2888 2889 // T9 should contain the address of the callee function if 2890 // -reloction-model=pic or it is an indirect call. 2891 if (IsPICCall || !GlobalOrExternal) { 2892 // copy to T9 2893 unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9; 2894 Chain = DAG.getCopyToReg(Chain, dl, T9Reg, Callee, SDValue(0, 0)); 2895 InFlag = Chain.getValue(1); 2896 2897 if (Subtarget->inMips16Mode()) 2898 T9 = DAG.getRegister(T9Reg, getPointerTy()); 2899 else 2900 Callee = DAG.getRegister(T9Reg, getPointerTy()); 2901 } 2902 2903 // Insert node "GP copy globalreg" before call to function. 2904 // Lazy-binding stubs require GP to point to the GOT. 2905 if (IsPICCall) { 2906 unsigned GPReg = IsN64 ? Mips::GP_64 : Mips::GP; 2907 EVT Ty = IsN64 ? MVT::i64 : MVT::i32; 2908 RegsToPass.push_back(std::make_pair(GPReg, GetGlobalReg(DAG, Ty))); 2909 } 2910 2911 // Build a sequence of copy-to-reg nodes chained together with token 2912 // chain and flag operands which copy the outgoing args into registers. 2913 // The InFlag in necessary since all emitted instructions must be 2914 // stuck together. 2915 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2916 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2917 RegsToPass[i].second, InFlag); 2918 InFlag = Chain.getValue(1); 2919 } 2920 2921 // MipsJmpLink = #chain, #target_address, #opt_in_flags... 2922 // = Chain, Callee, Reg#1, Reg#2, ... 2923 // 2924 // Returns a chain & a flag for retval copy to use. 2925 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2926 SmallVector<SDValue, 8> Ops; 2927 Ops.push_back(Chain); 2928 Ops.push_back(Callee); 2929 2930 // Add argument registers to the end of the list so that they are 2931 // known live into the call. 2932 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2933 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2934 RegsToPass[i].second.getValueType())); 2935 2936 // Add T9 register operand. 2937 if (T9.getNode()) 2938 Ops.push_back(T9); 2939 2940 // Add a register mask operand representing the call-preserved registers. 2941 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 2942 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv); 2943 assert(Mask && "Missing call preserved mask for calling convention"); 2944 Ops.push_back(DAG.getRegisterMask(Mask)); 2945 2946 if (InFlag.getNode()) 2947 Ops.push_back(InFlag); 2948 2949 if (isTailCall) 2950 return DAG.getNode(MipsISD::TailCall, dl, MVT::Other, &Ops[0], Ops.size()); 2951 2952 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size()); 2953 InFlag = Chain.getValue(1); 2954 2955 // Create the CALLSEQ_END node. 2956 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal, 2957 DAG.getIntPtrConstant(0, true), InFlag); 2958 InFlag = Chain.getValue(1); 2959 2960 // Handle result values, copying them out of physregs into vregs that we 2961 // return. 2962 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2963 Ins, dl, DAG, InVals); 2964} 2965 2966/// LowerCallResult - Lower the result values of a call into the 2967/// appropriate copies out of appropriate physical registers. 2968SDValue 2969MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 2970 CallingConv::ID CallConv, bool isVarArg, 2971 const SmallVectorImpl<ISD::InputArg> &Ins, 2972 DebugLoc dl, SelectionDAG &DAG, 2973 SmallVectorImpl<SDValue> &InVals) const { 2974 // Assign locations to each value returned by this call. 2975 SmallVector<CCValAssign, 16> RVLocs; 2976 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2977 getTargetMachine(), RVLocs, *DAG.getContext()); 2978 2979 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips); 2980 2981 // Copy all of the result registers out of their specified physreg. 2982 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2983 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), 2984 RVLocs[i].getValVT(), InFlag).getValue(1); 2985 InFlag = Chain.getValue(2); 2986 InVals.push_back(Chain.getValue(0)); 2987 } 2988 2989 return Chain; 2990} 2991 2992//===----------------------------------------------------------------------===// 2993// Formal Arguments Calling Convention Implementation 2994//===----------------------------------------------------------------------===// 2995/// LowerFormalArguments - transform physical registers into virtual registers 2996/// and generate load operations for arguments places on the stack. 2997SDValue 2998MipsTargetLowering::LowerFormalArguments(SDValue Chain, 2999 CallingConv::ID CallConv, 3000 bool isVarArg, 3001 const SmallVectorImpl<ISD::InputArg> &Ins, 3002 DebugLoc dl, SelectionDAG &DAG, 3003 SmallVectorImpl<SDValue> &InVals) 3004 const { 3005 MachineFunction &MF = DAG.getMachineFunction(); 3006 MachineFrameInfo *MFI = MF.getFrameInfo(); 3007 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3008 3009 MipsFI->setVarArgsFrameIndex(0); 3010 3011 // Used with vargs to acumulate store chains. 3012 std::vector<SDValue> OutChains; 3013 3014 // Assign locations to all of the incoming arguments. 3015 SmallVector<CCValAssign, 16> ArgLocs; 3016 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 3017 getTargetMachine(), ArgLocs, *DAG.getContext()); 3018 MipsCC MipsCCInfo(CallConv, isVarArg, IsO32, CCInfo); 3019 3020 MipsCCInfo.analyzeFormalArguments(Ins); 3021 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(), 3022 MipsCCInfo.hasByValArg()); 3023 3024 Function::const_arg_iterator FuncArg = 3025 DAG.getMachineFunction().getFunction()->arg_begin(); 3026 unsigned CurArgIdx = 0; 3027 MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin(); 3028 3029 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 3030 CCValAssign &VA = ArgLocs[i]; 3031 std::advance(FuncArg, Ins[i].OrigArgIndex - CurArgIdx); 3032 CurArgIdx = Ins[i].OrigArgIndex; 3033 EVT ValVT = VA.getValVT(); 3034 ISD::ArgFlagsTy Flags = Ins[i].Flags; 3035 bool IsRegLoc = VA.isRegLoc(); 3036 3037 if (Flags.isByVal()) { 3038 assert(Flags.getByValSize() && 3039 "ByVal args of size 0 should have been ignored by front-end."); 3040 assert(ByValArg != MipsCCInfo.byval_end()); 3041 copyByValRegs(Chain, dl, OutChains, DAG, Flags, InVals, &*FuncArg, 3042 MipsCCInfo, *ByValArg); 3043 ++ByValArg; 3044 continue; 3045 } 3046 3047 // Arguments stored on registers 3048 if (IsRegLoc) { 3049 EVT RegVT = VA.getLocVT(); 3050 unsigned ArgReg = VA.getLocReg(); 3051 const TargetRegisterClass *RC; 3052 3053 if (RegVT == MVT::i32) 3054 RC = &Mips::CPURegsRegClass; 3055 else if (RegVT == MVT::i64) 3056 RC = &Mips::CPU64RegsRegClass; 3057 else if (RegVT == MVT::f32) 3058 RC = &Mips::FGR32RegClass; 3059 else if (RegVT == MVT::f64) 3060 RC = HasMips64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; 3061 else 3062 llvm_unreachable("RegVT not supported by FormalArguments Lowering"); 3063 3064 // Transform the arguments stored on 3065 // physical registers into virtual ones 3066 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgReg, RC); 3067 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 3068 3069 // If this is an 8 or 16-bit value, it has been passed promoted 3070 // to 32 bits. Insert an assert[sz]ext to capture this, then 3071 // truncate to the right size. 3072 if (VA.getLocInfo() != CCValAssign::Full) { 3073 unsigned Opcode = 0; 3074 if (VA.getLocInfo() == CCValAssign::SExt) 3075 Opcode = ISD::AssertSext; 3076 else if (VA.getLocInfo() == CCValAssign::ZExt) 3077 Opcode = ISD::AssertZext; 3078 if (Opcode) 3079 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue, 3080 DAG.getValueType(ValVT)); 3081 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, ValVT, ArgValue); 3082 } 3083 3084 // Handle floating point arguments passed in integer registers. 3085 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || 3086 (RegVT == MVT::i64 && ValVT == MVT::f64)) 3087 ArgValue = DAG.getNode(ISD::BITCAST, dl, ValVT, ArgValue); 3088 else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) { 3089 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(), 3090 getNextIntArgReg(ArgReg), RC); 3091 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT); 3092 if (!Subtarget->isLittle()) 3093 std::swap(ArgValue, ArgValue2); 3094 ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64, 3095 ArgValue, ArgValue2); 3096 } 3097 3098 InVals.push_back(ArgValue); 3099 } else { // VA.isRegLoc() 3100 3101 // sanity check 3102 assert(VA.isMemLoc()); 3103 3104 // The stack pointer offset is relative to the caller stack frame. 3105 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 3106 VA.getLocMemOffset(), true); 3107 3108 // Create load nodes to retrieve arguments from the stack 3109 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 3110 InVals.push_back(DAG.getLoad(ValVT, dl, Chain, FIN, 3111 MachinePointerInfo::getFixedStack(FI), 3112 false, false, false, 0)); 3113 } 3114 } 3115 3116 // The mips ABIs for returning structs by value requires that we copy 3117 // the sret argument into $v0 for the return. Save the argument into 3118 // a virtual register so that we can access it from the return points. 3119 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 3120 unsigned Reg = MipsFI->getSRetReturnReg(); 3121 if (!Reg) { 3122 Reg = MF.getRegInfo(). 3123 createVirtualRegister(getRegClassFor(IsN64 ? MVT::i64 : MVT::i32)); 3124 MipsFI->setSRetReturnReg(Reg); 3125 } 3126 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 3127 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 3128 } 3129 3130 if (isVarArg) 3131 writeVarArgRegs(OutChains, MipsCCInfo, Chain, dl, DAG); 3132 3133 // All stores are grouped in one node to allow the matching between 3134 // the size of Ins and InVals. This only happens when on varg functions 3135 if (!OutChains.empty()) { 3136 OutChains.push_back(Chain); 3137 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3138 &OutChains[0], OutChains.size()); 3139 } 3140 3141 return Chain; 3142} 3143 3144//===----------------------------------------------------------------------===// 3145// Return Value Calling Convention Implementation 3146//===----------------------------------------------------------------------===// 3147 3148bool 3149MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv, 3150 MachineFunction &MF, bool isVarArg, 3151 const SmallVectorImpl<ISD::OutputArg> &Outs, 3152 LLVMContext &Context) const { 3153 SmallVector<CCValAssign, 16> RVLocs; 3154 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 3155 RVLocs, Context); 3156 return CCInfo.CheckReturn(Outs, RetCC_Mips); 3157} 3158 3159SDValue 3160MipsTargetLowering::LowerReturn(SDValue Chain, 3161 CallingConv::ID CallConv, bool isVarArg, 3162 const SmallVectorImpl<ISD::OutputArg> &Outs, 3163 const SmallVectorImpl<SDValue> &OutVals, 3164 DebugLoc dl, SelectionDAG &DAG) const { 3165 3166 // CCValAssign - represent the assignment of 3167 // the return value to a location 3168 SmallVector<CCValAssign, 16> RVLocs; 3169 3170 // CCState - Info about the registers and stack slot. 3171 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 3172 getTargetMachine(), RVLocs, *DAG.getContext()); 3173 3174 // Analize return values. 3175 CCInfo.AnalyzeReturn(Outs, RetCC_Mips); 3176 3177 // If this is the first return lowered for this function, add 3178 // the regs to the liveout set for the function. 3179 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 3180 for (unsigned i = 0; i != RVLocs.size(); ++i) 3181 if (RVLocs[i].isRegLoc()) 3182 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 3183 } 3184 3185 SDValue Flag; 3186 3187 // Copy the result values into the output registers. 3188 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3189 CCValAssign &VA = RVLocs[i]; 3190 assert(VA.isRegLoc() && "Can only return in registers!"); 3191 3192 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); 3193 3194 // guarantee that all emitted copies are 3195 // stuck together, avoiding something bad 3196 Flag = Chain.getValue(1); 3197 } 3198 3199 // The mips ABIs for returning structs by value requires that we copy 3200 // the sret argument into $v0 for the return. We saved the argument into 3201 // a virtual register in the entry block, so now we copy the value out 3202 // and into $v0. 3203 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 3204 MachineFunction &MF = DAG.getMachineFunction(); 3205 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3206 unsigned Reg = MipsFI->getSRetReturnReg(); 3207 3208 if (!Reg) 3209 llvm_unreachable("sret virtual register not created in the entry block"); 3210 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 3211 unsigned V0 = IsN64 ? Mips::V0_64 : Mips::V0; 3212 3213 Chain = DAG.getCopyToReg(Chain, dl, V0, Val, Flag); 3214 Flag = Chain.getValue(1); 3215 MF.getRegInfo().addLiveOut(V0); 3216 } 3217 3218 // Return on Mips is always a "jr $ra" 3219 if (Flag.getNode()) 3220 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, Chain, Flag); 3221 3222 // Return Void 3223 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, Chain); 3224} 3225 3226//===----------------------------------------------------------------------===// 3227// Mips Inline Assembly Support 3228//===----------------------------------------------------------------------===// 3229 3230/// getConstraintType - Given a constraint letter, return the type of 3231/// constraint it is for this target. 3232MipsTargetLowering::ConstraintType MipsTargetLowering:: 3233getConstraintType(const std::string &Constraint) const 3234{ 3235 // Mips specific constrainy 3236 // GCC config/mips/constraints.md 3237 // 3238 // 'd' : An address register. Equivalent to r 3239 // unless generating MIPS16 code. 3240 // 'y' : Equivalent to r; retained for 3241 // backwards compatibility. 3242 // 'c' : A register suitable for use in an indirect 3243 // jump. This will always be $25 for -mabicalls. 3244 // 'l' : The lo register. 1 word storage. 3245 // 'x' : The hilo register pair. Double word storage. 3246 if (Constraint.size() == 1) { 3247 switch (Constraint[0]) { 3248 default : break; 3249 case 'd': 3250 case 'y': 3251 case 'f': 3252 case 'c': 3253 case 'l': 3254 case 'x': 3255 return C_RegisterClass; 3256 } 3257 } 3258 return TargetLowering::getConstraintType(Constraint); 3259} 3260 3261/// Examine constraint type and operand type and determine a weight value. 3262/// This object must already have been set up with the operand type 3263/// and the current alternative constraint selected. 3264TargetLowering::ConstraintWeight 3265MipsTargetLowering::getSingleConstraintMatchWeight( 3266 AsmOperandInfo &info, const char *constraint) const { 3267 ConstraintWeight weight = CW_Invalid; 3268 Value *CallOperandVal = info.CallOperandVal; 3269 // If we don't have a value, we can't do a match, 3270 // but allow it at the lowest weight. 3271 if (CallOperandVal == NULL) 3272 return CW_Default; 3273 Type *type = CallOperandVal->getType(); 3274 // Look at the constraint type. 3275 switch (*constraint) { 3276 default: 3277 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 3278 break; 3279 case 'd': 3280 case 'y': 3281 if (type->isIntegerTy()) 3282 weight = CW_Register; 3283 break; 3284 case 'f': 3285 if (type->isFloatTy()) 3286 weight = CW_Register; 3287 break; 3288 case 'c': // $25 for indirect jumps 3289 case 'l': // lo register 3290 case 'x': // hilo register pair 3291 if (type->isIntegerTy()) 3292 weight = CW_SpecificReg; 3293 break; 3294 case 'I': // signed 16 bit immediate 3295 case 'J': // integer zero 3296 case 'K': // unsigned 16 bit immediate 3297 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3298 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3299 case 'O': // signed 15 bit immediate (+- 16383) 3300 case 'P': // immediate in the range of 65535 to 1 (inclusive) 3301 if (isa<ConstantInt>(CallOperandVal)) 3302 weight = CW_Constant; 3303 break; 3304 } 3305 return weight; 3306} 3307 3308/// Given a register class constraint, like 'r', if this corresponds directly 3309/// to an LLVM register class, return a register of 0 and the register class 3310/// pointer. 3311std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering:: 3312getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const 3313{ 3314 if (Constraint.size() == 1) { 3315 switch (Constraint[0]) { 3316 case 'd': // Address register. Same as 'r' unless generating MIPS16 code. 3317 case 'y': // Same as 'r'. Exists for compatibility. 3318 case 'r': 3319 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { 3320 if (Subtarget->inMips16Mode()) 3321 return std::make_pair(0U, &Mips::CPU16RegsRegClass); 3322 return std::make_pair(0U, &Mips::CPURegsRegClass); 3323 } 3324 if (VT == MVT::i64 && !HasMips64) 3325 return std::make_pair(0U, &Mips::CPURegsRegClass); 3326 if (VT == MVT::i64 && HasMips64) 3327 return std::make_pair(0U, &Mips::CPU64RegsRegClass); 3328 // This will generate an error message 3329 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 3330 case 'f': 3331 if (VT == MVT::f32) 3332 return std::make_pair(0U, &Mips::FGR32RegClass); 3333 if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) { 3334 if (Subtarget->isFP64bit()) 3335 return std::make_pair(0U, &Mips::FGR64RegClass); 3336 return std::make_pair(0U, &Mips::AFGR64RegClass); 3337 } 3338 break; 3339 case 'c': // register suitable for indirect jump 3340 if (VT == MVT::i32) 3341 return std::make_pair((unsigned)Mips::T9, &Mips::CPURegsRegClass); 3342 assert(VT == MVT::i64 && "Unexpected type."); 3343 return std::make_pair((unsigned)Mips::T9_64, &Mips::CPU64RegsRegClass); 3344 case 'l': // register suitable for indirect jump 3345 if (VT == MVT::i32) 3346 return std::make_pair((unsigned)Mips::LO, &Mips::HILORegClass); 3347 return std::make_pair((unsigned)Mips::LO64, &Mips::HILO64RegClass); 3348 case 'x': // register suitable for indirect jump 3349 // Fixme: Not triggering the use of both hi and low 3350 // This will generate an error message 3351 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 3352 } 3353 } 3354 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 3355} 3356 3357/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 3358/// vector. If it is invalid, don't add anything to Ops. 3359void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 3360 std::string &Constraint, 3361 std::vector<SDValue>&Ops, 3362 SelectionDAG &DAG) const { 3363 SDValue Result(0, 0); 3364 3365 // Only support length 1 constraints for now. 3366 if (Constraint.length() > 1) return; 3367 3368 char ConstraintLetter = Constraint[0]; 3369 switch (ConstraintLetter) { 3370 default: break; // This will fall through to the generic implementation 3371 case 'I': // Signed 16 bit constant 3372 // If this fails, the parent routine will give an error 3373 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3374 EVT Type = Op.getValueType(); 3375 int64_t Val = C->getSExtValue(); 3376 if (isInt<16>(Val)) { 3377 Result = DAG.getTargetConstant(Val, Type); 3378 break; 3379 } 3380 } 3381 return; 3382 case 'J': // integer zero 3383 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3384 EVT Type = Op.getValueType(); 3385 int64_t Val = C->getZExtValue(); 3386 if (Val == 0) { 3387 Result = DAG.getTargetConstant(0, Type); 3388 break; 3389 } 3390 } 3391 return; 3392 case 'K': // unsigned 16 bit immediate 3393 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3394 EVT Type = Op.getValueType(); 3395 uint64_t Val = (uint64_t)C->getZExtValue(); 3396 if (isUInt<16>(Val)) { 3397 Result = DAG.getTargetConstant(Val, Type); 3398 break; 3399 } 3400 } 3401 return; 3402 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3403 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3404 EVT Type = Op.getValueType(); 3405 int64_t Val = C->getSExtValue(); 3406 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){ 3407 Result = DAG.getTargetConstant(Val, Type); 3408 break; 3409 } 3410 } 3411 return; 3412 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3413 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3414 EVT Type = Op.getValueType(); 3415 int64_t Val = C->getSExtValue(); 3416 if ((Val >= -65535) && (Val <= -1)) { 3417 Result = DAG.getTargetConstant(Val, Type); 3418 break; 3419 } 3420 } 3421 return; 3422 case 'O': // signed 15 bit immediate 3423 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3424 EVT Type = Op.getValueType(); 3425 int64_t Val = C->getSExtValue(); 3426 if ((isInt<15>(Val))) { 3427 Result = DAG.getTargetConstant(Val, Type); 3428 break; 3429 } 3430 } 3431 return; 3432 case 'P': // immediate in the range of 1 to 65535 (inclusive) 3433 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3434 EVT Type = Op.getValueType(); 3435 int64_t Val = C->getSExtValue(); 3436 if ((Val <= 65535) && (Val >= 1)) { 3437 Result = DAG.getTargetConstant(Val, Type); 3438 break; 3439 } 3440 } 3441 return; 3442 } 3443 3444 if (Result.getNode()) { 3445 Ops.push_back(Result); 3446 return; 3447 } 3448 3449 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 3450} 3451 3452bool 3453MipsTargetLowering::isLegalAddressingMode(const AddrMode &AM, Type *Ty) const { 3454 // No global is ever allowed as a base. 3455 if (AM.BaseGV) 3456 return false; 3457 3458 switch (AM.Scale) { 3459 case 0: // "r+i" or just "i", depending on HasBaseReg. 3460 break; 3461 case 1: 3462 if (!AM.HasBaseReg) // allow "r+i". 3463 break; 3464 return false; // disallow "r+r" or "r+r+i". 3465 default: 3466 return false; 3467 } 3468 3469 return true; 3470} 3471 3472bool 3473MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 3474 // The Mips target isn't yet aware of offsets. 3475 return false; 3476} 3477 3478EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 3479 unsigned SrcAlign, bool IsZeroVal, 3480 bool MemcpyStrSrc, 3481 MachineFunction &MF) const { 3482 if (Subtarget->hasMips64()) 3483 return MVT::i64; 3484 3485 return MVT::i32; 3486} 3487 3488bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3489 if (VT != MVT::f32 && VT != MVT::f64) 3490 return false; 3491 if (Imm.isNegZero()) 3492 return false; 3493 return Imm.isZero(); 3494} 3495 3496unsigned MipsTargetLowering::getJumpTableEncoding() const { 3497 if (IsN64) 3498 return MachineJumpTableInfo::EK_GPRel64BlockAddress; 3499 3500 return TargetLowering::getJumpTableEncoding(); 3501} 3502 3503MipsTargetLowering::MipsCC::MipsCC(CallingConv::ID CallConv, bool IsVarArg, 3504 bool IsO32, CCState &Info) : CCInfo(Info) { 3505 UseRegsForByval = true; 3506 3507 if (IsO32) { 3508 RegSize = 4; 3509 NumIntArgRegs = array_lengthof(O32IntRegs); 3510 ReservedArgArea = 16; 3511 IntArgRegs = ShadowRegs = O32IntRegs; 3512 FixedFn = VarFn = CC_MipsO32; 3513 } else { 3514 RegSize = 8; 3515 NumIntArgRegs = array_lengthof(Mips64IntRegs); 3516 ReservedArgArea = 0; 3517 IntArgRegs = Mips64IntRegs; 3518 ShadowRegs = Mips64DPRegs; 3519 FixedFn = CC_MipsN; 3520 VarFn = CC_MipsN_VarArg; 3521 } 3522 3523 if (CallConv == CallingConv::Fast) { 3524 assert(!IsVarArg); 3525 UseRegsForByval = false; 3526 ReservedArgArea = 0; 3527 FixedFn = VarFn = CC_Mips_FastCC; 3528 } 3529 3530 // Pre-allocate reserved argument area. 3531 CCInfo.AllocateStack(ReservedArgArea, 1); 3532} 3533 3534void MipsTargetLowering::MipsCC:: 3535analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Args) { 3536 unsigned NumOpnds = Args.size(); 3537 3538 for (unsigned I = 0; I != NumOpnds; ++I) { 3539 MVT ArgVT = Args[I].VT; 3540 ISD::ArgFlagsTy ArgFlags = Args[I].Flags; 3541 bool R; 3542 3543 if (ArgFlags.isByVal()) { 3544 handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags); 3545 continue; 3546 } 3547 3548 if (Args[I].IsFixed) 3549 R = FixedFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo); 3550 else 3551 R = VarFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo); 3552 3553 if (R) { 3554#ifndef NDEBUG 3555 dbgs() << "Call operand #" << I << " has unhandled type " 3556 << EVT(ArgVT).getEVTString(); 3557#endif 3558 llvm_unreachable(0); 3559 } 3560 } 3561} 3562 3563void MipsTargetLowering::MipsCC:: 3564analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Args) { 3565 unsigned NumArgs = Args.size(); 3566 3567 for (unsigned I = 0; I != NumArgs; ++I) { 3568 MVT ArgVT = Args[I].VT; 3569 ISD::ArgFlagsTy ArgFlags = Args[I].Flags; 3570 3571 if (ArgFlags.isByVal()) { 3572 handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags); 3573 continue; 3574 } 3575 3576 if (!FixedFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo)) 3577 continue; 3578 3579#ifndef NDEBUG 3580 dbgs() << "Formal Arg #" << I << " has unhandled type " 3581 << EVT(ArgVT).getEVTString(); 3582#endif 3583 llvm_unreachable(0); 3584 } 3585} 3586 3587void 3588MipsTargetLowering::MipsCC::handleByValArg(unsigned ValNo, MVT ValVT, 3589 MVT LocVT, 3590 CCValAssign::LocInfo LocInfo, 3591 ISD::ArgFlagsTy ArgFlags) { 3592 assert(ArgFlags.getByValSize() && "Byval argument's size shouldn't be 0."); 3593 3594 struct ByValArgInfo ByVal; 3595 unsigned ByValSize = RoundUpToAlignment(ArgFlags.getByValSize(), RegSize); 3596 unsigned Align = std::min(std::max(ArgFlags.getByValAlign(), RegSize), 3597 RegSize * 2); 3598 3599 if (UseRegsForByval) 3600 allocateRegs(ByVal, ByValSize, Align); 3601 3602 // Allocate space on caller's stack. 3603 ByVal.Address = CCInfo.AllocateStack(ByValSize - RegSize * ByVal.NumRegs, 3604 Align); 3605 CCInfo.addLoc(CCValAssign::getMem(ValNo, ValVT, ByVal.Address, LocVT, 3606 LocInfo)); 3607 ByValArgs.push_back(ByVal); 3608} 3609 3610void MipsTargetLowering::MipsCC::allocateRegs(ByValArgInfo &ByVal, 3611 unsigned ByValSize, 3612 unsigned Align) { 3613 assert(!(ByValSize % RegSize) && !(Align % RegSize) && 3614 "Byval argument's size and alignment should be a multiple of" 3615 "RegSize."); 3616 3617 ByVal.FirstIdx = CCInfo.getFirstUnallocated(IntArgRegs, NumIntArgRegs); 3618 3619 // If Align > RegSize, the first arg register must be even. 3620 if ((Align > RegSize) && (ByVal.FirstIdx % 2)) { 3621 CCInfo.AllocateReg(IntArgRegs[ByVal.FirstIdx], ShadowRegs[ByVal.FirstIdx]); 3622 ++ByVal.FirstIdx; 3623 } 3624 3625 // Mark the registers allocated. 3626 for (unsigned I = ByVal.FirstIdx; ByValSize && (I < NumIntArgRegs); 3627 ByValSize -= RegSize, ++I, ++ByVal.NumRegs) 3628 CCInfo.AllocateReg(IntArgRegs[I], ShadowRegs[I]); 3629} 3630 3631void MipsTargetLowering:: 3632copyByValRegs(SDValue Chain, DebugLoc DL, std::vector<SDValue> &OutChains, 3633 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags, 3634 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg, 3635 const MipsCC &CC, const ByValArgInfo &ByVal) const { 3636 MachineFunction &MF = DAG.getMachineFunction(); 3637 MachineFrameInfo *MFI = MF.getFrameInfo(); 3638 unsigned RegAreaSize = ByVal.NumRegs * CC.regSize(); 3639 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize); 3640 int FrameObjOffset; 3641 3642 if (RegAreaSize) 3643 FrameObjOffset = (int)CC.reservedArgArea() - 3644 (int)((CC.numIntArgRegs() - ByVal.FirstIdx) * CC.regSize()); 3645 else 3646 FrameObjOffset = ByVal.Address; 3647 3648 // Create frame object. 3649 EVT PtrTy = getPointerTy(); 3650 int FI = MFI->CreateFixedObject(FrameObjSize, FrameObjOffset, true); 3651 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 3652 InVals.push_back(FIN); 3653 3654 if (!ByVal.NumRegs) 3655 return; 3656 3657 // Copy arg registers. 3658 MVT RegTy = MVT::getIntegerVT(CC.regSize() * 8); 3659 const TargetRegisterClass *RC = getRegClassFor(RegTy); 3660 3661 for (unsigned I = 0; I < ByVal.NumRegs; ++I) { 3662 unsigned ArgReg = CC.intArgRegs()[ByVal.FirstIdx + I]; 3663 unsigned VReg = AddLiveIn(MF, ArgReg, RC); 3664 unsigned Offset = I * CC.regSize(); 3665 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN, 3666 DAG.getConstant(Offset, PtrTy)); 3667 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy), 3668 StorePtr, MachinePointerInfo(FuncArg, Offset), 3669 false, false, 0); 3670 OutChains.push_back(Store); 3671 } 3672} 3673 3674// Copy byVal arg to registers and stack. 3675void MipsTargetLowering:: 3676passByValArg(SDValue Chain, DebugLoc DL, 3677 SmallVector<std::pair<unsigned, SDValue>, 16> &RegsToPass, 3678 SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr, 3679 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, 3680 const MipsCC &CC, const ByValArgInfo &ByVal, 3681 const ISD::ArgFlagsTy &Flags, bool isLittle) const { 3682 unsigned ByValSize = Flags.getByValSize(); 3683 unsigned Offset = 0; // Offset in # of bytes from the beginning of struct. 3684 unsigned RegSize = CC.regSize(); 3685 unsigned Alignment = std::min(Flags.getByValAlign(), RegSize); 3686 EVT PtrTy = getPointerTy(), RegTy = MVT::getIntegerVT(RegSize * 8); 3687 3688 if (ByVal.NumRegs) { 3689 const uint16_t *ArgRegs = CC.intArgRegs(); 3690 bool LeftoverBytes = (ByVal.NumRegs * RegSize > ByValSize); 3691 unsigned I = 0; 3692 3693 // Copy words to registers. 3694 for (; I < ByVal.NumRegs - LeftoverBytes; ++I, Offset += RegSize) { 3695 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3696 DAG.getConstant(Offset, PtrTy)); 3697 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr, 3698 MachinePointerInfo(), false, false, false, 3699 Alignment); 3700 MemOpChains.push_back(LoadVal.getValue(1)); 3701 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I]; 3702 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal)); 3703 } 3704 3705 // Return if the struct has been fully copied. 3706 if (ByValSize == Offset) 3707 return; 3708 3709 // Copy the remainder of the byval argument with sub-word loads and shifts. 3710 if (LeftoverBytes) { 3711 assert((ByValSize > Offset) && (ByValSize < Offset + RegSize) && 3712 "Size of the remainder should be smaller than RegSize."); 3713 SDValue Val; 3714 3715 for (unsigned LoadSize = RegSize / 2, TotalSizeLoaded = 0; 3716 Offset < ByValSize; LoadSize /= 2) { 3717 unsigned RemSize = ByValSize - Offset; 3718 3719 if (RemSize < LoadSize) 3720 continue; 3721 3722 // Load subword. 3723 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3724 DAG.getConstant(Offset, PtrTy)); 3725 SDValue LoadVal = 3726 DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, 3727 MachinePointerInfo(), MVT::getIntegerVT(LoadSize * 8), 3728 false, false, Alignment); 3729 MemOpChains.push_back(LoadVal.getValue(1)); 3730 3731 // Shift the loaded value. 3732 unsigned Shamt; 3733 3734 if (isLittle) 3735 Shamt = TotalSizeLoaded; 3736 else 3737 Shamt = (RegSize - (TotalSizeLoaded + LoadSize)) * 8; 3738 3739 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal, 3740 DAG.getConstant(Shamt, MVT::i32)); 3741 3742 if (Val.getNode()) 3743 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift); 3744 else 3745 Val = Shift; 3746 3747 Offset += LoadSize; 3748 TotalSizeLoaded += LoadSize; 3749 Alignment = std::min(Alignment, LoadSize); 3750 } 3751 3752 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I]; 3753 RegsToPass.push_back(std::make_pair(ArgReg, Val)); 3754 return; 3755 } 3756 } 3757 3758 // Copy remainder of byval arg to it with memcpy. 3759 unsigned MemCpySize = ByValSize - Offset; 3760 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3761 DAG.getConstant(Offset, PtrTy)); 3762 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr, 3763 DAG.getIntPtrConstant(ByVal.Address)); 3764 Chain = DAG.getMemcpy(Chain, DL, Dst, Src, 3765 DAG.getConstant(MemCpySize, PtrTy), Alignment, 3766 /*isVolatile=*/false, /*AlwaysInline=*/false, 3767 MachinePointerInfo(0), MachinePointerInfo(0)); 3768 MemOpChains.push_back(Chain); 3769} 3770 3771void 3772MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains, 3773 const MipsCC &CC, SDValue Chain, 3774 DebugLoc DL, SelectionDAG &DAG) const { 3775 unsigned NumRegs = CC.numIntArgRegs(); 3776 const uint16_t *ArgRegs = CC.intArgRegs(); 3777 const CCState &CCInfo = CC.getCCInfo(); 3778 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumRegs); 3779 unsigned RegSize = CC.regSize(); 3780 MVT RegTy = MVT::getIntegerVT(RegSize * 8); 3781 const TargetRegisterClass *RC = getRegClassFor(RegTy); 3782 MachineFunction &MF = DAG.getMachineFunction(); 3783 MachineFrameInfo *MFI = MF.getFrameInfo(); 3784 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3785 3786 // Offset of the first variable argument from stack pointer. 3787 int VaArgOffset; 3788 3789 if (NumRegs == Idx) 3790 VaArgOffset = RoundUpToAlignment(CCInfo.getNextStackOffset(), RegSize); 3791 else 3792 VaArgOffset = 3793 (int)CC.reservedArgArea() - (int)(RegSize * (NumRegs - Idx)); 3794 3795 // Record the frame index of the first variable argument 3796 // which is a value necessary to VASTART. 3797 int FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true); 3798 MipsFI->setVarArgsFrameIndex(FI); 3799 3800 // Copy the integer registers that have not been used for argument passing 3801 // to the argument register save area. For O32, the save area is allocated 3802 // in the caller's stack frame, while for N32/64, it is allocated in the 3803 // callee's stack frame. 3804 for (unsigned I = Idx; I < NumRegs; ++I, VaArgOffset += RegSize) { 3805 unsigned Reg = AddLiveIn(MF, ArgRegs[I], RC); 3806 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy); 3807 FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true); 3808 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy()); 3809 SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff, 3810 MachinePointerInfo(), false, false, 0); 3811 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(0); 3812 OutChains.push_back(Store); 3813 } 3814} 3815