MipsISelLowering.cpp revision 93d995719e2459a6e9ccdb2c93a8ede8fa88c899
1//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that Mips uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14#define DEBUG_TYPE "mips-lower" 15#include "MipsISelLowering.h" 16#include "InstPrinter/MipsInstPrinter.h" 17#include "MCTargetDesc/MipsBaseInfo.h" 18#include "MipsMachineFunction.h" 19#include "MipsSubtarget.h" 20#include "MipsTargetMachine.h" 21#include "MipsTargetObjectFile.h" 22#include "llvm/ADT/Statistic.h" 23#include "llvm/CodeGen/CallingConvLower.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineFunction.h" 26#include "llvm/CodeGen/MachineInstrBuilder.h" 27#include "llvm/CodeGen/MachineRegisterInfo.h" 28#include "llvm/CodeGen/SelectionDAGISel.h" 29#include "llvm/CodeGen/ValueTypes.h" 30#include "llvm/IR/CallingConv.h" 31#include "llvm/IR/DerivedTypes.h" 32#include "llvm/IR/GlobalVariable.h" 33#include "llvm/Support/CommandLine.h" 34#include "llvm/Support/Debug.h" 35#include "llvm/Support/ErrorHandling.h" 36#include "llvm/Support/raw_ostream.h" 37#include <cctype> 38 39using namespace llvm; 40 41STATISTIC(NumTailCalls, "Number of tail calls"); 42 43static cl::opt<bool> 44LargeGOT("mxgot", cl::Hidden, 45 cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false)); 46 47static cl::opt<bool> 48NoZeroDivCheck("mno-check-zero-division", cl::Hidden, 49 cl::desc("MIPS: Don't trap on integer division by zero."), 50 cl::init(false)); 51 52static const uint16_t O32IntRegs[4] = { 53 Mips::A0, Mips::A1, Mips::A2, Mips::A3 54}; 55 56static const uint16_t Mips64IntRegs[8] = { 57 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, 58 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64 59}; 60 61static const uint16_t Mips64DPRegs[8] = { 62 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, 63 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64 64}; 65 66// If I is a shifted mask, set the size (Size) and the first bit of the 67// mask (Pos), and return true. 68// For example, if I is 0x003ff800, (Pos, Size) = (11, 11). 69static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { 70 if (!isShiftedMask_64(I)) 71 return false; 72 73 Size = CountPopulation_64(I); 74 Pos = countTrailingZeros(I); 75 return true; 76} 77 78SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const { 79 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>(); 80 return DAG.getRegister(FI->getGlobalBaseReg(), Ty); 81} 82 83static SDValue getTargetNode(SDValue Op, SelectionDAG &DAG, unsigned Flag) { 84 EVT Ty = Op.getValueType(); 85 86 if (GlobalAddressSDNode *N = dyn_cast<GlobalAddressSDNode>(Op)) 87 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(Op), Ty, 0, 88 Flag); 89 if (ExternalSymbolSDNode *N = dyn_cast<ExternalSymbolSDNode>(Op)) 90 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag); 91 if (BlockAddressSDNode *N = dyn_cast<BlockAddressSDNode>(Op)) 92 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag); 93 if (JumpTableSDNode *N = dyn_cast<JumpTableSDNode>(Op)) 94 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag); 95 if (ConstantPoolSDNode *N = dyn_cast<ConstantPoolSDNode>(Op)) 96 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(), 97 N->getOffset(), Flag); 98 99 llvm_unreachable("Unexpected node type."); 100 return SDValue(); 101} 102 103static SDValue getAddrNonPIC(SDValue Op, SelectionDAG &DAG) { 104 SDLoc DL(Op); 105 EVT Ty = Op.getValueType(); 106 SDValue Hi = getTargetNode(Op, DAG, MipsII::MO_ABS_HI); 107 SDValue Lo = getTargetNode(Op, DAG, MipsII::MO_ABS_LO); 108 return DAG.getNode(ISD::ADD, DL, Ty, 109 DAG.getNode(MipsISD::Hi, DL, Ty, Hi), 110 DAG.getNode(MipsISD::Lo, DL, Ty, Lo)); 111} 112 113SDValue MipsTargetLowering::getAddrLocal(SDValue Op, SelectionDAG &DAG, 114 bool HasMips64) const { 115 SDLoc DL(Op); 116 EVT Ty = Op.getValueType(); 117 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT; 118 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty), 119 getTargetNode(Op, DAG, GOTFlag)); 120 SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT, 121 MachinePointerInfo::getGOT(), false, false, false, 122 0); 123 unsigned LoFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO; 124 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty, getTargetNode(Op, DAG, LoFlag)); 125 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo); 126} 127 128SDValue MipsTargetLowering::getAddrGlobal(SDValue Op, SelectionDAG &DAG, 129 unsigned Flag) const { 130 SDLoc DL(Op); 131 EVT Ty = Op.getValueType(); 132 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty), 133 getTargetNode(Op, DAG, Flag)); 134 return DAG.getLoad(Ty, DL, DAG.getEntryNode(), Tgt, 135 MachinePointerInfo::getGOT(), false, false, false, 0); 136} 137 138SDValue MipsTargetLowering::getAddrGlobalLargeGOT(SDValue Op, SelectionDAG &DAG, 139 unsigned HiFlag, 140 unsigned LoFlag) const { 141 SDLoc DL(Op); 142 EVT Ty = Op.getValueType(); 143 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, Ty, getTargetNode(Op, DAG, HiFlag)); 144 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty)); 145 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi, 146 getTargetNode(Op, DAG, LoFlag)); 147 return DAG.getLoad(Ty, DL, DAG.getEntryNode(), Wrapper, 148 MachinePointerInfo::getGOT(), false, false, false, 0); 149} 150 151const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 152 switch (Opcode) { 153 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 154 case MipsISD::TailCall: return "MipsISD::TailCall"; 155 case MipsISD::Hi: return "MipsISD::Hi"; 156 case MipsISD::Lo: return "MipsISD::Lo"; 157 case MipsISD::GPRel: return "MipsISD::GPRel"; 158 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; 159 case MipsISD::Ret: return "MipsISD::Ret"; 160 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN"; 161 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 162 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 163 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 164 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 165 case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP"; 166 case MipsISD::ExtractLOHI: return "MipsISD::ExtractLOHI"; 167 case MipsISD::InsertLOHI: return "MipsISD::InsertLOHI"; 168 case MipsISD::Mult: return "MipsISD::Mult"; 169 case MipsISD::Multu: return "MipsISD::Multu"; 170 case MipsISD::MAdd: return "MipsISD::MAdd"; 171 case MipsISD::MAddu: return "MipsISD::MAddu"; 172 case MipsISD::MSub: return "MipsISD::MSub"; 173 case MipsISD::MSubu: return "MipsISD::MSubu"; 174 case MipsISD::DivRem: return "MipsISD::DivRem"; 175 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 176 case MipsISD::DivRem16: return "MipsISD::DivRem16"; 177 case MipsISD::DivRemU16: return "MipsISD::DivRemU16"; 178 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 179 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 180 case MipsISD::Wrapper: return "MipsISD::Wrapper"; 181 case MipsISD::Sync: return "MipsISD::Sync"; 182 case MipsISD::Ext: return "MipsISD::Ext"; 183 case MipsISD::Ins: return "MipsISD::Ins"; 184 case MipsISD::LWL: return "MipsISD::LWL"; 185 case MipsISD::LWR: return "MipsISD::LWR"; 186 case MipsISD::SWL: return "MipsISD::SWL"; 187 case MipsISD::SWR: return "MipsISD::SWR"; 188 case MipsISD::LDL: return "MipsISD::LDL"; 189 case MipsISD::LDR: return "MipsISD::LDR"; 190 case MipsISD::SDL: return "MipsISD::SDL"; 191 case MipsISD::SDR: return "MipsISD::SDR"; 192 case MipsISD::EXTP: return "MipsISD::EXTP"; 193 case MipsISD::EXTPDP: return "MipsISD::EXTPDP"; 194 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H"; 195 case MipsISD::EXTR_W: return "MipsISD::EXTR_W"; 196 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W"; 197 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W"; 198 case MipsISD::SHILO: return "MipsISD::SHILO"; 199 case MipsISD::MTHLIP: return "MipsISD::MTHLIP"; 200 case MipsISD::MULT: return "MipsISD::MULT"; 201 case MipsISD::MULTU: return "MipsISD::MULTU"; 202 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP"; 203 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP"; 204 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP"; 205 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP"; 206 case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP"; 207 case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP"; 208 case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP"; 209 case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP"; 210 case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP"; 211 case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO"; 212 case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO"; 213 case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO"; 214 case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO"; 215 case MipsISD::VCEQ: return "MipsISD::VCEQ"; 216 case MipsISD::VCLE_S: return "MipsISD::VCLE_S"; 217 case MipsISD::VCLE_U: return "MipsISD::VCLE_U"; 218 case MipsISD::VCLT_S: return "MipsISD::VCLT_S"; 219 case MipsISD::VCLT_U: return "MipsISD::VCLT_U"; 220 case MipsISD::VSMAX: return "MipsISD::VSMAX"; 221 case MipsISD::VSMIN: return "MipsISD::VSMIN"; 222 case MipsISD::VUMAX: return "MipsISD::VUMAX"; 223 case MipsISD::VUMIN: return "MipsISD::VUMIN"; 224 case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT"; 225 case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT"; 226 case MipsISD::VNOR: return "MipsISD::VNOR"; 227 case MipsISD::VSHF: return "MipsISD::VSHF"; 228 case MipsISD::SHF: return "MipsISD::SHF"; 229 default: return NULL; 230 } 231} 232 233MipsTargetLowering:: 234MipsTargetLowering(MipsTargetMachine &TM) 235 : TargetLowering(TM, new MipsTargetObjectFile()), 236 Subtarget(&TM.getSubtarget<MipsSubtarget>()), 237 HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()), 238 IsO32(Subtarget->isABI_O32()) { 239 // Mips does not have i1 type, so use i32 for 240 // setcc operations results (slt, sgt, ...). 241 setBooleanContents(ZeroOrOneBooleanContent); 242 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 243 244 // Load extented operations for i1 types must be promoted 245 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 246 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 247 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 248 249 // MIPS doesn't have extending float->double load/store 250 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 251 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 252 253 // Used by legalize types to correctly generate the setcc result. 254 // Without this, every float setcc comes with a AND/OR with the result, 255 // we don't want this, since the fpcmp result goes to a flag register, 256 // which is used implicitly by brcond and select operations. 257 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 258 259 // Mips Custom Operations 260 setOperationAction(ISD::BR_JT, MVT::Other, Custom); 261 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 262 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 263 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 264 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 265 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 266 setOperationAction(ISD::SELECT, MVT::f32, Custom); 267 setOperationAction(ISD::SELECT, MVT::f64, Custom); 268 setOperationAction(ISD::SELECT, MVT::i32, Custom); 269 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 270 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 271 setOperationAction(ISD::SETCC, MVT::f32, Custom); 272 setOperationAction(ISD::SETCC, MVT::f64, Custom); 273 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 274 setOperationAction(ISD::VASTART, MVT::Other, Custom); 275 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 276 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 277 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 278 279 if (!TM.Options.NoNaNsFPMath) { 280 setOperationAction(ISD::FABS, MVT::f32, Custom); 281 setOperationAction(ISD::FABS, MVT::f64, Custom); 282 } 283 284 if (HasMips64) { 285 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 286 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 287 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 288 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 289 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 290 setOperationAction(ISD::SELECT, MVT::i64, Custom); 291 setOperationAction(ISD::LOAD, MVT::i64, Custom); 292 setOperationAction(ISD::STORE, MVT::i64, Custom); 293 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 294 } 295 296 if (!HasMips64) { 297 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 298 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 299 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 300 } 301 302 setOperationAction(ISD::ADD, MVT::i32, Custom); 303 if (HasMips64) 304 setOperationAction(ISD::ADD, MVT::i64, Custom); 305 306 setOperationAction(ISD::SDIV, MVT::i32, Expand); 307 setOperationAction(ISD::SREM, MVT::i32, Expand); 308 setOperationAction(ISD::UDIV, MVT::i32, Expand); 309 setOperationAction(ISD::UREM, MVT::i32, Expand); 310 setOperationAction(ISD::SDIV, MVT::i64, Expand); 311 setOperationAction(ISD::SREM, MVT::i64, Expand); 312 setOperationAction(ISD::UDIV, MVT::i64, Expand); 313 setOperationAction(ISD::UREM, MVT::i64, Expand); 314 315 // Operations not directly supported by Mips. 316 setOperationAction(ISD::BR_CC, MVT::f32, Expand); 317 setOperationAction(ISD::BR_CC, MVT::f64, Expand); 318 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 319 setOperationAction(ISD::BR_CC, MVT::i64, Expand); 320 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 321 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 322 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 323 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 324 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 325 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 326 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 327 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 328 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 329 setOperationAction(ISD::CTTZ, MVT::i64, Expand); 330 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 331 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 332 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 333 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 334 setOperationAction(ISD::ROTL, MVT::i32, Expand); 335 setOperationAction(ISD::ROTL, MVT::i64, Expand); 336 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 337 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 338 339 if (!Subtarget->hasMips32r2()) 340 setOperationAction(ISD::ROTR, MVT::i32, Expand); 341 342 if (!Subtarget->hasMips64r2()) 343 setOperationAction(ISD::ROTR, MVT::i64, Expand); 344 345 setOperationAction(ISD::FSIN, MVT::f32, Expand); 346 setOperationAction(ISD::FSIN, MVT::f64, Expand); 347 setOperationAction(ISD::FCOS, MVT::f32, Expand); 348 setOperationAction(ISD::FCOS, MVT::f64, Expand); 349 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 350 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 351 setOperationAction(ISD::FPOWI, MVT::f32, Expand); 352 setOperationAction(ISD::FPOW, MVT::f32, Expand); 353 setOperationAction(ISD::FPOW, MVT::f64, Expand); 354 setOperationAction(ISD::FLOG, MVT::f32, Expand); 355 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 356 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 357 setOperationAction(ISD::FEXP, MVT::f32, Expand); 358 setOperationAction(ISD::FMA, MVT::f32, Expand); 359 setOperationAction(ISD::FMA, MVT::f64, Expand); 360 setOperationAction(ISD::FREM, MVT::f32, Expand); 361 setOperationAction(ISD::FREM, MVT::f64, Expand); 362 363 if (!TM.Options.NoNaNsFPMath) { 364 setOperationAction(ISD::FNEG, MVT::f32, Expand); 365 setOperationAction(ISD::FNEG, MVT::f64, Expand); 366 } 367 368 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); 369 370 setOperationAction(ISD::VAARG, MVT::Other, Expand); 371 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 372 setOperationAction(ISD::VAEND, MVT::Other, Expand); 373 374 // Use the default for now 375 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 376 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 377 378 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); 379 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); 380 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); 381 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); 382 383 setInsertFencesForAtomic(true); 384 385 if (!Subtarget->hasSEInReg()) { 386 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 387 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 388 } 389 390 if (!Subtarget->hasBitCount()) { 391 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 392 setOperationAction(ISD::CTLZ, MVT::i64, Expand); 393 } 394 395 if (!Subtarget->hasSwap()) { 396 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 397 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 398 } 399 400 if (HasMips64) { 401 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom); 402 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom); 403 setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom); 404 setTruncStoreAction(MVT::i64, MVT::i32, Custom); 405 } 406 407 setOperationAction(ISD::TRAP, MVT::Other, Legal); 408 409 setTargetDAGCombine(ISD::SDIVREM); 410 setTargetDAGCombine(ISD::UDIVREM); 411 setTargetDAGCombine(ISD::SELECT); 412 setTargetDAGCombine(ISD::AND); 413 setTargetDAGCombine(ISD::OR); 414 setTargetDAGCombine(ISD::ADD); 415 416 setMinFunctionAlignment(HasMips64 ? 3 : 2); 417 418 setStackPointerRegisterToSaveRestore(IsN64 ? Mips::SP_64 : Mips::SP); 419 420 setExceptionPointerRegister(IsN64 ? Mips::A0_64 : Mips::A0); 421 setExceptionSelectorRegister(IsN64 ? Mips::A1_64 : Mips::A1); 422 423 MaxStoresPerMemcpy = 16; 424} 425 426const MipsTargetLowering *MipsTargetLowering::create(MipsTargetMachine &TM) { 427 if (TM.getSubtargetImpl()->inMips16Mode()) 428 return llvm::createMips16TargetLowering(TM); 429 430 return llvm::createMipsSETargetLowering(TM); 431} 432 433EVT MipsTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const { 434 if (!VT.isVector()) 435 return MVT::i32; 436 return VT.changeVectorElementTypeToInteger(); 437} 438 439static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG, 440 TargetLowering::DAGCombinerInfo &DCI, 441 const MipsSubtarget *Subtarget) { 442 if (DCI.isBeforeLegalizeOps()) 443 return SDValue(); 444 445 EVT Ty = N->getValueType(0); 446 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64; 447 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64; 448 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 : 449 MipsISD::DivRemU16; 450 SDLoc DL(N); 451 452 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue, 453 N->getOperand(0), N->getOperand(1)); 454 SDValue InChain = DAG.getEntryNode(); 455 SDValue InGlue = DivRem; 456 457 // insert MFLO 458 if (N->hasAnyUseOfValue(0)) { 459 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty, 460 InGlue); 461 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 462 InChain = CopyFromLo.getValue(1); 463 InGlue = CopyFromLo.getValue(2); 464 } 465 466 // insert MFHI 467 if (N->hasAnyUseOfValue(1)) { 468 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL, 469 HI, Ty, InGlue); 470 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 471 } 472 473 return SDValue(); 474} 475 476static Mips::CondCode condCodeToFCC(ISD::CondCode CC) { 477 switch (CC) { 478 default: llvm_unreachable("Unknown fp condition code!"); 479 case ISD::SETEQ: 480 case ISD::SETOEQ: return Mips::FCOND_OEQ; 481 case ISD::SETUNE: return Mips::FCOND_UNE; 482 case ISD::SETLT: 483 case ISD::SETOLT: return Mips::FCOND_OLT; 484 case ISD::SETGT: 485 case ISD::SETOGT: return Mips::FCOND_OGT; 486 case ISD::SETLE: 487 case ISD::SETOLE: return Mips::FCOND_OLE; 488 case ISD::SETGE: 489 case ISD::SETOGE: return Mips::FCOND_OGE; 490 case ISD::SETULT: return Mips::FCOND_ULT; 491 case ISD::SETULE: return Mips::FCOND_ULE; 492 case ISD::SETUGT: return Mips::FCOND_UGT; 493 case ISD::SETUGE: return Mips::FCOND_UGE; 494 case ISD::SETUO: return Mips::FCOND_UN; 495 case ISD::SETO: return Mips::FCOND_OR; 496 case ISD::SETNE: 497 case ISD::SETONE: return Mips::FCOND_ONE; 498 case ISD::SETUEQ: return Mips::FCOND_UEQ; 499 } 500} 501 502 503/// This function returns true if the floating point conditional branches and 504/// conditional moves which use condition code CC should be inverted. 505static bool invertFPCondCodeUser(Mips::CondCode CC) { 506 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 507 return false; 508 509 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 510 "Illegal Condition Code"); 511 512 return true; 513} 514 515// Creates and returns an FPCmp node from a setcc node. 516// Returns Op if setcc is not a floating point comparison. 517static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) { 518 // must be a SETCC node 519 if (Op.getOpcode() != ISD::SETCC) 520 return Op; 521 522 SDValue LHS = Op.getOperand(0); 523 524 if (!LHS.getValueType().isFloatingPoint()) 525 return Op; 526 527 SDValue RHS = Op.getOperand(1); 528 SDLoc DL(Op); 529 530 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 531 // node if necessary. 532 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 533 534 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS, 535 DAG.getConstant(condCodeToFCC(CC), MVT::i32)); 536} 537 538// Creates and returns a CMovFPT/F node. 539static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, 540 SDValue False, SDLoc DL) { 541 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2)); 542 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue()); 543 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 544 545 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 546 True.getValueType(), True, FCC0, False, Cond); 547} 548 549static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, 550 TargetLowering::DAGCombinerInfo &DCI, 551 const MipsSubtarget *Subtarget) { 552 if (DCI.isBeforeLegalizeOps()) 553 return SDValue(); 554 555 SDValue SetCC = N->getOperand(0); 556 557 if ((SetCC.getOpcode() != ISD::SETCC) || 558 !SetCC.getOperand(0).getValueType().isInteger()) 559 return SDValue(); 560 561 SDValue False = N->getOperand(2); 562 EVT FalseTy = False.getValueType(); 563 564 if (!FalseTy.isInteger()) 565 return SDValue(); 566 567 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(False); 568 569 if (!CN || CN->getZExtValue()) 570 return SDValue(); 571 572 const SDLoc DL(N); 573 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 574 SDValue True = N->getOperand(1); 575 576 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 577 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 578 579 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); 580} 581 582static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, 583 TargetLowering::DAGCombinerInfo &DCI, 584 const MipsSubtarget *Subtarget) { 585 // Pattern match EXT. 586 // $dst = and ((sra or srl) $src , pos), (2**size - 1) 587 // => ext $dst, $src, size, pos 588 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2()) 589 return SDValue(); 590 591 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1); 592 unsigned ShiftRightOpc = ShiftRight.getOpcode(); 593 594 // Op's first operand must be a shift right. 595 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL) 596 return SDValue(); 597 598 // The second operand of the shift must be an immediate. 599 ConstantSDNode *CN; 600 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1)))) 601 return SDValue(); 602 603 uint64_t Pos = CN->getZExtValue(); 604 uint64_t SMPos, SMSize; 605 606 // Op's second operand must be a shifted mask. 607 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) || 608 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 609 return SDValue(); 610 611 // Return if the shifted mask does not start at bit 0 or the sum of its size 612 // and Pos exceeds the word's size. 613 EVT ValTy = N->getValueType(0); 614 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits()) 615 return SDValue(); 616 617 return DAG.getNode(MipsISD::Ext, SDLoc(N), ValTy, 618 ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32), 619 DAG.getConstant(SMSize, MVT::i32)); 620} 621 622static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, 623 TargetLowering::DAGCombinerInfo &DCI, 624 const MipsSubtarget *Subtarget) { 625 // Pattern match INS. 626 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), 627 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 628 // => ins $dst, $src, size, pos, $src1 629 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2()) 630 return SDValue(); 631 632 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); 633 uint64_t SMPos0, SMSize0, SMPos1, SMSize1; 634 ConstantSDNode *CN; 635 636 // See if Op's first operand matches (and $src1 , mask0). 637 if (And0.getOpcode() != ISD::AND) 638 return SDValue(); 639 640 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) || 641 !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0)) 642 return SDValue(); 643 644 // See if Op's second operand matches (and (shl $src, pos), mask1). 645 if (And1.getOpcode() != ISD::AND) 646 return SDValue(); 647 648 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || 649 !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1)) 650 return SDValue(); 651 652 // The shift masks must have the same position and size. 653 if (SMPos0 != SMPos1 || SMSize0 != SMSize1) 654 return SDValue(); 655 656 SDValue Shl = And1.getOperand(0); 657 if (Shl.getOpcode() != ISD::SHL) 658 return SDValue(); 659 660 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1)))) 661 return SDValue(); 662 663 unsigned Shamt = CN->getZExtValue(); 664 665 // Return if the shift amount and the first bit position of mask are not the 666 // same. 667 EVT ValTy = N->getValueType(0); 668 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits())) 669 return SDValue(); 670 671 return DAG.getNode(MipsISD::Ins, SDLoc(N), ValTy, Shl.getOperand(0), 672 DAG.getConstant(SMPos0, MVT::i32), 673 DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0)); 674} 675 676static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG, 677 TargetLowering::DAGCombinerInfo &DCI, 678 const MipsSubtarget *Subtarget) { 679 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) 680 681 if (DCI.isBeforeLegalizeOps()) 682 return SDValue(); 683 684 SDValue Add = N->getOperand(1); 685 686 if (Add.getOpcode() != ISD::ADD) 687 return SDValue(); 688 689 SDValue Lo = Add.getOperand(1); 690 691 if ((Lo.getOpcode() != MipsISD::Lo) || 692 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable)) 693 return SDValue(); 694 695 EVT ValTy = N->getValueType(0); 696 SDLoc DL(N); 697 698 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0), 699 Add.getOperand(0)); 700 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo); 701} 702 703SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 704 const { 705 SelectionDAG &DAG = DCI.DAG; 706 unsigned Opc = N->getOpcode(); 707 708 switch (Opc) { 709 default: break; 710 case ISD::SDIVREM: 711 case ISD::UDIVREM: 712 return performDivRemCombine(N, DAG, DCI, Subtarget); 713 case ISD::SELECT: 714 return performSELECTCombine(N, DAG, DCI, Subtarget); 715 case ISD::AND: 716 return performANDCombine(N, DAG, DCI, Subtarget); 717 case ISD::OR: 718 return performORCombine(N, DAG, DCI, Subtarget); 719 case ISD::ADD: 720 return performADDCombine(N, DAG, DCI, Subtarget); 721 } 722 723 return SDValue(); 724} 725 726void 727MipsTargetLowering::LowerOperationWrapper(SDNode *N, 728 SmallVectorImpl<SDValue> &Results, 729 SelectionDAG &DAG) const { 730 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 731 732 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I) 733 Results.push_back(Res.getValue(I)); 734} 735 736void 737MipsTargetLowering::ReplaceNodeResults(SDNode *N, 738 SmallVectorImpl<SDValue> &Results, 739 SelectionDAG &DAG) const { 740 return LowerOperationWrapper(N, Results, DAG); 741} 742 743SDValue MipsTargetLowering:: 744LowerOperation(SDValue Op, SelectionDAG &DAG) const 745{ 746 switch (Op.getOpcode()) 747 { 748 case ISD::BR_JT: return lowerBR_JT(Op, DAG); 749 case ISD::BRCOND: return lowerBRCOND(Op, DAG); 750 case ISD::ConstantPool: return lowerConstantPool(Op, DAG); 751 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG); 752 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG); 753 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG); 754 case ISD::JumpTable: return lowerJumpTable(Op, DAG); 755 case ISD::SELECT: return lowerSELECT(Op, DAG); 756 case ISD::SELECT_CC: return lowerSELECT_CC(Op, DAG); 757 case ISD::SETCC: return lowerSETCC(Op, DAG); 758 case ISD::VASTART: return lowerVASTART(Op, DAG); 759 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG); 760 case ISD::FABS: return lowerFABS(Op, DAG); 761 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG); 762 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG); 763 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG); 764 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG); 765 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG); 766 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true); 767 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false); 768 case ISD::LOAD: return lowerLOAD(Op, DAG); 769 case ISD::STORE: return lowerSTORE(Op, DAG); 770 case ISD::ADD: return lowerADD(Op, DAG); 771 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG); 772 } 773 return SDValue(); 774} 775 776//===----------------------------------------------------------------------===// 777// Lower helper functions 778//===----------------------------------------------------------------------===// 779 780// addLiveIn - This helper function adds the specified physical register to the 781// MachineFunction as a live in value. It also creates a corresponding 782// virtual register for it. 783static unsigned 784addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) 785{ 786 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 787 MF.getRegInfo().addLiveIn(PReg, VReg); 788 return VReg; 789} 790 791static MachineBasicBlock *expandPseudoDIV(MachineInstr *MI, 792 MachineBasicBlock &MBB, 793 const TargetInstrInfo &TII, 794 bool Is64Bit) { 795 if (NoZeroDivCheck) 796 return &MBB; 797 798 // Insert instruction "teq $divisor_reg, $zero, 7". 799 MachineBasicBlock::iterator I(MI); 800 MachineInstrBuilder MIB; 801 MIB = BuildMI(MBB, llvm::next(I), MI->getDebugLoc(), TII.get(Mips::TEQ)) 802 .addOperand(MI->getOperand(2)).addReg(Mips::ZERO).addImm(7); 803 804 // Use the 32-bit sub-register if this is a 64-bit division. 805 if (Is64Bit) 806 MIB->getOperand(0).setSubReg(Mips::sub_32); 807 808 return &MBB; 809} 810 811MachineBasicBlock * 812MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 813 MachineBasicBlock *BB) const { 814 switch (MI->getOpcode()) { 815 default: 816 llvm_unreachable("Unexpected instr type to insert"); 817 case Mips::ATOMIC_LOAD_ADD_I8: 818 return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu); 819 case Mips::ATOMIC_LOAD_ADD_I16: 820 return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu); 821 case Mips::ATOMIC_LOAD_ADD_I32: 822 return emitAtomicBinary(MI, BB, 4, Mips::ADDu); 823 case Mips::ATOMIC_LOAD_ADD_I64: 824 return emitAtomicBinary(MI, BB, 8, Mips::DADDu); 825 826 case Mips::ATOMIC_LOAD_AND_I8: 827 return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND); 828 case Mips::ATOMIC_LOAD_AND_I16: 829 return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND); 830 case Mips::ATOMIC_LOAD_AND_I32: 831 return emitAtomicBinary(MI, BB, 4, Mips::AND); 832 case Mips::ATOMIC_LOAD_AND_I64: 833 return emitAtomicBinary(MI, BB, 8, Mips::AND64); 834 835 case Mips::ATOMIC_LOAD_OR_I8: 836 return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR); 837 case Mips::ATOMIC_LOAD_OR_I16: 838 return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR); 839 case Mips::ATOMIC_LOAD_OR_I32: 840 return emitAtomicBinary(MI, BB, 4, Mips::OR); 841 case Mips::ATOMIC_LOAD_OR_I64: 842 return emitAtomicBinary(MI, BB, 8, Mips::OR64); 843 844 case Mips::ATOMIC_LOAD_XOR_I8: 845 return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR); 846 case Mips::ATOMIC_LOAD_XOR_I16: 847 return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR); 848 case Mips::ATOMIC_LOAD_XOR_I32: 849 return emitAtomicBinary(MI, BB, 4, Mips::XOR); 850 case Mips::ATOMIC_LOAD_XOR_I64: 851 return emitAtomicBinary(MI, BB, 8, Mips::XOR64); 852 853 case Mips::ATOMIC_LOAD_NAND_I8: 854 return emitAtomicBinaryPartword(MI, BB, 1, 0, true); 855 case Mips::ATOMIC_LOAD_NAND_I16: 856 return emitAtomicBinaryPartword(MI, BB, 2, 0, true); 857 case Mips::ATOMIC_LOAD_NAND_I32: 858 return emitAtomicBinary(MI, BB, 4, 0, true); 859 case Mips::ATOMIC_LOAD_NAND_I64: 860 return emitAtomicBinary(MI, BB, 8, 0, true); 861 862 case Mips::ATOMIC_LOAD_SUB_I8: 863 return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu); 864 case Mips::ATOMIC_LOAD_SUB_I16: 865 return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu); 866 case Mips::ATOMIC_LOAD_SUB_I32: 867 return emitAtomicBinary(MI, BB, 4, Mips::SUBu); 868 case Mips::ATOMIC_LOAD_SUB_I64: 869 return emitAtomicBinary(MI, BB, 8, Mips::DSUBu); 870 871 case Mips::ATOMIC_SWAP_I8: 872 return emitAtomicBinaryPartword(MI, BB, 1, 0); 873 case Mips::ATOMIC_SWAP_I16: 874 return emitAtomicBinaryPartword(MI, BB, 2, 0); 875 case Mips::ATOMIC_SWAP_I32: 876 return emitAtomicBinary(MI, BB, 4, 0); 877 case Mips::ATOMIC_SWAP_I64: 878 return emitAtomicBinary(MI, BB, 8, 0); 879 880 case Mips::ATOMIC_CMP_SWAP_I8: 881 return emitAtomicCmpSwapPartword(MI, BB, 1); 882 case Mips::ATOMIC_CMP_SWAP_I16: 883 return emitAtomicCmpSwapPartword(MI, BB, 2); 884 case Mips::ATOMIC_CMP_SWAP_I32: 885 return emitAtomicCmpSwap(MI, BB, 4); 886 case Mips::ATOMIC_CMP_SWAP_I64: 887 return emitAtomicCmpSwap(MI, BB, 8); 888 case Mips::PseudoSDIV: 889 case Mips::PseudoUDIV: 890 return expandPseudoDIV(MI, *BB, *getTargetMachine().getInstrInfo(), false); 891 case Mips::PseudoDSDIV: 892 case Mips::PseudoDUDIV: 893 return expandPseudoDIV(MI, *BB, *getTargetMachine().getInstrInfo(), true); 894 } 895} 896 897// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 898// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 899MachineBasicBlock * 900MipsTargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 901 unsigned Size, unsigned BinOpcode, 902 bool Nand) const { 903 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary."); 904 905 MachineFunction *MF = BB->getParent(); 906 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 907 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 908 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 909 DebugLoc DL = MI->getDebugLoc(); 910 unsigned LL, SC, AND, NOR, ZERO, BEQ; 911 912 if (Size == 4) { 913 LL = Mips::LL; 914 SC = Mips::SC; 915 AND = Mips::AND; 916 NOR = Mips::NOR; 917 ZERO = Mips::ZERO; 918 BEQ = Mips::BEQ; 919 } 920 else { 921 LL = Mips::LLD; 922 SC = Mips::SCD; 923 AND = Mips::AND64; 924 NOR = Mips::NOR64; 925 ZERO = Mips::ZERO_64; 926 BEQ = Mips::BEQ64; 927 } 928 929 unsigned OldVal = MI->getOperand(0).getReg(); 930 unsigned Ptr = MI->getOperand(1).getReg(); 931 unsigned Incr = MI->getOperand(2).getReg(); 932 933 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 934 unsigned AndRes = RegInfo.createVirtualRegister(RC); 935 unsigned Success = RegInfo.createVirtualRegister(RC); 936 937 // insert new blocks after the current block 938 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 939 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 940 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 941 MachineFunction::iterator It = BB; 942 ++It; 943 MF->insert(It, loopMBB); 944 MF->insert(It, exitMBB); 945 946 // Transfer the remainder of BB and its successor edges to exitMBB. 947 exitMBB->splice(exitMBB->begin(), BB, 948 llvm::next(MachineBasicBlock::iterator(MI)), 949 BB->end()); 950 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 951 952 // thisMBB: 953 // ... 954 // fallthrough --> loopMBB 955 BB->addSuccessor(loopMBB); 956 loopMBB->addSuccessor(loopMBB); 957 loopMBB->addSuccessor(exitMBB); 958 959 // loopMBB: 960 // ll oldval, 0(ptr) 961 // <binop> storeval, oldval, incr 962 // sc success, storeval, 0(ptr) 963 // beq success, $0, loopMBB 964 BB = loopMBB; 965 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0); 966 if (Nand) { 967 // and andres, oldval, incr 968 // nor storeval, $0, andres 969 BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr); 970 BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes); 971 } else if (BinOpcode) { 972 // <binop> storeval, oldval, incr 973 BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr); 974 } else { 975 StoreVal = Incr; 976 } 977 BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0); 978 BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB); 979 980 MI->eraseFromParent(); // The instruction is gone now. 981 982 return exitMBB; 983} 984 985MachineBasicBlock * 986MipsTargetLowering::emitAtomicBinaryPartword(MachineInstr *MI, 987 MachineBasicBlock *BB, 988 unsigned Size, unsigned BinOpcode, 989 bool Nand) const { 990 assert((Size == 1 || Size == 2) && 991 "Unsupported size for EmitAtomicBinaryPartial."); 992 993 MachineFunction *MF = BB->getParent(); 994 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 995 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 996 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 997 DebugLoc DL = MI->getDebugLoc(); 998 999 unsigned Dest = MI->getOperand(0).getReg(); 1000 unsigned Ptr = MI->getOperand(1).getReg(); 1001 unsigned Incr = MI->getOperand(2).getReg(); 1002 1003 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 1004 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1005 unsigned Mask = RegInfo.createVirtualRegister(RC); 1006 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1007 unsigned NewVal = RegInfo.createVirtualRegister(RC); 1008 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1009 unsigned Incr2 = RegInfo.createVirtualRegister(RC); 1010 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 1011 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1012 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1013 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1014 unsigned BinOpRes = RegInfo.createVirtualRegister(RC); 1015 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1016 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1017 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1018 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1019 unsigned SllRes = RegInfo.createVirtualRegister(RC); 1020 unsigned Success = RegInfo.createVirtualRegister(RC); 1021 1022 // insert new blocks after the current block 1023 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1024 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1025 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1026 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1027 MachineFunction::iterator It = BB; 1028 ++It; 1029 MF->insert(It, loopMBB); 1030 MF->insert(It, sinkMBB); 1031 MF->insert(It, exitMBB); 1032 1033 // Transfer the remainder of BB and its successor edges to exitMBB. 1034 exitMBB->splice(exitMBB->begin(), BB, 1035 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1036 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1037 1038 BB->addSuccessor(loopMBB); 1039 loopMBB->addSuccessor(loopMBB); 1040 loopMBB->addSuccessor(sinkMBB); 1041 sinkMBB->addSuccessor(exitMBB); 1042 1043 // thisMBB: 1044 // addiu masklsb2,$0,-4 # 0xfffffffc 1045 // and alignedaddr,ptr,masklsb2 1046 // andi ptrlsb2,ptr,3 1047 // sll shiftamt,ptrlsb2,3 1048 // ori maskupper,$0,255 # 0xff 1049 // sll mask,maskupper,shiftamt 1050 // nor mask2,$0,mask 1051 // sll incr2,incr,shiftamt 1052 1053 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1054 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2) 1055 .addReg(Mips::ZERO).addImm(-4); 1056 BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr) 1057 .addReg(Ptr).addReg(MaskLSB2); 1058 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1059 if (Subtarget->isLittle()) { 1060 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1061 } else { 1062 unsigned Off = RegInfo.createVirtualRegister(RC); 1063 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1064 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1065 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1066 } 1067 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1068 .addReg(Mips::ZERO).addImm(MaskImm); 1069 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1070 .addReg(MaskUpper).addReg(ShiftAmt); 1071 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1072 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt); 1073 1074 // atomic.load.binop 1075 // loopMBB: 1076 // ll oldval,0(alignedaddr) 1077 // binop binopres,oldval,incr2 1078 // and newval,binopres,mask 1079 // and maskedoldval0,oldval,mask2 1080 // or storeval,maskedoldval0,newval 1081 // sc success,storeval,0(alignedaddr) 1082 // beq success,$0,loopMBB 1083 1084 // atomic.swap 1085 // loopMBB: 1086 // ll oldval,0(alignedaddr) 1087 // and newval,incr2,mask 1088 // and maskedoldval0,oldval,mask2 1089 // or storeval,maskedoldval0,newval 1090 // sc success,storeval,0(alignedaddr) 1091 // beq success,$0,loopMBB 1092 1093 BB = loopMBB; 1094 BuildMI(BB, DL, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0); 1095 if (Nand) { 1096 // and andres, oldval, incr2 1097 // nor binopres, $0, andres 1098 // and newval, binopres, mask 1099 BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2); 1100 BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes) 1101 .addReg(Mips::ZERO).addReg(AndRes); 1102 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1103 } else if (BinOpcode) { 1104 // <binop> binopres, oldval, incr2 1105 // and newval, binopres, mask 1106 BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2); 1107 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1108 } else {// atomic.swap 1109 // and newval, incr2, mask 1110 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask); 1111 } 1112 1113 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0) 1114 .addReg(OldVal).addReg(Mask2); 1115 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal) 1116 .addReg(MaskedOldVal0).addReg(NewVal); 1117 BuildMI(BB, DL, TII->get(Mips::SC), Success) 1118 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1119 BuildMI(BB, DL, TII->get(Mips::BEQ)) 1120 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB); 1121 1122 // sinkMBB: 1123 // and maskedoldval1,oldval,mask 1124 // srl srlres,maskedoldval1,shiftamt 1125 // sll sllres,srlres,24 1126 // sra dest,sllres,24 1127 BB = sinkMBB; 1128 int64_t ShiftImm = (Size == 1) ? 24 : 16; 1129 1130 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1) 1131 .addReg(OldVal).addReg(Mask); 1132 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes) 1133 .addReg(MaskedOldVal1).addReg(ShiftAmt); 1134 BuildMI(BB, DL, TII->get(Mips::SLL), SllRes) 1135 .addReg(SrlRes).addImm(ShiftImm); 1136 BuildMI(BB, DL, TII->get(Mips::SRA), Dest) 1137 .addReg(SllRes).addImm(ShiftImm); 1138 1139 MI->eraseFromParent(); // The instruction is gone now. 1140 1141 return exitMBB; 1142} 1143 1144MachineBasicBlock * 1145MipsTargetLowering::emitAtomicCmpSwap(MachineInstr *MI, 1146 MachineBasicBlock *BB, 1147 unsigned Size) const { 1148 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap."); 1149 1150 MachineFunction *MF = BB->getParent(); 1151 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1152 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1153 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1154 DebugLoc DL = MI->getDebugLoc(); 1155 unsigned LL, SC, ZERO, BNE, BEQ; 1156 1157 if (Size == 4) { 1158 LL = Mips::LL; 1159 SC = Mips::SC; 1160 ZERO = Mips::ZERO; 1161 BNE = Mips::BNE; 1162 BEQ = Mips::BEQ; 1163 } 1164 else { 1165 LL = Mips::LLD; 1166 SC = Mips::SCD; 1167 ZERO = Mips::ZERO_64; 1168 BNE = Mips::BNE64; 1169 BEQ = Mips::BEQ64; 1170 } 1171 1172 unsigned Dest = MI->getOperand(0).getReg(); 1173 unsigned Ptr = MI->getOperand(1).getReg(); 1174 unsigned OldVal = MI->getOperand(2).getReg(); 1175 unsigned NewVal = MI->getOperand(3).getReg(); 1176 1177 unsigned Success = RegInfo.createVirtualRegister(RC); 1178 1179 // insert new blocks after the current block 1180 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1181 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1182 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1183 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1184 MachineFunction::iterator It = BB; 1185 ++It; 1186 MF->insert(It, loop1MBB); 1187 MF->insert(It, loop2MBB); 1188 MF->insert(It, exitMBB); 1189 1190 // Transfer the remainder of BB and its successor edges to exitMBB. 1191 exitMBB->splice(exitMBB->begin(), BB, 1192 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1193 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1194 1195 // thisMBB: 1196 // ... 1197 // fallthrough --> loop1MBB 1198 BB->addSuccessor(loop1MBB); 1199 loop1MBB->addSuccessor(exitMBB); 1200 loop1MBB->addSuccessor(loop2MBB); 1201 loop2MBB->addSuccessor(loop1MBB); 1202 loop2MBB->addSuccessor(exitMBB); 1203 1204 // loop1MBB: 1205 // ll dest, 0(ptr) 1206 // bne dest, oldval, exitMBB 1207 BB = loop1MBB; 1208 BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0); 1209 BuildMI(BB, DL, TII->get(BNE)) 1210 .addReg(Dest).addReg(OldVal).addMBB(exitMBB); 1211 1212 // loop2MBB: 1213 // sc success, newval, 0(ptr) 1214 // beq success, $0, loop1MBB 1215 BB = loop2MBB; 1216 BuildMI(BB, DL, TII->get(SC), Success) 1217 .addReg(NewVal).addReg(Ptr).addImm(0); 1218 BuildMI(BB, DL, TII->get(BEQ)) 1219 .addReg(Success).addReg(ZERO).addMBB(loop1MBB); 1220 1221 MI->eraseFromParent(); // The instruction is gone now. 1222 1223 return exitMBB; 1224} 1225 1226MachineBasicBlock * 1227MipsTargetLowering::emitAtomicCmpSwapPartword(MachineInstr *MI, 1228 MachineBasicBlock *BB, 1229 unsigned Size) const { 1230 assert((Size == 1 || Size == 2) && 1231 "Unsupported size for EmitAtomicCmpSwapPartial."); 1232 1233 MachineFunction *MF = BB->getParent(); 1234 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1235 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1236 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1237 DebugLoc DL = MI->getDebugLoc(); 1238 1239 unsigned Dest = MI->getOperand(0).getReg(); 1240 unsigned Ptr = MI->getOperand(1).getReg(); 1241 unsigned CmpVal = MI->getOperand(2).getReg(); 1242 unsigned NewVal = MI->getOperand(3).getReg(); 1243 1244 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 1245 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1246 unsigned Mask = RegInfo.createVirtualRegister(RC); 1247 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1248 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC); 1249 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1250 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1251 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC); 1252 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 1253 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1254 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1255 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC); 1256 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC); 1257 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1258 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1259 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1260 unsigned SllRes = RegInfo.createVirtualRegister(RC); 1261 unsigned Success = RegInfo.createVirtualRegister(RC); 1262 1263 // insert new blocks after the current block 1264 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1265 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1266 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1267 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1268 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1269 MachineFunction::iterator It = BB; 1270 ++It; 1271 MF->insert(It, loop1MBB); 1272 MF->insert(It, loop2MBB); 1273 MF->insert(It, sinkMBB); 1274 MF->insert(It, exitMBB); 1275 1276 // Transfer the remainder of BB and its successor edges to exitMBB. 1277 exitMBB->splice(exitMBB->begin(), BB, 1278 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1279 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1280 1281 BB->addSuccessor(loop1MBB); 1282 loop1MBB->addSuccessor(sinkMBB); 1283 loop1MBB->addSuccessor(loop2MBB); 1284 loop2MBB->addSuccessor(loop1MBB); 1285 loop2MBB->addSuccessor(sinkMBB); 1286 sinkMBB->addSuccessor(exitMBB); 1287 1288 // FIXME: computation of newval2 can be moved to loop2MBB. 1289 // thisMBB: 1290 // addiu masklsb2,$0,-4 # 0xfffffffc 1291 // and alignedaddr,ptr,masklsb2 1292 // andi ptrlsb2,ptr,3 1293 // sll shiftamt,ptrlsb2,3 1294 // ori maskupper,$0,255 # 0xff 1295 // sll mask,maskupper,shiftamt 1296 // nor mask2,$0,mask 1297 // andi maskedcmpval,cmpval,255 1298 // sll shiftedcmpval,maskedcmpval,shiftamt 1299 // andi maskednewval,newval,255 1300 // sll shiftednewval,maskednewval,shiftamt 1301 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1302 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2) 1303 .addReg(Mips::ZERO).addImm(-4); 1304 BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr) 1305 .addReg(Ptr).addReg(MaskLSB2); 1306 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1307 if (Subtarget->isLittle()) { 1308 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1309 } else { 1310 unsigned Off = RegInfo.createVirtualRegister(RC); 1311 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1312 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1313 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1314 } 1315 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1316 .addReg(Mips::ZERO).addImm(MaskImm); 1317 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1318 .addReg(MaskUpper).addReg(ShiftAmt); 1319 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1320 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal) 1321 .addReg(CmpVal).addImm(MaskImm); 1322 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal) 1323 .addReg(MaskedCmpVal).addReg(ShiftAmt); 1324 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal) 1325 .addReg(NewVal).addImm(MaskImm); 1326 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal) 1327 .addReg(MaskedNewVal).addReg(ShiftAmt); 1328 1329 // loop1MBB: 1330 // ll oldval,0(alginedaddr) 1331 // and maskedoldval0,oldval,mask 1332 // bne maskedoldval0,shiftedcmpval,sinkMBB 1333 BB = loop1MBB; 1334 BuildMI(BB, DL, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0); 1335 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0) 1336 .addReg(OldVal).addReg(Mask); 1337 BuildMI(BB, DL, TII->get(Mips::BNE)) 1338 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB); 1339 1340 // loop2MBB: 1341 // and maskedoldval1,oldval,mask2 1342 // or storeval,maskedoldval1,shiftednewval 1343 // sc success,storeval,0(alignedaddr) 1344 // beq success,$0,loop1MBB 1345 BB = loop2MBB; 1346 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1) 1347 .addReg(OldVal).addReg(Mask2); 1348 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal) 1349 .addReg(MaskedOldVal1).addReg(ShiftedNewVal); 1350 BuildMI(BB, DL, TII->get(Mips::SC), Success) 1351 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1352 BuildMI(BB, DL, TII->get(Mips::BEQ)) 1353 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB); 1354 1355 // sinkMBB: 1356 // srl srlres,maskedoldval0,shiftamt 1357 // sll sllres,srlres,24 1358 // sra dest,sllres,24 1359 BB = sinkMBB; 1360 int64_t ShiftImm = (Size == 1) ? 24 : 16; 1361 1362 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes) 1363 .addReg(MaskedOldVal0).addReg(ShiftAmt); 1364 BuildMI(BB, DL, TII->get(Mips::SLL), SllRes) 1365 .addReg(SrlRes).addImm(ShiftImm); 1366 BuildMI(BB, DL, TII->get(Mips::SRA), Dest) 1367 .addReg(SllRes).addImm(ShiftImm); 1368 1369 MI->eraseFromParent(); // The instruction is gone now. 1370 1371 return exitMBB; 1372} 1373 1374//===----------------------------------------------------------------------===// 1375// Misc Lower Operation implementation 1376//===----------------------------------------------------------------------===// 1377SDValue MipsTargetLowering::lowerBR_JT(SDValue Op, SelectionDAG &DAG) const { 1378 SDValue Chain = Op.getOperand(0); 1379 SDValue Table = Op.getOperand(1); 1380 SDValue Index = Op.getOperand(2); 1381 SDLoc DL(Op); 1382 EVT PTy = getPointerTy(); 1383 unsigned EntrySize = 1384 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(*getDataLayout()); 1385 1386 Index = DAG.getNode(ISD::MUL, DL, PTy, Index, 1387 DAG.getConstant(EntrySize, PTy)); 1388 SDValue Addr = DAG.getNode(ISD::ADD, DL, PTy, Index, Table); 1389 1390 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8); 1391 Addr = DAG.getExtLoad(ISD::SEXTLOAD, DL, PTy, Chain, Addr, 1392 MachinePointerInfo::getJumpTable(), MemVT, false, false, 1393 0); 1394 Chain = Addr.getValue(1); 1395 1396 if ((getTargetMachine().getRelocationModel() == Reloc::PIC_) || IsN64) { 1397 // For PIC, the sequence is: 1398 // BRIND(load(Jumptable + index) + RelocBase) 1399 // RelocBase can be JumpTable, GOT or some sort of global base. 1400 Addr = DAG.getNode(ISD::ADD, DL, PTy, Addr, 1401 getPICJumpTableRelocBase(Table, DAG)); 1402 } 1403 1404 return DAG.getNode(ISD::BRIND, DL, MVT::Other, Chain, Addr); 1405} 1406 1407SDValue MipsTargetLowering:: 1408lowerBRCOND(SDValue Op, SelectionDAG &DAG) const 1409{ 1410 // The first operand is the chain, the second is the condition, the third is 1411 // the block to branch to if the condition is true. 1412 SDValue Chain = Op.getOperand(0); 1413 SDValue Dest = Op.getOperand(2); 1414 SDLoc DL(Op); 1415 1416 SDValue CondRes = createFPCmp(DAG, Op.getOperand(1)); 1417 1418 // Return if flag is not set by a floating point comparison. 1419 if (CondRes.getOpcode() != MipsISD::FPCmp) 1420 return Op; 1421 1422 SDValue CCNode = CondRes.getOperand(2); 1423 Mips::CondCode CC = 1424 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 1425 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T; 1426 SDValue BrCode = DAG.getConstant(Opc, MVT::i32); 1427 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 1428 return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode, 1429 FCC0, Dest, CondRes); 1430} 1431 1432SDValue MipsTargetLowering:: 1433lowerSELECT(SDValue Op, SelectionDAG &DAG) const 1434{ 1435 SDValue Cond = createFPCmp(DAG, Op.getOperand(0)); 1436 1437 // Return if flag is not set by a floating point comparison. 1438 if (Cond.getOpcode() != MipsISD::FPCmp) 1439 return Op; 1440 1441 return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 1442 SDLoc(Op)); 1443} 1444 1445SDValue MipsTargetLowering:: 1446lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const 1447{ 1448 SDLoc DL(Op); 1449 EVT Ty = Op.getOperand(0).getValueType(); 1450 SDValue Cond = DAG.getNode(ISD::SETCC, DL, 1451 getSetCCResultType(*DAG.getContext(), Ty), 1452 Op.getOperand(0), Op.getOperand(1), 1453 Op.getOperand(4)); 1454 1455 return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2), 1456 Op.getOperand(3)); 1457} 1458 1459SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const { 1460 SDValue Cond = createFPCmp(DAG, Op); 1461 1462 assert(Cond.getOpcode() == MipsISD::FPCmp && 1463 "Floating point operand expected."); 1464 1465 SDValue True = DAG.getConstant(1, MVT::i32); 1466 SDValue False = DAG.getConstant(0, MVT::i32); 1467 1468 return createCMovFP(DAG, Cond, True, False, SDLoc(Op)); 1469} 1470 1471SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op, 1472 SelectionDAG &DAG) const { 1473 // FIXME there isn't actually debug info here 1474 SDLoc DL(Op); 1475 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 1476 1477 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) { 1478 const MipsTargetObjectFile &TLOF = 1479 (const MipsTargetObjectFile&)getObjFileLowering(); 1480 1481 // %gp_rel relocation 1482 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) { 1483 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, 0, 1484 MipsII::MO_GPREL); 1485 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, DL, 1486 DAG.getVTList(MVT::i32), &GA, 1); 1487 SDValue GPReg = DAG.getRegister(Mips::GP, MVT::i32); 1488 return DAG.getNode(ISD::ADD, DL, MVT::i32, GPReg, GPRelNode); 1489 } 1490 1491 // %hi/%lo relocation 1492 return getAddrNonPIC(Op, DAG); 1493 } 1494 1495 if (GV->hasInternalLinkage() || (GV->hasLocalLinkage() && !isa<Function>(GV))) 1496 return getAddrLocal(Op, DAG, HasMips64); 1497 1498 if (LargeGOT) 1499 return getAddrGlobalLargeGOT(Op, DAG, MipsII::MO_GOT_HI16, 1500 MipsII::MO_GOT_LO16); 1501 1502 return getAddrGlobal(Op, DAG, 1503 HasMips64 ? MipsII::MO_GOT_DISP : MipsII::MO_GOT16); 1504} 1505 1506SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op, 1507 SelectionDAG &DAG) const { 1508 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) 1509 return getAddrNonPIC(Op, DAG); 1510 1511 return getAddrLocal(Op, DAG, HasMips64); 1512} 1513 1514SDValue MipsTargetLowering:: 1515lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 1516{ 1517 // If the relocation model is PIC, use the General Dynamic TLS Model or 1518 // Local Dynamic TLS model, otherwise use the Initial Exec or 1519 // Local Exec TLS Model. 1520 1521 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1522 SDLoc DL(GA); 1523 const GlobalValue *GV = GA->getGlobal(); 1524 EVT PtrVT = getPointerTy(); 1525 1526 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 1527 1528 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) { 1529 // General Dynamic and Local Dynamic TLS Model. 1530 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM 1531 : MipsII::MO_TLSGD; 1532 1533 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag); 1534 SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, 1535 getGlobalReg(DAG, PtrVT), TGA); 1536 unsigned PtrSize = PtrVT.getSizeInBits(); 1537 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize); 1538 1539 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT); 1540 1541 ArgListTy Args; 1542 ArgListEntry Entry; 1543 Entry.Node = Argument; 1544 Entry.Ty = PtrTy; 1545 Args.push_back(Entry); 1546 1547 TargetLowering::CallLoweringInfo CLI(DAG.getEntryNode(), PtrTy, 1548 false, false, false, false, 0, CallingConv::C, 1549 /*IsTailCall=*/false, /*doesNotRet=*/false, 1550 /*isReturnValueUsed=*/true, 1551 TlsGetAddr, Args, DAG, DL); 1552 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 1553 1554 SDValue Ret = CallResult.first; 1555 1556 if (model != TLSModel::LocalDynamic) 1557 return Ret; 1558 1559 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1560 MipsII::MO_DTPREL_HI); 1561 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi); 1562 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1563 MipsII::MO_DTPREL_LO); 1564 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 1565 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret); 1566 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo); 1567 } 1568 1569 SDValue Offset; 1570 if (model == TLSModel::InitialExec) { 1571 // Initial Exec TLS Model 1572 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1573 MipsII::MO_GOTTPREL); 1574 TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT), 1575 TGA); 1576 Offset = DAG.getLoad(PtrVT, DL, 1577 DAG.getEntryNode(), TGA, MachinePointerInfo(), 1578 false, false, false, 0); 1579 } else { 1580 // Local Exec TLS Model 1581 assert(model == TLSModel::LocalExec); 1582 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1583 MipsII::MO_TPREL_HI); 1584 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1585 MipsII::MO_TPREL_LO); 1586 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi); 1587 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 1588 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 1589 } 1590 1591 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT); 1592 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset); 1593} 1594 1595SDValue MipsTargetLowering:: 1596lowerJumpTable(SDValue Op, SelectionDAG &DAG) const 1597{ 1598 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) 1599 return getAddrNonPIC(Op, DAG); 1600 1601 return getAddrLocal(Op, DAG, HasMips64); 1602} 1603 1604SDValue MipsTargetLowering:: 1605lowerConstantPool(SDValue Op, SelectionDAG &DAG) const 1606{ 1607 // gp_rel relocation 1608 // FIXME: we should reference the constant pool using small data sections, 1609 // but the asm printer currently doesn't support this feature without 1610 // hacking it. This feature should come soon so we can uncomment the 1611 // stuff below. 1612 //if (IsInSmallSection(C->getType())) { 1613 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP); 1614 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); 1615 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode); 1616 1617 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) 1618 return getAddrNonPIC(Op, DAG); 1619 1620 return getAddrLocal(Op, DAG, HasMips64); 1621} 1622 1623SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const { 1624 MachineFunction &MF = DAG.getMachineFunction(); 1625 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 1626 1627 SDLoc DL(Op); 1628 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1629 getPointerTy()); 1630 1631 // vastart just stores the address of the VarArgsFrameIndex slot into the 1632 // memory location argument. 1633 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1634 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1), 1635 MachinePointerInfo(SV), false, false, 0); 1636} 1637 1638static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasR2) { 1639 EVT TyX = Op.getOperand(0).getValueType(); 1640 EVT TyY = Op.getOperand(1).getValueType(); 1641 SDValue Const1 = DAG.getConstant(1, MVT::i32); 1642 SDValue Const31 = DAG.getConstant(31, MVT::i32); 1643 SDLoc DL(Op); 1644 SDValue Res; 1645 1646 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 1647 // to i32. 1648 SDValue X = (TyX == MVT::f32) ? 1649 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 1650 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 1651 Const1); 1652 SDValue Y = (TyY == MVT::f32) ? 1653 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) : 1654 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1), 1655 Const1); 1656 1657 if (HasR2) { 1658 // ext E, Y, 31, 1 ; extract bit31 of Y 1659 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X 1660 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1); 1661 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X); 1662 } else { 1663 // sll SllX, X, 1 1664 // srl SrlX, SllX, 1 1665 // srl SrlY, Y, 31 1666 // sll SllY, SrlX, 31 1667 // or Or, SrlX, SllY 1668 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 1669 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 1670 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); 1671 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31); 1672 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY); 1673 } 1674 1675 if (TyX == MVT::f32) 1676 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res); 1677 1678 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 1679 Op.getOperand(0), DAG.getConstant(0, MVT::i32)); 1680 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 1681} 1682 1683static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasR2) { 1684 unsigned WidthX = Op.getOperand(0).getValueSizeInBits(); 1685 unsigned WidthY = Op.getOperand(1).getValueSizeInBits(); 1686 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY); 1687 SDValue Const1 = DAG.getConstant(1, MVT::i32); 1688 SDLoc DL(Op); 1689 1690 // Bitcast to integer nodes. 1691 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0)); 1692 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1)); 1693 1694 if (HasR2) { 1695 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y 1696 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X 1697 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y, 1698 DAG.getConstant(WidthY - 1, MVT::i32), Const1); 1699 1700 if (WidthX > WidthY) 1701 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E); 1702 else if (WidthY > WidthX) 1703 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E); 1704 1705 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E, 1706 DAG.getConstant(WidthX - 1, MVT::i32), Const1, X); 1707 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I); 1708 } 1709 1710 // (d)sll SllX, X, 1 1711 // (d)srl SrlX, SllX, 1 1712 // (d)srl SrlY, Y, width(Y)-1 1713 // (d)sll SllY, SrlX, width(Y)-1 1714 // or Or, SrlX, SllY 1715 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1); 1716 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); 1717 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, 1718 DAG.getConstant(WidthY - 1, MVT::i32)); 1719 1720 if (WidthX > WidthY) 1721 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY); 1722 else if (WidthY > WidthX) 1723 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY); 1724 1725 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY, 1726 DAG.getConstant(WidthX - 1, MVT::i32)); 1727 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY); 1728 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or); 1729} 1730 1731SDValue 1732MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 1733 if (Subtarget->hasMips64()) 1734 return lowerFCOPYSIGN64(Op, DAG, Subtarget->hasMips32r2()); 1735 1736 return lowerFCOPYSIGN32(Op, DAG, Subtarget->hasMips32r2()); 1737} 1738 1739static SDValue lowerFABS32(SDValue Op, SelectionDAG &DAG, bool HasR2) { 1740 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32); 1741 SDLoc DL(Op); 1742 1743 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 1744 // to i32. 1745 SDValue X = (Op.getValueType() == MVT::f32) ? 1746 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 1747 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 1748 Const1); 1749 1750 // Clear MSB. 1751 if (HasR2) 1752 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, 1753 DAG.getRegister(Mips::ZERO, MVT::i32), 1754 DAG.getConstant(31, MVT::i32), Const1, X); 1755 else { 1756 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 1757 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 1758 } 1759 1760 if (Op.getValueType() == MVT::f32) 1761 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res); 1762 1763 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 1764 Op.getOperand(0), DAG.getConstant(0, MVT::i32)); 1765 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 1766} 1767 1768static SDValue lowerFABS64(SDValue Op, SelectionDAG &DAG, bool HasR2) { 1769 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32); 1770 SDLoc DL(Op); 1771 1772 // Bitcast to integer node. 1773 SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0)); 1774 1775 // Clear MSB. 1776 if (HasR2) 1777 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64, 1778 DAG.getRegister(Mips::ZERO_64, MVT::i64), 1779 DAG.getConstant(63, MVT::i32), Const1, X); 1780 else { 1781 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1); 1782 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1); 1783 } 1784 1785 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res); 1786} 1787 1788SDValue 1789MipsTargetLowering::lowerFABS(SDValue Op, SelectionDAG &DAG) const { 1790 if (Subtarget->hasMips64() && (Op.getValueType() == MVT::f64)) 1791 return lowerFABS64(Op, DAG, Subtarget->hasMips32r2()); 1792 1793 return lowerFABS32(Op, DAG, Subtarget->hasMips32r2()); 1794} 1795 1796SDValue MipsTargetLowering:: 1797lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 1798 // check the depth 1799 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 1800 "Frame address can only be determined for current frame."); 1801 1802 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1803 MFI->setFrameAddressIsTaken(true); 1804 EVT VT = Op.getValueType(); 1805 SDLoc DL(Op); 1806 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL, 1807 IsN64 ? Mips::FP_64 : Mips::FP, VT); 1808 return FrameAddr; 1809} 1810 1811SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op, 1812 SelectionDAG &DAG) const { 1813 // check the depth 1814 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 1815 "Return address can be determined only for current frame."); 1816 1817 MachineFunction &MF = DAG.getMachineFunction(); 1818 MachineFrameInfo *MFI = MF.getFrameInfo(); 1819 MVT VT = Op.getSimpleValueType(); 1820 unsigned RA = IsN64 ? Mips::RA_64 : Mips::RA; 1821 MFI->setReturnAddressIsTaken(true); 1822 1823 // Return RA, which contains the return address. Mark it an implicit live-in. 1824 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); 1825 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT); 1826} 1827 1828// An EH_RETURN is the result of lowering llvm.eh.return which in turn is 1829// generated from __builtin_eh_return (offset, handler) 1830// The effect of this is to adjust the stack pointer by "offset" 1831// and then branch to "handler". 1832SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) 1833 const { 1834 MachineFunction &MF = DAG.getMachineFunction(); 1835 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 1836 1837 MipsFI->setCallsEhReturn(); 1838 SDValue Chain = Op.getOperand(0); 1839 SDValue Offset = Op.getOperand(1); 1840 SDValue Handler = Op.getOperand(2); 1841 SDLoc DL(Op); 1842 EVT Ty = IsN64 ? MVT::i64 : MVT::i32; 1843 1844 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and 1845 // EH_RETURN nodes, so that instructions are emitted back-to-back. 1846 unsigned OffsetReg = IsN64 ? Mips::V1_64 : Mips::V1; 1847 unsigned AddrReg = IsN64 ? Mips::V0_64 : Mips::V0; 1848 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue()); 1849 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1)); 1850 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain, 1851 DAG.getRegister(OffsetReg, Ty), 1852 DAG.getRegister(AddrReg, getPointerTy()), 1853 Chain.getValue(1)); 1854} 1855 1856SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op, 1857 SelectionDAG &DAG) const { 1858 // FIXME: Need pseudo-fence for 'singlethread' fences 1859 // FIXME: Set SType for weaker fences where supported/appropriate. 1860 unsigned SType = 0; 1861 SDLoc DL(Op); 1862 return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0), 1863 DAG.getConstant(SType, MVT::i32)); 1864} 1865 1866SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op, 1867 SelectionDAG &DAG) const { 1868 SDLoc DL(Op); 1869 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 1870 SDValue Shamt = Op.getOperand(2); 1871 1872 // if shamt < 32: 1873 // lo = (shl lo, shamt) 1874 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt)) 1875 // else: 1876 // lo = 0 1877 // hi = (shl lo, shamt[4:0]) 1878 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 1879 DAG.getConstant(-1, MVT::i32)); 1880 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, 1881 DAG.getConstant(1, MVT::i32)); 1882 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo, 1883 Not); 1884 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt); 1885 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo); 1886 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt); 1887 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 1888 DAG.getConstant(0x20, MVT::i32)); 1889 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, 1890 DAG.getConstant(0, MVT::i32), ShiftLeftLo); 1891 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or); 1892 1893 SDValue Ops[2] = {Lo, Hi}; 1894 return DAG.getMergeValues(Ops, 2, DL); 1895} 1896 1897SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, 1898 bool IsSRA) const { 1899 SDLoc DL(Op); 1900 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 1901 SDValue Shamt = Op.getOperand(2); 1902 1903 // if shamt < 32: 1904 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt)) 1905 // if isSRA: 1906 // hi = (sra hi, shamt) 1907 // else: 1908 // hi = (srl hi, shamt) 1909 // else: 1910 // if isSRA: 1911 // lo = (sra hi, shamt[4:0]) 1912 // hi = (sra hi, 31) 1913 // else: 1914 // lo = (srl hi, shamt[4:0]) 1915 // hi = 0 1916 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 1917 DAG.getConstant(-1, MVT::i32)); 1918 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, 1919 DAG.getConstant(1, MVT::i32)); 1920 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not); 1921 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt); 1922 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo); 1923 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32, 1924 Hi, Shamt); 1925 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 1926 DAG.getConstant(0x20, MVT::i32)); 1927 SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi, 1928 DAG.getConstant(31, MVT::i32)); 1929 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or); 1930 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, 1931 IsSRA ? Shift31 : DAG.getConstant(0, MVT::i32), 1932 ShiftRightHi); 1933 1934 SDValue Ops[2] = {Lo, Hi}; 1935 return DAG.getMergeValues(Ops, 2, DL); 1936} 1937 1938static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, 1939 SDValue Chain, SDValue Src, unsigned Offset) { 1940 SDValue Ptr = LD->getBasePtr(); 1941 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT(); 1942 EVT BasePtrVT = Ptr.getValueType(); 1943 SDLoc DL(LD); 1944 SDVTList VTList = DAG.getVTList(VT, MVT::Other); 1945 1946 if (Offset) 1947 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 1948 DAG.getConstant(Offset, BasePtrVT)); 1949 1950 SDValue Ops[] = { Chain, Ptr, Src }; 1951 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT, 1952 LD->getMemOperand()); 1953} 1954 1955// Expand an unaligned 32 or 64-bit integer load node. 1956SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const { 1957 LoadSDNode *LD = cast<LoadSDNode>(Op); 1958 EVT MemVT = LD->getMemoryVT(); 1959 1960 // Return if load is aligned or if MemVT is neither i32 nor i64. 1961 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) || 1962 ((MemVT != MVT::i32) && (MemVT != MVT::i64))) 1963 return SDValue(); 1964 1965 bool IsLittle = Subtarget->isLittle(); 1966 EVT VT = Op.getValueType(); 1967 ISD::LoadExtType ExtType = LD->getExtensionType(); 1968 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT); 1969 1970 assert((VT == MVT::i32) || (VT == MVT::i64)); 1971 1972 // Expand 1973 // (set dst, (i64 (load baseptr))) 1974 // to 1975 // (set tmp, (ldl (add baseptr, 7), undef)) 1976 // (set dst, (ldr baseptr, tmp)) 1977 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) { 1978 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef, 1979 IsLittle ? 7 : 0); 1980 return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL, 1981 IsLittle ? 0 : 7); 1982 } 1983 1984 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, 1985 IsLittle ? 3 : 0); 1986 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, 1987 IsLittle ? 0 : 3); 1988 1989 // Expand 1990 // (set dst, (i32 (load baseptr))) or 1991 // (set dst, (i64 (sextload baseptr))) or 1992 // (set dst, (i64 (extload baseptr))) 1993 // to 1994 // (set tmp, (lwl (add baseptr, 3), undef)) 1995 // (set dst, (lwr baseptr, tmp)) 1996 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) || 1997 (ExtType == ISD::EXTLOAD)) 1998 return LWR; 1999 2000 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)); 2001 2002 // Expand 2003 // (set dst, (i64 (zextload baseptr))) 2004 // to 2005 // (set tmp0, (lwl (add baseptr, 3), undef)) 2006 // (set tmp1, (lwr baseptr, tmp0)) 2007 // (set tmp2, (shl tmp1, 32)) 2008 // (set dst, (srl tmp2, 32)) 2009 SDLoc DL(LD); 2010 SDValue Const32 = DAG.getConstant(32, MVT::i32); 2011 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); 2012 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); 2013 SDValue Ops[] = { SRL, LWR.getValue(1) }; 2014 return DAG.getMergeValues(Ops, 2, DL); 2015} 2016 2017static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, 2018 SDValue Chain, unsigned Offset) { 2019 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue(); 2020 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType(); 2021 SDLoc DL(SD); 2022 SDVTList VTList = DAG.getVTList(MVT::Other); 2023 2024 if (Offset) 2025 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2026 DAG.getConstant(Offset, BasePtrVT)); 2027 2028 SDValue Ops[] = { Chain, Value, Ptr }; 2029 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT, 2030 SD->getMemOperand()); 2031} 2032 2033// Expand an unaligned 32 or 64-bit integer store node. 2034static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG, 2035 bool IsLittle) { 2036 SDValue Value = SD->getValue(), Chain = SD->getChain(); 2037 EVT VT = Value.getValueType(); 2038 2039 // Expand 2040 // (store val, baseptr) or 2041 // (truncstore val, baseptr) 2042 // to 2043 // (swl val, (add baseptr, 3)) 2044 // (swr val, baseptr) 2045 if ((VT == MVT::i32) || SD->isTruncatingStore()) { 2046 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain, 2047 IsLittle ? 3 : 0); 2048 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); 2049 } 2050 2051 assert(VT == MVT::i64); 2052 2053 // Expand 2054 // (store val, baseptr) 2055 // to 2056 // (sdl val, (add baseptr, 7)) 2057 // (sdr val, baseptr) 2058 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0); 2059 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7); 2060} 2061 2062// Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr). 2063static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG) { 2064 SDValue Val = SD->getValue(); 2065 2066 if (Val.getOpcode() != ISD::FP_TO_SINT) 2067 return SDValue(); 2068 2069 EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits()); 2070 SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy, 2071 Val.getOperand(0)); 2072 2073 return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(), 2074 SD->getPointerInfo(), SD->isVolatile(), 2075 SD->isNonTemporal(), SD->getAlignment()); 2076} 2077 2078SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const { 2079 StoreSDNode *SD = cast<StoreSDNode>(Op); 2080 EVT MemVT = SD->getMemoryVT(); 2081 2082 // Lower unaligned integer stores. 2083 if ((SD->getAlignment() < MemVT.getSizeInBits() / 8) && 2084 ((MemVT == MVT::i32) || (MemVT == MVT::i64))) 2085 return lowerUnalignedIntStore(SD, DAG, Subtarget->isLittle()); 2086 2087 return lowerFP_TO_SINT_STORE(SD, DAG); 2088} 2089 2090SDValue MipsTargetLowering::lowerADD(SDValue Op, SelectionDAG &DAG) const { 2091 if (Op->getOperand(0).getOpcode() != ISD::FRAMEADDR 2092 || cast<ConstantSDNode> 2093 (Op->getOperand(0).getOperand(0))->getZExtValue() != 0 2094 || Op->getOperand(1).getOpcode() != ISD::FRAME_TO_ARGS_OFFSET) 2095 return SDValue(); 2096 2097 // The pattern 2098 // (add (frameaddr 0), (frame_to_args_offset)) 2099 // results from lowering llvm.eh.dwarf.cfa intrinsic. Transform it to 2100 // (add FrameObject, 0) 2101 // where FrameObject is a fixed StackObject with offset 0 which points to 2102 // the old stack pointer. 2103 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2104 EVT ValTy = Op->getValueType(0); 2105 int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false); 2106 SDValue InArgsAddr = DAG.getFrameIndex(FI, ValTy); 2107 return DAG.getNode(ISD::ADD, SDLoc(Op), ValTy, InArgsAddr, 2108 DAG.getConstant(0, ValTy)); 2109} 2110 2111SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op, 2112 SelectionDAG &DAG) const { 2113 EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits()); 2114 SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy, 2115 Op.getOperand(0)); 2116 return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc); 2117} 2118 2119//===----------------------------------------------------------------------===// 2120// Calling Convention Implementation 2121//===----------------------------------------------------------------------===// 2122 2123//===----------------------------------------------------------------------===// 2124// TODO: Implement a generic logic using tblgen that can support this. 2125// Mips O32 ABI rules: 2126// --- 2127// i32 - Passed in A0, A1, A2, A3 and stack 2128// f32 - Only passed in f32 registers if no int reg has been used yet to hold 2129// an argument. Otherwise, passed in A1, A2, A3 and stack. 2130// f64 - Only passed in two aliased f32 registers if no int reg has been used 2131// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 2132// not used, it must be shadowed. If only A3 is avaiable, shadow it and 2133// go to stack. 2134// 2135// For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 2136//===----------------------------------------------------------------------===// 2137 2138static bool CC_MipsO32(unsigned ValNo, MVT ValVT, 2139 MVT LocVT, CCValAssign::LocInfo LocInfo, 2140 ISD::ArgFlagsTy ArgFlags, CCState &State, 2141 const uint16_t *F64Regs) { 2142 2143 static const unsigned IntRegsSize=4, FloatRegsSize=2; 2144 2145 static const uint16_t IntRegs[] = { 2146 Mips::A0, Mips::A1, Mips::A2, Mips::A3 2147 }; 2148 static const uint16_t F32Regs[] = { 2149 Mips::F12, Mips::F14 2150 }; 2151 2152 // Do not process byval args here. 2153 if (ArgFlags.isByVal()) 2154 return true; 2155 2156 // Promote i8 and i16 2157 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 2158 LocVT = MVT::i32; 2159 if (ArgFlags.isSExt()) 2160 LocInfo = CCValAssign::SExt; 2161 else if (ArgFlags.isZExt()) 2162 LocInfo = CCValAssign::ZExt; 2163 else 2164 LocInfo = CCValAssign::AExt; 2165 } 2166 2167 unsigned Reg; 2168 2169 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 2170 // is true: function is vararg, argument is 3rd or higher, there is previous 2171 // argument which is not f32 or f64. 2172 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 2173 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo; 2174 unsigned OrigAlign = ArgFlags.getOrigAlign(); 2175 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8); 2176 2177 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 2178 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2179 // If this is the first part of an i64 arg, 2180 // the allocated register must be either A0 or A2. 2181 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 2182 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2183 LocVT = MVT::i32; 2184 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 2185 // Allocate int register and shadow next int register. If first 2186 // available register is Mips::A1 or Mips::A3, shadow it too. 2187 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2188 if (Reg == Mips::A1 || Reg == Mips::A3) 2189 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2190 State.AllocateReg(IntRegs, IntRegsSize); 2191 LocVT = MVT::i32; 2192 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 2193 // we are guaranteed to find an available float register 2194 if (ValVT == MVT::f32) { 2195 Reg = State.AllocateReg(F32Regs, FloatRegsSize); 2196 // Shadow int register 2197 State.AllocateReg(IntRegs, IntRegsSize); 2198 } else { 2199 Reg = State.AllocateReg(F64Regs, FloatRegsSize); 2200 // Shadow int registers 2201 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize); 2202 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 2203 State.AllocateReg(IntRegs, IntRegsSize); 2204 State.AllocateReg(IntRegs, IntRegsSize); 2205 } 2206 } else 2207 llvm_unreachable("Cannot handle this ValVT."); 2208 2209 if (!Reg) { 2210 unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3, 2211 OrigAlign); 2212 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 2213 } else 2214 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2215 2216 return false; 2217} 2218 2219static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, 2220 MVT LocVT, CCValAssign::LocInfo LocInfo, 2221 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2222 static const uint16_t F64Regs[] = { Mips::D6, Mips::D7 }; 2223 2224 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2225} 2226 2227static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, 2228 MVT LocVT, CCValAssign::LocInfo LocInfo, 2229 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2230 static const uint16_t F64Regs[] = { Mips::D12_64, Mips::D12_64 }; 2231 2232 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2233} 2234 2235#include "MipsGenCallingConv.inc" 2236 2237//===----------------------------------------------------------------------===// 2238// Call Calling Convention Implementation 2239//===----------------------------------------------------------------------===// 2240 2241// Return next O32 integer argument register. 2242static unsigned getNextIntArgReg(unsigned Reg) { 2243 assert((Reg == Mips::A0) || (Reg == Mips::A2)); 2244 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3; 2245} 2246 2247SDValue 2248MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset, 2249 SDValue Chain, SDValue Arg, SDLoc DL, 2250 bool IsTailCall, SelectionDAG &DAG) const { 2251 if (!IsTailCall) { 2252 SDValue PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, 2253 DAG.getIntPtrConstant(Offset)); 2254 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), false, 2255 false, 0); 2256 } 2257 2258 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2259 int FI = MFI->CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false); 2260 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2261 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(), 2262 /*isVolatile=*/ true, false, 0); 2263} 2264 2265void MipsTargetLowering:: 2266getOpndList(SmallVectorImpl<SDValue> &Ops, 2267 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 2268 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 2269 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const { 2270 // Insert node "GP copy globalreg" before call to function. 2271 // 2272 // R_MIPS_CALL* operators (emitted when non-internal functions are called 2273 // in PIC mode) allow symbols to be resolved via lazy binding. 2274 // The lazy binding stub requires GP to point to the GOT. 2275 if (IsPICCall && !InternalLinkage) { 2276 unsigned GPReg = IsN64 ? Mips::GP_64 : Mips::GP; 2277 EVT Ty = IsN64 ? MVT::i64 : MVT::i32; 2278 RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty))); 2279 } 2280 2281 // Build a sequence of copy-to-reg nodes chained together with token 2282 // chain and flag operands which copy the outgoing args into registers. 2283 // The InFlag in necessary since all emitted instructions must be 2284 // stuck together. 2285 SDValue InFlag; 2286 2287 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2288 Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first, 2289 RegsToPass[i].second, InFlag); 2290 InFlag = Chain.getValue(1); 2291 } 2292 2293 // Add argument registers to the end of the list so that they are 2294 // known live into the call. 2295 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2296 Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first, 2297 RegsToPass[i].second.getValueType())); 2298 2299 // Add a register mask operand representing the call-preserved registers. 2300 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 2301 const uint32_t *Mask = TRI->getCallPreservedMask(CLI.CallConv); 2302 assert(Mask && "Missing call preserved mask for calling convention"); 2303 if (Subtarget->inMips16HardFloat()) { 2304 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) { 2305 llvm::StringRef Sym = G->getGlobal()->getName(); 2306 Function *F = G->getGlobal()->getParent()->getFunction(Sym); 2307 if (F->hasFnAttribute("__Mips16RetHelper")) { 2308 Mask = MipsRegisterInfo::getMips16RetHelperMask(); 2309 } 2310 } 2311 } 2312 Ops.push_back(CLI.DAG.getRegisterMask(Mask)); 2313 2314 if (InFlag.getNode()) 2315 Ops.push_back(InFlag); 2316} 2317 2318/// LowerCall - functions arguments are copied from virtual regs to 2319/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 2320SDValue 2321MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 2322 SmallVectorImpl<SDValue> &InVals) const { 2323 SelectionDAG &DAG = CLI.DAG; 2324 SDLoc DL = CLI.DL; 2325 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 2326 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 2327 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 2328 SDValue Chain = CLI.Chain; 2329 SDValue Callee = CLI.Callee; 2330 bool &IsTailCall = CLI.IsTailCall; 2331 CallingConv::ID CallConv = CLI.CallConv; 2332 bool IsVarArg = CLI.IsVarArg; 2333 2334 MachineFunction &MF = DAG.getMachineFunction(); 2335 MachineFrameInfo *MFI = MF.getFrameInfo(); 2336 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering(); 2337 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 2338 2339 // Analyze operands of the call, assigning locations to each operand. 2340 SmallVector<CCValAssign, 16> ArgLocs; 2341 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 2342 getTargetMachine(), ArgLocs, *DAG.getContext()); 2343 MipsCC::SpecialCallingConvType SpecialCallingConv = 2344 getSpecialCallingConv(Callee); 2345 MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo, 2346 SpecialCallingConv); 2347 2348 MipsCCInfo.analyzeCallOperands(Outs, IsVarArg, 2349 Subtarget->mipsSEUsesSoftFloat(), 2350 Callee.getNode(), CLI.Args); 2351 2352 // Get a count of how many bytes are to be pushed on the stack. 2353 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 2354 2355 // Check if it's really possible to do a tail call. 2356 if (IsTailCall) 2357 IsTailCall = 2358 isEligibleForTailCallOptimization(MipsCCInfo, NextStackOffset, 2359 *MF.getInfo<MipsFunctionInfo>()); 2360 2361 if (IsTailCall) 2362 ++NumTailCalls; 2363 2364 // Chain is the output chain of the last Load/Store or CopyToReg node. 2365 // ByValChain is the output chain of the last Memcpy node created for copying 2366 // byval arguments to the stack. 2367 unsigned StackAlignment = TFL->getStackAlignment(); 2368 NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment); 2369 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true); 2370 2371 if (!IsTailCall) 2372 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL); 2373 2374 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, 2375 IsN64 ? Mips::SP_64 : Mips::SP, 2376 getPointerTy()); 2377 2378 // With EABI is it possible to have 16 args on registers. 2379 std::deque< std::pair<unsigned, SDValue> > RegsToPass; 2380 SmallVector<SDValue, 8> MemOpChains; 2381 MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin(); 2382 2383 // Walk the register/memloc assignments, inserting copies/loads. 2384 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2385 SDValue Arg = OutVals[i]; 2386 CCValAssign &VA = ArgLocs[i]; 2387 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); 2388 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2389 2390 // ByVal Arg. 2391 if (Flags.isByVal()) { 2392 assert(Flags.getByValSize() && 2393 "ByVal args of size 0 should have been ignored by front-end."); 2394 assert(ByValArg != MipsCCInfo.byval_end()); 2395 assert(!IsTailCall && 2396 "Do not tail-call optimize if there is a byval argument."); 2397 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg, 2398 MipsCCInfo, *ByValArg, Flags, Subtarget->isLittle()); 2399 ++ByValArg; 2400 continue; 2401 } 2402 2403 // Promote the value if needed. 2404 switch (VA.getLocInfo()) { 2405 default: llvm_unreachable("Unknown loc info!"); 2406 case CCValAssign::Full: 2407 if (VA.isRegLoc()) { 2408 if ((ValVT == MVT::f32 && LocVT == MVT::i32) || 2409 (ValVT == MVT::f64 && LocVT == MVT::i64) || 2410 (ValVT == MVT::i64 && LocVT == MVT::f64)) 2411 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 2412 else if (ValVT == MVT::f64 && LocVT == MVT::i32) { 2413 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2414 Arg, DAG.getConstant(0, MVT::i32)); 2415 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2416 Arg, DAG.getConstant(1, MVT::i32)); 2417 if (!Subtarget->isLittle()) 2418 std::swap(Lo, Hi); 2419 unsigned LocRegLo = VA.getLocReg(); 2420 unsigned LocRegHigh = getNextIntArgReg(LocRegLo); 2421 RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); 2422 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); 2423 continue; 2424 } 2425 } 2426 break; 2427 case CCValAssign::SExt: 2428 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg); 2429 break; 2430 case CCValAssign::ZExt: 2431 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg); 2432 break; 2433 case CCValAssign::AExt: 2434 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg); 2435 break; 2436 } 2437 2438 // Arguments that can be passed on register must be kept at 2439 // RegsToPass vector 2440 if (VA.isRegLoc()) { 2441 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2442 continue; 2443 } 2444 2445 // Register can't get to this point... 2446 assert(VA.isMemLoc()); 2447 2448 // emit ISD::STORE whichs stores the 2449 // parameter value to a stack Location 2450 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(), 2451 Chain, Arg, DL, IsTailCall, DAG)); 2452 } 2453 2454 // Transform all store nodes into one single node because all store 2455 // nodes are independent of each other. 2456 if (!MemOpChains.empty()) 2457 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 2458 &MemOpChains[0], MemOpChains.size()); 2459 2460 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 2461 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 2462 // node so that legalize doesn't hack it. 2463 bool IsPICCall = (IsN64 || IsPIC); // true if calls are translated to jalr $25 2464 bool GlobalOrExternal = false, InternalLinkage = false; 2465 SDValue CalleeLo; 2466 2467 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2468 if (IsPICCall) { 2469 InternalLinkage = G->getGlobal()->hasInternalLinkage(); 2470 2471 if (InternalLinkage) 2472 Callee = getAddrLocal(Callee, DAG, HasMips64); 2473 else if (LargeGOT) 2474 Callee = getAddrGlobalLargeGOT(Callee, DAG, MipsII::MO_CALL_HI16, 2475 MipsII::MO_CALL_LO16); 2476 else 2477 Callee = getAddrGlobal(Callee, DAG, MipsII::MO_GOT_CALL); 2478 } else 2479 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, getPointerTy(), 0, 2480 MipsII::MO_NO_FLAG); 2481 GlobalOrExternal = true; 2482 } 2483 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2484 if (!IsN64 && !IsPIC) // !N64 && static 2485 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2486 MipsII::MO_NO_FLAG); 2487 else if (LargeGOT) 2488 Callee = getAddrGlobalLargeGOT(Callee, DAG, MipsII::MO_CALL_HI16, 2489 MipsII::MO_CALL_LO16); 2490 else // N64 || PIC 2491 Callee = getAddrGlobal(Callee, DAG, MipsII::MO_GOT_CALL); 2492 2493 GlobalOrExternal = true; 2494 } 2495 2496 SmallVector<SDValue, 8> Ops(1, Chain); 2497 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2498 2499 getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, InternalLinkage, 2500 CLI, Callee, Chain); 2501 2502 if (IsTailCall) 2503 return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, &Ops[0], Ops.size()); 2504 2505 Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, &Ops[0], Ops.size()); 2506 SDValue InFlag = Chain.getValue(1); 2507 2508 // Create the CALLSEQ_END node. 2509 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal, 2510 DAG.getIntPtrConstant(0, true), InFlag, DL); 2511 InFlag = Chain.getValue(1); 2512 2513 // Handle result values, copying them out of physregs into vregs that we 2514 // return. 2515 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, 2516 Ins, DL, DAG, InVals, CLI.Callee.getNode(), CLI.RetTy); 2517} 2518 2519/// LowerCallResult - Lower the result values of a call into the 2520/// appropriate copies out of appropriate physical registers. 2521SDValue 2522MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 2523 CallingConv::ID CallConv, bool IsVarArg, 2524 const SmallVectorImpl<ISD::InputArg> &Ins, 2525 SDLoc DL, SelectionDAG &DAG, 2526 SmallVectorImpl<SDValue> &InVals, 2527 const SDNode *CallNode, 2528 const Type *RetTy) const { 2529 // Assign locations to each value returned by this call. 2530 SmallVector<CCValAssign, 16> RVLocs; 2531 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 2532 getTargetMachine(), RVLocs, *DAG.getContext()); 2533 MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo); 2534 2535 MipsCCInfo.analyzeCallResult(Ins, Subtarget->mipsSEUsesSoftFloat(), 2536 CallNode, RetTy); 2537 2538 // Copy all of the result registers out of their specified physreg. 2539 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2540 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), 2541 RVLocs[i].getLocVT(), InFlag); 2542 Chain = Val.getValue(1); 2543 InFlag = Val.getValue(2); 2544 2545 if (RVLocs[i].getValVT() != RVLocs[i].getLocVT()) 2546 Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getValVT(), Val); 2547 2548 InVals.push_back(Val); 2549 } 2550 2551 return Chain; 2552} 2553 2554//===----------------------------------------------------------------------===// 2555// Formal Arguments Calling Convention Implementation 2556//===----------------------------------------------------------------------===// 2557/// LowerFormalArguments - transform physical registers into virtual registers 2558/// and generate load operations for arguments places on the stack. 2559SDValue 2560MipsTargetLowering::LowerFormalArguments(SDValue Chain, 2561 CallingConv::ID CallConv, 2562 bool IsVarArg, 2563 const SmallVectorImpl<ISD::InputArg> &Ins, 2564 SDLoc DL, SelectionDAG &DAG, 2565 SmallVectorImpl<SDValue> &InVals) 2566 const { 2567 MachineFunction &MF = DAG.getMachineFunction(); 2568 MachineFrameInfo *MFI = MF.getFrameInfo(); 2569 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2570 2571 MipsFI->setVarArgsFrameIndex(0); 2572 2573 // Used with vargs to acumulate store chains. 2574 std::vector<SDValue> OutChains; 2575 2576 // Assign locations to all of the incoming arguments. 2577 SmallVector<CCValAssign, 16> ArgLocs; 2578 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 2579 getTargetMachine(), ArgLocs, *DAG.getContext()); 2580 MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo); 2581 Function::const_arg_iterator FuncArg = 2582 DAG.getMachineFunction().getFunction()->arg_begin(); 2583 bool UseSoftFloat = Subtarget->mipsSEUsesSoftFloat(); 2584 2585 MipsCCInfo.analyzeFormalArguments(Ins, UseSoftFloat, FuncArg); 2586 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(), 2587 MipsCCInfo.hasByValArg()); 2588 2589 unsigned CurArgIdx = 0; 2590 MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin(); 2591 2592 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2593 CCValAssign &VA = ArgLocs[i]; 2594 std::advance(FuncArg, Ins[i].OrigArgIndex - CurArgIdx); 2595 CurArgIdx = Ins[i].OrigArgIndex; 2596 EVT ValVT = VA.getValVT(); 2597 ISD::ArgFlagsTy Flags = Ins[i].Flags; 2598 bool IsRegLoc = VA.isRegLoc(); 2599 2600 if (Flags.isByVal()) { 2601 assert(Flags.getByValSize() && 2602 "ByVal args of size 0 should have been ignored by front-end."); 2603 assert(ByValArg != MipsCCInfo.byval_end()); 2604 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg, 2605 MipsCCInfo, *ByValArg); 2606 ++ByValArg; 2607 continue; 2608 } 2609 2610 // Arguments stored on registers 2611 if (IsRegLoc) { 2612 EVT RegVT = VA.getLocVT(); 2613 unsigned ArgReg = VA.getLocReg(); 2614 const TargetRegisterClass *RC; 2615 2616 if (RegVT == MVT::i32) 2617 RC = Subtarget->inMips16Mode()? &Mips::CPU16RegsRegClass : 2618 &Mips::GPR32RegClass; 2619 else if (RegVT == MVT::i64) 2620 RC = &Mips::GPR64RegClass; 2621 else if (RegVT == MVT::f32) 2622 RC = &Mips::FGR32RegClass; 2623 else if (RegVT == MVT::f64) 2624 RC = Subtarget->isFP64bit() ? &Mips::FGR64RegClass : 2625 &Mips::AFGR64RegClass; 2626 else 2627 llvm_unreachable("RegVT not supported by FormalArguments Lowering"); 2628 2629 // Transform the arguments stored on 2630 // physical registers into virtual ones 2631 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC); 2632 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); 2633 2634 // If this is an 8 or 16-bit value, it has been passed promoted 2635 // to 32 bits. Insert an assert[sz]ext to capture this, then 2636 // truncate to the right size. 2637 if (VA.getLocInfo() != CCValAssign::Full) { 2638 unsigned Opcode = 0; 2639 if (VA.getLocInfo() == CCValAssign::SExt) 2640 Opcode = ISD::AssertSext; 2641 else if (VA.getLocInfo() == CCValAssign::ZExt) 2642 Opcode = ISD::AssertZext; 2643 if (Opcode) 2644 ArgValue = DAG.getNode(Opcode, DL, RegVT, ArgValue, 2645 DAG.getValueType(ValVT)); 2646 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, ValVT, ArgValue); 2647 } 2648 2649 // Handle floating point arguments passed in integer registers and 2650 // long double arguments passed in floating point registers. 2651 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || 2652 (RegVT == MVT::i64 && ValVT == MVT::f64) || 2653 (RegVT == MVT::f64 && ValVT == MVT::i64)) 2654 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue); 2655 else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) { 2656 unsigned Reg2 = addLiveIn(DAG.getMachineFunction(), 2657 getNextIntArgReg(ArgReg), RC); 2658 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); 2659 if (!Subtarget->isLittle()) 2660 std::swap(ArgValue, ArgValue2); 2661 ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, 2662 ArgValue, ArgValue2); 2663 } 2664 2665 InVals.push_back(ArgValue); 2666 } else { // VA.isRegLoc() 2667 2668 // sanity check 2669 assert(VA.isMemLoc()); 2670 2671 // The stack pointer offset is relative to the caller stack frame. 2672 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 2673 VA.getLocMemOffset(), true); 2674 2675 // Create load nodes to retrieve arguments from the stack 2676 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2677 InVals.push_back(DAG.getLoad(ValVT, DL, Chain, FIN, 2678 MachinePointerInfo::getFixedStack(FI), 2679 false, false, false, 0)); 2680 } 2681 } 2682 2683 // The mips ABIs for returning structs by value requires that we copy 2684 // the sret argument into $v0 for the return. Save the argument into 2685 // a virtual register so that we can access it from the return points. 2686 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 2687 unsigned Reg = MipsFI->getSRetReturnReg(); 2688 if (!Reg) { 2689 Reg = MF.getRegInfo(). 2690 createVirtualRegister(getRegClassFor(IsN64 ? MVT::i64 : MVT::i32)); 2691 MipsFI->setSRetReturnReg(Reg); 2692 } 2693 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[0]); 2694 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain); 2695 } 2696 2697 if (IsVarArg) 2698 writeVarArgRegs(OutChains, MipsCCInfo, Chain, DL, DAG); 2699 2700 // All stores are grouped in one node to allow the matching between 2701 // the size of Ins and InVals. This only happens when on varg functions 2702 if (!OutChains.empty()) { 2703 OutChains.push_back(Chain); 2704 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 2705 &OutChains[0], OutChains.size()); 2706 } 2707 2708 return Chain; 2709} 2710 2711//===----------------------------------------------------------------------===// 2712// Return Value Calling Convention Implementation 2713//===----------------------------------------------------------------------===// 2714 2715bool 2716MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv, 2717 MachineFunction &MF, bool IsVarArg, 2718 const SmallVectorImpl<ISD::OutputArg> &Outs, 2719 LLVMContext &Context) const { 2720 SmallVector<CCValAssign, 16> RVLocs; 2721 CCState CCInfo(CallConv, IsVarArg, MF, getTargetMachine(), 2722 RVLocs, Context); 2723 return CCInfo.CheckReturn(Outs, RetCC_Mips); 2724} 2725 2726SDValue 2727MipsTargetLowering::LowerReturn(SDValue Chain, 2728 CallingConv::ID CallConv, bool IsVarArg, 2729 const SmallVectorImpl<ISD::OutputArg> &Outs, 2730 const SmallVectorImpl<SDValue> &OutVals, 2731 SDLoc DL, SelectionDAG &DAG) const { 2732 // CCValAssign - represent the assignment of 2733 // the return value to a location 2734 SmallVector<CCValAssign, 16> RVLocs; 2735 MachineFunction &MF = DAG.getMachineFunction(); 2736 2737 // CCState - Info about the registers and stack slot. 2738 CCState CCInfo(CallConv, IsVarArg, MF, getTargetMachine(), RVLocs, 2739 *DAG.getContext()); 2740 MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo); 2741 2742 // Analyze return values. 2743 MipsCCInfo.analyzeReturn(Outs, Subtarget->mipsSEUsesSoftFloat(), 2744 MF.getFunction()->getReturnType()); 2745 2746 SDValue Flag; 2747 SmallVector<SDValue, 4> RetOps(1, Chain); 2748 2749 // Copy the result values into the output registers. 2750 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2751 SDValue Val = OutVals[i]; 2752 CCValAssign &VA = RVLocs[i]; 2753 assert(VA.isRegLoc() && "Can only return in registers!"); 2754 2755 if (RVLocs[i].getValVT() != RVLocs[i].getLocVT()) 2756 Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getLocVT(), Val); 2757 2758 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag); 2759 2760 // Guarantee that all emitted copies are stuck together with flags. 2761 Flag = Chain.getValue(1); 2762 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 2763 } 2764 2765 // The mips ABIs for returning structs by value requires that we copy 2766 // the sret argument into $v0 for the return. We saved the argument into 2767 // a virtual register in the entry block, so now we copy the value out 2768 // and into $v0. 2769 if (MF.getFunction()->hasStructRetAttr()) { 2770 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2771 unsigned Reg = MipsFI->getSRetReturnReg(); 2772 2773 if (!Reg) 2774 llvm_unreachable("sret virtual register not created in the entry block"); 2775 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy()); 2776 unsigned V0 = IsN64 ? Mips::V0_64 : Mips::V0; 2777 2778 Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag); 2779 Flag = Chain.getValue(1); 2780 RetOps.push_back(DAG.getRegister(V0, getPointerTy())); 2781 } 2782 2783 RetOps[0] = Chain; // Update chain. 2784 2785 // Add the flag if we have it. 2786 if (Flag.getNode()) 2787 RetOps.push_back(Flag); 2788 2789 // Return on Mips is always a "jr $ra" 2790 return DAG.getNode(MipsISD::Ret, DL, MVT::Other, &RetOps[0], RetOps.size()); 2791} 2792 2793//===----------------------------------------------------------------------===// 2794// Mips Inline Assembly Support 2795//===----------------------------------------------------------------------===// 2796 2797/// getConstraintType - Given a constraint letter, return the type of 2798/// constraint it is for this target. 2799MipsTargetLowering::ConstraintType MipsTargetLowering:: 2800getConstraintType(const std::string &Constraint) const 2801{ 2802 // Mips specific constrainy 2803 // GCC config/mips/constraints.md 2804 // 2805 // 'd' : An address register. Equivalent to r 2806 // unless generating MIPS16 code. 2807 // 'y' : Equivalent to r; retained for 2808 // backwards compatibility. 2809 // 'c' : A register suitable for use in an indirect 2810 // jump. This will always be $25 for -mabicalls. 2811 // 'l' : The lo register. 1 word storage. 2812 // 'x' : The hilo register pair. Double word storage. 2813 if (Constraint.size() == 1) { 2814 switch (Constraint[0]) { 2815 default : break; 2816 case 'd': 2817 case 'y': 2818 case 'f': 2819 case 'c': 2820 case 'l': 2821 case 'x': 2822 return C_RegisterClass; 2823 case 'R': 2824 return C_Memory; 2825 } 2826 } 2827 return TargetLowering::getConstraintType(Constraint); 2828} 2829 2830/// Examine constraint type and operand type and determine a weight value. 2831/// This object must already have been set up with the operand type 2832/// and the current alternative constraint selected. 2833TargetLowering::ConstraintWeight 2834MipsTargetLowering::getSingleConstraintMatchWeight( 2835 AsmOperandInfo &info, const char *constraint) const { 2836 ConstraintWeight weight = CW_Invalid; 2837 Value *CallOperandVal = info.CallOperandVal; 2838 // If we don't have a value, we can't do a match, 2839 // but allow it at the lowest weight. 2840 if (CallOperandVal == NULL) 2841 return CW_Default; 2842 Type *type = CallOperandVal->getType(); 2843 // Look at the constraint type. 2844 switch (*constraint) { 2845 default: 2846 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 2847 break; 2848 case 'd': 2849 case 'y': 2850 if (type->isIntegerTy()) 2851 weight = CW_Register; 2852 break; 2853 case 'f': 2854 if (type->isFloatTy()) 2855 weight = CW_Register; 2856 break; 2857 case 'c': // $25 for indirect jumps 2858 case 'l': // lo register 2859 case 'x': // hilo register pair 2860 if (type->isIntegerTy()) 2861 weight = CW_SpecificReg; 2862 break; 2863 case 'I': // signed 16 bit immediate 2864 case 'J': // integer zero 2865 case 'K': // unsigned 16 bit immediate 2866 case 'L': // signed 32 bit immediate where lower 16 bits are 0 2867 case 'N': // immediate in the range of -65535 to -1 (inclusive) 2868 case 'O': // signed 15 bit immediate (+- 16383) 2869 case 'P': // immediate in the range of 65535 to 1 (inclusive) 2870 if (isa<ConstantInt>(CallOperandVal)) 2871 weight = CW_Constant; 2872 break; 2873 case 'R': 2874 weight = CW_Memory; 2875 break; 2876 } 2877 return weight; 2878} 2879 2880/// This is a helper function to parse a physical register string and split it 2881/// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag 2882/// that is returned indicates whether parsing was successful. The second flag 2883/// is true if the numeric part exists. 2884static std::pair<bool, bool> 2885parsePhysicalReg(const StringRef &C, std::string &Prefix, 2886 unsigned long long &Reg) { 2887 if (C.front() != '{' || C.back() != '}') 2888 return std::make_pair(false, false); 2889 2890 // Search for the first numeric character. 2891 StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1; 2892 I = std::find_if(B, E, std::ptr_fun(isdigit)); 2893 2894 Prefix.assign(B, I - B); 2895 2896 // The second flag is set to false if no numeric characters were found. 2897 if (I == E) 2898 return std::make_pair(true, false); 2899 2900 // Parse the numeric characters. 2901 return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg), 2902 true); 2903} 2904 2905std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering:: 2906parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const { 2907 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 2908 const TargetRegisterClass *RC; 2909 std::string Prefix; 2910 unsigned long long Reg; 2911 2912 std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg); 2913 2914 if (!R.first) 2915 return std::make_pair((unsigned)0, (const TargetRegisterClass*)0); 2916 2917 if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo. 2918 // No numeric characters follow "hi" or "lo". 2919 if (R.second) 2920 return std::make_pair((unsigned)0, (const TargetRegisterClass*)0); 2921 2922 RC = TRI->getRegClass(Prefix == "hi" ? 2923 Mips::HI32RegClassID : Mips::LO32RegClassID); 2924 return std::make_pair(*(RC->begin()), RC); 2925 } 2926 2927 if (!R.second) 2928 return std::make_pair((unsigned)0, (const TargetRegisterClass*)0); 2929 2930 if (Prefix == "$f") { // Parse $f0-$f31. 2931 // If the size of FP registers is 64-bit or Reg is an even number, select 2932 // the 64-bit register class. Otherwise, select the 32-bit register class. 2933 if (VT == MVT::Other) 2934 VT = (Subtarget->isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32; 2935 2936 RC= getRegClassFor(VT); 2937 2938 if (RC == &Mips::AFGR64RegClass) { 2939 assert(Reg % 2 == 0); 2940 Reg >>= 1; 2941 } 2942 } else if (Prefix == "$fcc") { // Parse $fcc0-$fcc7. 2943 RC = TRI->getRegClass(Mips::FCCRegClassID); 2944 } else { // Parse $0-$31. 2945 assert(Prefix == "$"); 2946 RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT); 2947 } 2948 2949 assert(Reg < RC->getNumRegs()); 2950 return std::make_pair(*(RC->begin() + Reg), RC); 2951} 2952 2953/// Given a register class constraint, like 'r', if this corresponds directly 2954/// to an LLVM register class, return a register of 0 and the register class 2955/// pointer. 2956std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering:: 2957getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const 2958{ 2959 if (Constraint.size() == 1) { 2960 switch (Constraint[0]) { 2961 case 'd': // Address register. Same as 'r' unless generating MIPS16 code. 2962 case 'y': // Same as 'r'. Exists for compatibility. 2963 case 'r': 2964 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { 2965 if (Subtarget->inMips16Mode()) 2966 return std::make_pair(0U, &Mips::CPU16RegsRegClass); 2967 return std::make_pair(0U, &Mips::GPR32RegClass); 2968 } 2969 if (VT == MVT::i64 && !HasMips64) 2970 return std::make_pair(0U, &Mips::GPR32RegClass); 2971 if (VT == MVT::i64 && HasMips64) 2972 return std::make_pair(0U, &Mips::GPR64RegClass); 2973 // This will generate an error message 2974 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 2975 case 'f': 2976 if (VT == MVT::f32) 2977 return std::make_pair(0U, &Mips::FGR32RegClass); 2978 if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) { 2979 if (Subtarget->isFP64bit()) 2980 return std::make_pair(0U, &Mips::FGR64RegClass); 2981 return std::make_pair(0U, &Mips::AFGR64RegClass); 2982 } 2983 break; 2984 case 'c': // register suitable for indirect jump 2985 if (VT == MVT::i32) 2986 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass); 2987 assert(VT == MVT::i64 && "Unexpected type."); 2988 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass); 2989 case 'l': // register suitable for indirect jump 2990 if (VT == MVT::i32) 2991 return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass); 2992 return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass); 2993 case 'x': // register suitable for indirect jump 2994 // Fixme: Not triggering the use of both hi and low 2995 // This will generate an error message 2996 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 2997 } 2998 } 2999 3000 std::pair<unsigned, const TargetRegisterClass *> R; 3001 R = parseRegForInlineAsmConstraint(Constraint, VT); 3002 3003 if (R.second) 3004 return R; 3005 3006 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 3007} 3008 3009/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 3010/// vector. If it is invalid, don't add anything to Ops. 3011void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 3012 std::string &Constraint, 3013 std::vector<SDValue>&Ops, 3014 SelectionDAG &DAG) const { 3015 SDValue Result(0, 0); 3016 3017 // Only support length 1 constraints for now. 3018 if (Constraint.length() > 1) return; 3019 3020 char ConstraintLetter = Constraint[0]; 3021 switch (ConstraintLetter) { 3022 default: break; // This will fall through to the generic implementation 3023 case 'I': // Signed 16 bit constant 3024 // If this fails, the parent routine will give an error 3025 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3026 EVT Type = Op.getValueType(); 3027 int64_t Val = C->getSExtValue(); 3028 if (isInt<16>(Val)) { 3029 Result = DAG.getTargetConstant(Val, Type); 3030 break; 3031 } 3032 } 3033 return; 3034 case 'J': // integer zero 3035 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3036 EVT Type = Op.getValueType(); 3037 int64_t Val = C->getZExtValue(); 3038 if (Val == 0) { 3039 Result = DAG.getTargetConstant(0, Type); 3040 break; 3041 } 3042 } 3043 return; 3044 case 'K': // unsigned 16 bit immediate 3045 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3046 EVT Type = Op.getValueType(); 3047 uint64_t Val = (uint64_t)C->getZExtValue(); 3048 if (isUInt<16>(Val)) { 3049 Result = DAG.getTargetConstant(Val, Type); 3050 break; 3051 } 3052 } 3053 return; 3054 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3055 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3056 EVT Type = Op.getValueType(); 3057 int64_t Val = C->getSExtValue(); 3058 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){ 3059 Result = DAG.getTargetConstant(Val, Type); 3060 break; 3061 } 3062 } 3063 return; 3064 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3065 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3066 EVT Type = Op.getValueType(); 3067 int64_t Val = C->getSExtValue(); 3068 if ((Val >= -65535) && (Val <= -1)) { 3069 Result = DAG.getTargetConstant(Val, Type); 3070 break; 3071 } 3072 } 3073 return; 3074 case 'O': // signed 15 bit immediate 3075 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3076 EVT Type = Op.getValueType(); 3077 int64_t Val = C->getSExtValue(); 3078 if ((isInt<15>(Val))) { 3079 Result = DAG.getTargetConstant(Val, Type); 3080 break; 3081 } 3082 } 3083 return; 3084 case 'P': // immediate in the range of 1 to 65535 (inclusive) 3085 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3086 EVT Type = Op.getValueType(); 3087 int64_t Val = C->getSExtValue(); 3088 if ((Val <= 65535) && (Val >= 1)) { 3089 Result = DAG.getTargetConstant(Val, Type); 3090 break; 3091 } 3092 } 3093 return; 3094 } 3095 3096 if (Result.getNode()) { 3097 Ops.push_back(Result); 3098 return; 3099 } 3100 3101 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 3102} 3103 3104bool 3105MipsTargetLowering::isLegalAddressingMode(const AddrMode &AM, Type *Ty) const { 3106 // No global is ever allowed as a base. 3107 if (AM.BaseGV) 3108 return false; 3109 3110 switch (AM.Scale) { 3111 case 0: // "r+i" or just "i", depending on HasBaseReg. 3112 break; 3113 case 1: 3114 if (!AM.HasBaseReg) // allow "r+i". 3115 break; 3116 return false; // disallow "r+r" or "r+r+i". 3117 default: 3118 return false; 3119 } 3120 3121 return true; 3122} 3123 3124bool 3125MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 3126 // The Mips target isn't yet aware of offsets. 3127 return false; 3128} 3129 3130EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 3131 unsigned SrcAlign, 3132 bool IsMemset, bool ZeroMemset, 3133 bool MemcpyStrSrc, 3134 MachineFunction &MF) const { 3135 if (Subtarget->hasMips64()) 3136 return MVT::i64; 3137 3138 return MVT::i32; 3139} 3140 3141bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3142 if (VT != MVT::f32 && VT != MVT::f64) 3143 return false; 3144 if (Imm.isNegZero()) 3145 return false; 3146 return Imm.isZero(); 3147} 3148 3149unsigned MipsTargetLowering::getJumpTableEncoding() const { 3150 if (IsN64) 3151 return MachineJumpTableInfo::EK_GPRel64BlockAddress; 3152 3153 return TargetLowering::getJumpTableEncoding(); 3154} 3155 3156/// This function returns true if CallSym is a long double emulation routine. 3157static bool isF128SoftLibCall(const char *CallSym) { 3158 const char *const LibCalls[] = 3159 {"__addtf3", "__divtf3", "__eqtf2", "__extenddftf2", "__extendsftf2", 3160 "__fixtfdi", "__fixtfsi", "__fixtfti", "__fixunstfdi", "__fixunstfsi", 3161 "__fixunstfti", "__floatditf", "__floatsitf", "__floattitf", 3162 "__floatunditf", "__floatunsitf", "__floatuntitf", "__getf2", "__gttf2", 3163 "__letf2", "__lttf2", "__multf3", "__netf2", "__powitf2", "__subtf3", 3164 "__trunctfdf2", "__trunctfsf2", "__unordtf2", 3165 "ceill", "copysignl", "cosl", "exp2l", "expl", "floorl", "fmal", "fmodl", 3166 "log10l", "log2l", "logl", "nearbyintl", "powl", "rintl", "sinl", "sqrtl", 3167 "truncl"}; 3168 3169 const char * const *End = LibCalls + array_lengthof(LibCalls); 3170 3171 // Check that LibCalls is sorted alphabetically. 3172 MipsTargetLowering::LTStr Comp; 3173 3174#ifndef NDEBUG 3175 for (const char * const *I = LibCalls; I < End - 1; ++I) 3176 assert(Comp(*I, *(I + 1))); 3177#endif 3178 3179 return std::binary_search(LibCalls, End, CallSym, Comp); 3180} 3181 3182/// This function returns true if Ty is fp128 or i128 which was originally a 3183/// fp128. 3184static bool originalTypeIsF128(const Type *Ty, const SDNode *CallNode) { 3185 if (Ty->isFP128Ty()) 3186 return true; 3187 3188 const ExternalSymbolSDNode *ES = 3189 dyn_cast_or_null<const ExternalSymbolSDNode>(CallNode); 3190 3191 // If the Ty is i128 and the function being called is a long double emulation 3192 // routine, then the original type is f128. 3193 return (ES && Ty->isIntegerTy(128) && isF128SoftLibCall(ES->getSymbol())); 3194} 3195 3196MipsTargetLowering::MipsCC::SpecialCallingConvType 3197 MipsTargetLowering::getSpecialCallingConv(SDValue Callee) const { 3198 MipsCC::SpecialCallingConvType SpecialCallingConv = 3199 MipsCC::NoSpecialCallingConv;; 3200 if (Subtarget->inMips16HardFloat()) { 3201 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 3202 llvm::StringRef Sym = G->getGlobal()->getName(); 3203 Function *F = G->getGlobal()->getParent()->getFunction(Sym); 3204 if (F->hasFnAttribute("__Mips16RetHelper")) { 3205 SpecialCallingConv = MipsCC::Mips16RetHelperConv; 3206 } 3207 } 3208 } 3209 return SpecialCallingConv; 3210} 3211 3212MipsTargetLowering::MipsCC::MipsCC( 3213 CallingConv::ID CC, bool IsO32_, bool IsFP64_, CCState &Info, 3214 MipsCC::SpecialCallingConvType SpecialCallingConv_) 3215 : CCInfo(Info), CallConv(CC), IsO32(IsO32_), IsFP64(IsFP64_), 3216 SpecialCallingConv(SpecialCallingConv_){ 3217 // Pre-allocate reserved argument area. 3218 CCInfo.AllocateStack(reservedArgArea(), 1); 3219} 3220 3221 3222void MipsTargetLowering::MipsCC:: 3223analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Args, 3224 bool IsVarArg, bool IsSoftFloat, const SDNode *CallNode, 3225 std::vector<ArgListEntry> &FuncArgs) { 3226 assert((CallConv != CallingConv::Fast || !IsVarArg) && 3227 "CallingConv::Fast shouldn't be used for vararg functions."); 3228 3229 unsigned NumOpnds = Args.size(); 3230 llvm::CCAssignFn *FixedFn = fixedArgFn(), *VarFn = varArgFn(); 3231 3232 for (unsigned I = 0; I != NumOpnds; ++I) { 3233 MVT ArgVT = Args[I].VT; 3234 ISD::ArgFlagsTy ArgFlags = Args[I].Flags; 3235 bool R; 3236 3237 if (ArgFlags.isByVal()) { 3238 handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags); 3239 continue; 3240 } 3241 3242 if (IsVarArg && !Args[I].IsFixed) 3243 R = VarFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo); 3244 else { 3245 MVT RegVT = getRegVT(ArgVT, FuncArgs[Args[I].OrigArgIndex].Ty, CallNode, 3246 IsSoftFloat); 3247 R = FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, CCInfo); 3248 } 3249 3250 if (R) { 3251#ifndef NDEBUG 3252 dbgs() << "Call operand #" << I << " has unhandled type " 3253 << EVT(ArgVT).getEVTString(); 3254#endif 3255 llvm_unreachable(0); 3256 } 3257 } 3258} 3259 3260void MipsTargetLowering::MipsCC:: 3261analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Args, 3262 bool IsSoftFloat, Function::const_arg_iterator FuncArg) { 3263 unsigned NumArgs = Args.size(); 3264 llvm::CCAssignFn *FixedFn = fixedArgFn(); 3265 unsigned CurArgIdx = 0; 3266 3267 for (unsigned I = 0; I != NumArgs; ++I) { 3268 MVT ArgVT = Args[I].VT; 3269 ISD::ArgFlagsTy ArgFlags = Args[I].Flags; 3270 std::advance(FuncArg, Args[I].OrigArgIndex - CurArgIdx); 3271 CurArgIdx = Args[I].OrigArgIndex; 3272 3273 if (ArgFlags.isByVal()) { 3274 handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags); 3275 continue; 3276 } 3277 3278 MVT RegVT = getRegVT(ArgVT, FuncArg->getType(), 0, IsSoftFloat); 3279 3280 if (!FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, CCInfo)) 3281 continue; 3282 3283#ifndef NDEBUG 3284 dbgs() << "Formal Arg #" << I << " has unhandled type " 3285 << EVT(ArgVT).getEVTString(); 3286#endif 3287 llvm_unreachable(0); 3288 } 3289} 3290 3291template<typename Ty> 3292void MipsTargetLowering::MipsCC:: 3293analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat, 3294 const SDNode *CallNode, const Type *RetTy) const { 3295 CCAssignFn *Fn; 3296 3297 if (IsSoftFloat && originalTypeIsF128(RetTy, CallNode)) 3298 Fn = RetCC_F128Soft; 3299 else 3300 Fn = RetCC_Mips; 3301 3302 for (unsigned I = 0, E = RetVals.size(); I < E; ++I) { 3303 MVT VT = RetVals[I].VT; 3304 ISD::ArgFlagsTy Flags = RetVals[I].Flags; 3305 MVT RegVT = this->getRegVT(VT, RetTy, CallNode, IsSoftFloat); 3306 3307 if (Fn(I, VT, RegVT, CCValAssign::Full, Flags, this->CCInfo)) { 3308#ifndef NDEBUG 3309 dbgs() << "Call result #" << I << " has unhandled type " 3310 << EVT(VT).getEVTString() << '\n'; 3311#endif 3312 llvm_unreachable(0); 3313 } 3314 } 3315} 3316 3317void MipsTargetLowering::MipsCC:: 3318analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, bool IsSoftFloat, 3319 const SDNode *CallNode, const Type *RetTy) const { 3320 analyzeReturn(Ins, IsSoftFloat, CallNode, RetTy); 3321} 3322 3323void MipsTargetLowering::MipsCC:: 3324analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsSoftFloat, 3325 const Type *RetTy) const { 3326 analyzeReturn(Outs, IsSoftFloat, 0, RetTy); 3327} 3328 3329void 3330MipsTargetLowering::MipsCC::handleByValArg(unsigned ValNo, MVT ValVT, 3331 MVT LocVT, 3332 CCValAssign::LocInfo LocInfo, 3333 ISD::ArgFlagsTy ArgFlags) { 3334 assert(ArgFlags.getByValSize() && "Byval argument's size shouldn't be 0."); 3335 3336 struct ByValArgInfo ByVal; 3337 unsigned RegSize = regSize(); 3338 unsigned ByValSize = RoundUpToAlignment(ArgFlags.getByValSize(), RegSize); 3339 unsigned Align = std::min(std::max(ArgFlags.getByValAlign(), RegSize), 3340 RegSize * 2); 3341 3342 if (useRegsForByval()) 3343 allocateRegs(ByVal, ByValSize, Align); 3344 3345 // Allocate space on caller's stack. 3346 ByVal.Address = CCInfo.AllocateStack(ByValSize - RegSize * ByVal.NumRegs, 3347 Align); 3348 CCInfo.addLoc(CCValAssign::getMem(ValNo, ValVT, ByVal.Address, LocVT, 3349 LocInfo)); 3350 ByValArgs.push_back(ByVal); 3351} 3352 3353unsigned MipsTargetLowering::MipsCC::numIntArgRegs() const { 3354 return IsO32 ? array_lengthof(O32IntRegs) : array_lengthof(Mips64IntRegs); 3355} 3356 3357unsigned MipsTargetLowering::MipsCC::reservedArgArea() const { 3358 return (IsO32 && (CallConv != CallingConv::Fast)) ? 16 : 0; 3359} 3360 3361const uint16_t *MipsTargetLowering::MipsCC::intArgRegs() const { 3362 return IsO32 ? O32IntRegs : Mips64IntRegs; 3363} 3364 3365llvm::CCAssignFn *MipsTargetLowering::MipsCC::fixedArgFn() const { 3366 if (CallConv == CallingConv::Fast) 3367 return CC_Mips_FastCC; 3368 3369 if (SpecialCallingConv == Mips16RetHelperConv) 3370 return CC_Mips16RetHelper; 3371 return IsO32 ? (IsFP64 ? CC_MipsO32_FP64 : CC_MipsO32_FP32) : CC_MipsN; 3372} 3373 3374llvm::CCAssignFn *MipsTargetLowering::MipsCC::varArgFn() const { 3375 return IsO32 ? (IsFP64 ? CC_MipsO32_FP64 : CC_MipsO32_FP32) : CC_MipsN_VarArg; 3376} 3377 3378const uint16_t *MipsTargetLowering::MipsCC::shadowRegs() const { 3379 return IsO32 ? O32IntRegs : Mips64DPRegs; 3380} 3381 3382void MipsTargetLowering::MipsCC::allocateRegs(ByValArgInfo &ByVal, 3383 unsigned ByValSize, 3384 unsigned Align) { 3385 unsigned RegSize = regSize(), NumIntArgRegs = numIntArgRegs(); 3386 const uint16_t *IntArgRegs = intArgRegs(), *ShadowRegs = shadowRegs(); 3387 assert(!(ByValSize % RegSize) && !(Align % RegSize) && 3388 "Byval argument's size and alignment should be a multiple of" 3389 "RegSize."); 3390 3391 ByVal.FirstIdx = CCInfo.getFirstUnallocated(IntArgRegs, NumIntArgRegs); 3392 3393 // If Align > RegSize, the first arg register must be even. 3394 if ((Align > RegSize) && (ByVal.FirstIdx % 2)) { 3395 CCInfo.AllocateReg(IntArgRegs[ByVal.FirstIdx], ShadowRegs[ByVal.FirstIdx]); 3396 ++ByVal.FirstIdx; 3397 } 3398 3399 // Mark the registers allocated. 3400 for (unsigned I = ByVal.FirstIdx; ByValSize && (I < NumIntArgRegs); 3401 ByValSize -= RegSize, ++I, ++ByVal.NumRegs) 3402 CCInfo.AllocateReg(IntArgRegs[I], ShadowRegs[I]); 3403} 3404 3405MVT MipsTargetLowering::MipsCC::getRegVT(MVT VT, const Type *OrigTy, 3406 const SDNode *CallNode, 3407 bool IsSoftFloat) const { 3408 if (IsSoftFloat || IsO32) 3409 return VT; 3410 3411 // Check if the original type was fp128. 3412 if (originalTypeIsF128(OrigTy, CallNode)) { 3413 assert(VT == MVT::i64); 3414 return MVT::f64; 3415 } 3416 3417 return VT; 3418} 3419 3420void MipsTargetLowering:: 3421copyByValRegs(SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains, 3422 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags, 3423 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg, 3424 const MipsCC &CC, const ByValArgInfo &ByVal) const { 3425 MachineFunction &MF = DAG.getMachineFunction(); 3426 MachineFrameInfo *MFI = MF.getFrameInfo(); 3427 unsigned RegAreaSize = ByVal.NumRegs * CC.regSize(); 3428 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize); 3429 int FrameObjOffset; 3430 3431 if (RegAreaSize) 3432 FrameObjOffset = (int)CC.reservedArgArea() - 3433 (int)((CC.numIntArgRegs() - ByVal.FirstIdx) * CC.regSize()); 3434 else 3435 FrameObjOffset = ByVal.Address; 3436 3437 // Create frame object. 3438 EVT PtrTy = getPointerTy(); 3439 int FI = MFI->CreateFixedObject(FrameObjSize, FrameObjOffset, true); 3440 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 3441 InVals.push_back(FIN); 3442 3443 if (!ByVal.NumRegs) 3444 return; 3445 3446 // Copy arg registers. 3447 MVT RegTy = MVT::getIntegerVT(CC.regSize() * 8); 3448 const TargetRegisterClass *RC = getRegClassFor(RegTy); 3449 3450 for (unsigned I = 0; I < ByVal.NumRegs; ++I) { 3451 unsigned ArgReg = CC.intArgRegs()[ByVal.FirstIdx + I]; 3452 unsigned VReg = addLiveIn(MF, ArgReg, RC); 3453 unsigned Offset = I * CC.regSize(); 3454 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN, 3455 DAG.getConstant(Offset, PtrTy)); 3456 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy), 3457 StorePtr, MachinePointerInfo(FuncArg, Offset), 3458 false, false, 0); 3459 OutChains.push_back(Store); 3460 } 3461} 3462 3463// Copy byVal arg to registers and stack. 3464void MipsTargetLowering:: 3465passByValArg(SDValue Chain, SDLoc DL, 3466 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 3467 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, 3468 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, 3469 const MipsCC &CC, const ByValArgInfo &ByVal, 3470 const ISD::ArgFlagsTy &Flags, bool isLittle) const { 3471 unsigned ByValSize = Flags.getByValSize(); 3472 unsigned Offset = 0; // Offset in # of bytes from the beginning of struct. 3473 unsigned RegSize = CC.regSize(); 3474 unsigned Alignment = std::min(Flags.getByValAlign(), RegSize); 3475 EVT PtrTy = getPointerTy(), RegTy = MVT::getIntegerVT(RegSize * 8); 3476 3477 if (ByVal.NumRegs) { 3478 const uint16_t *ArgRegs = CC.intArgRegs(); 3479 bool LeftoverBytes = (ByVal.NumRegs * RegSize > ByValSize); 3480 unsigned I = 0; 3481 3482 // Copy words to registers. 3483 for (; I < ByVal.NumRegs - LeftoverBytes; ++I, Offset += RegSize) { 3484 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3485 DAG.getConstant(Offset, PtrTy)); 3486 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr, 3487 MachinePointerInfo(), false, false, false, 3488 Alignment); 3489 MemOpChains.push_back(LoadVal.getValue(1)); 3490 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I]; 3491 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal)); 3492 } 3493 3494 // Return if the struct has been fully copied. 3495 if (ByValSize == Offset) 3496 return; 3497 3498 // Copy the remainder of the byval argument with sub-word loads and shifts. 3499 if (LeftoverBytes) { 3500 assert((ByValSize > Offset) && (ByValSize < Offset + RegSize) && 3501 "Size of the remainder should be smaller than RegSize."); 3502 SDValue Val; 3503 3504 for (unsigned LoadSize = RegSize / 2, TotalSizeLoaded = 0; 3505 Offset < ByValSize; LoadSize /= 2) { 3506 unsigned RemSize = ByValSize - Offset; 3507 3508 if (RemSize < LoadSize) 3509 continue; 3510 3511 // Load subword. 3512 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3513 DAG.getConstant(Offset, PtrTy)); 3514 SDValue LoadVal = 3515 DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, 3516 MachinePointerInfo(), MVT::getIntegerVT(LoadSize * 8), 3517 false, false, Alignment); 3518 MemOpChains.push_back(LoadVal.getValue(1)); 3519 3520 // Shift the loaded value. 3521 unsigned Shamt; 3522 3523 if (isLittle) 3524 Shamt = TotalSizeLoaded; 3525 else 3526 Shamt = (RegSize - (TotalSizeLoaded + LoadSize)) * 8; 3527 3528 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal, 3529 DAG.getConstant(Shamt, MVT::i32)); 3530 3531 if (Val.getNode()) 3532 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift); 3533 else 3534 Val = Shift; 3535 3536 Offset += LoadSize; 3537 TotalSizeLoaded += LoadSize; 3538 Alignment = std::min(Alignment, LoadSize); 3539 } 3540 3541 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I]; 3542 RegsToPass.push_back(std::make_pair(ArgReg, Val)); 3543 return; 3544 } 3545 } 3546 3547 // Copy remainder of byval arg to it with memcpy. 3548 unsigned MemCpySize = ByValSize - Offset; 3549 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3550 DAG.getConstant(Offset, PtrTy)); 3551 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr, 3552 DAG.getIntPtrConstant(ByVal.Address)); 3553 Chain = DAG.getMemcpy(Chain, DL, Dst, Src, 3554 DAG.getConstant(MemCpySize, PtrTy), Alignment, 3555 /*isVolatile=*/false, /*AlwaysInline=*/false, 3556 MachinePointerInfo(0), MachinePointerInfo(0)); 3557 MemOpChains.push_back(Chain); 3558} 3559 3560void 3561MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains, 3562 const MipsCC &CC, SDValue Chain, 3563 SDLoc DL, SelectionDAG &DAG) const { 3564 unsigned NumRegs = CC.numIntArgRegs(); 3565 const uint16_t *ArgRegs = CC.intArgRegs(); 3566 const CCState &CCInfo = CC.getCCInfo(); 3567 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumRegs); 3568 unsigned RegSize = CC.regSize(); 3569 MVT RegTy = MVT::getIntegerVT(RegSize * 8); 3570 const TargetRegisterClass *RC = getRegClassFor(RegTy); 3571 MachineFunction &MF = DAG.getMachineFunction(); 3572 MachineFrameInfo *MFI = MF.getFrameInfo(); 3573 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3574 3575 // Offset of the first variable argument from stack pointer. 3576 int VaArgOffset; 3577 3578 if (NumRegs == Idx) 3579 VaArgOffset = RoundUpToAlignment(CCInfo.getNextStackOffset(), RegSize); 3580 else 3581 VaArgOffset = 3582 (int)CC.reservedArgArea() - (int)(RegSize * (NumRegs - Idx)); 3583 3584 // Record the frame index of the first variable argument 3585 // which is a value necessary to VASTART. 3586 int FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true); 3587 MipsFI->setVarArgsFrameIndex(FI); 3588 3589 // Copy the integer registers that have not been used for argument passing 3590 // to the argument register save area. For O32, the save area is allocated 3591 // in the caller's stack frame, while for N32/64, it is allocated in the 3592 // callee's stack frame. 3593 for (unsigned I = Idx; I < NumRegs; ++I, VaArgOffset += RegSize) { 3594 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC); 3595 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy); 3596 FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true); 3597 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy()); 3598 SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff, 3599 MachinePointerInfo(), false, false, 0); 3600 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(0); 3601 OutChains.push_back(Store); 3602 } 3603} 3604