MipsISelLowering.cpp revision 95830221bd4877816adc6707eb34ca68c5a515d2
1//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that Mips uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14#define DEBUG_TYPE "mips-lower" 15#include "MipsISelLowering.h" 16#include "InstPrinter/MipsInstPrinter.h" 17#include "MCTargetDesc/MipsBaseInfo.h" 18#include "MipsMachineFunction.h" 19#include "MipsSubtarget.h" 20#include "MipsTargetMachine.h" 21#include "MipsTargetObjectFile.h" 22#include "llvm/ADT/Statistic.h" 23#include "llvm/CodeGen/CallingConvLower.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineFunction.h" 26#include "llvm/CodeGen/MachineInstrBuilder.h" 27#include "llvm/CodeGen/MachineRegisterInfo.h" 28#include "llvm/CodeGen/SelectionDAGISel.h" 29#include "llvm/CodeGen/ValueTypes.h" 30#include "llvm/IR/CallingConv.h" 31#include "llvm/IR/DerivedTypes.h" 32#include "llvm/IR/GlobalVariable.h" 33#include "llvm/Support/CommandLine.h" 34#include "llvm/Support/Debug.h" 35#include "llvm/Support/ErrorHandling.h" 36#include "llvm/Support/raw_ostream.h" 37#include <cctype> 38 39using namespace llvm; 40 41STATISTIC(NumTailCalls, "Number of tail calls"); 42 43static cl::opt<bool> 44LargeGOT("mxgot", cl::Hidden, 45 cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false)); 46 47static cl::opt<bool> 48NoZeroDivCheck("mno-check-zero-division", cl::Hidden, 49 cl::desc("MIPS: Don't trap on integer division by zero."), 50 cl::init(false)); 51 52static const uint16_t O32IntRegs[4] = { 53 Mips::A0, Mips::A1, Mips::A2, Mips::A3 54}; 55 56static const uint16_t Mips64IntRegs[8] = { 57 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, 58 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64 59}; 60 61static const uint16_t Mips64DPRegs[8] = { 62 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, 63 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64 64}; 65 66// If I is a shifted mask, set the size (Size) and the first bit of the 67// mask (Pos), and return true. 68// For example, if I is 0x003ff800, (Pos, Size) = (11, 11). 69static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { 70 if (!isShiftedMask_64(I)) 71 return false; 72 73 Size = CountPopulation_64(I); 74 Pos = countTrailingZeros(I); 75 return true; 76} 77 78SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const { 79 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>(); 80 return DAG.getRegister(FI->getGlobalBaseReg(), Ty); 81} 82 83SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty, 84 SelectionDAG &DAG, 85 unsigned Flag) const { 86 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag); 87} 88 89SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty, 90 SelectionDAG &DAG, 91 unsigned Flag) const { 92 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag); 93} 94 95SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty, 96 SelectionDAG &DAG, 97 unsigned Flag) const { 98 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag); 99} 100 101SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty, 102 SelectionDAG &DAG, 103 unsigned Flag) const { 104 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag); 105} 106 107SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty, 108 SelectionDAG &DAG, 109 unsigned Flag) const { 110 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(), 111 N->getOffset(), Flag); 112} 113 114const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 115 switch (Opcode) { 116 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 117 case MipsISD::TailCall: return "MipsISD::TailCall"; 118 case MipsISD::Hi: return "MipsISD::Hi"; 119 case MipsISD::Lo: return "MipsISD::Lo"; 120 case MipsISD::GPRel: return "MipsISD::GPRel"; 121 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; 122 case MipsISD::Ret: return "MipsISD::Ret"; 123 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN"; 124 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 125 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 126 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 127 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 128 case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP"; 129 case MipsISD::MFHI: return "MipsISD::MFHI"; 130 case MipsISD::MFLO: return "MipsISD::MFLO"; 131 case MipsISD::MTLOHI: return "MipsISD::MTLOHI"; 132 case MipsISD::Mult: return "MipsISD::Mult"; 133 case MipsISD::Multu: return "MipsISD::Multu"; 134 case MipsISD::MAdd: return "MipsISD::MAdd"; 135 case MipsISD::MAddu: return "MipsISD::MAddu"; 136 case MipsISD::MSub: return "MipsISD::MSub"; 137 case MipsISD::MSubu: return "MipsISD::MSubu"; 138 case MipsISD::DivRem: return "MipsISD::DivRem"; 139 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 140 case MipsISD::DivRem16: return "MipsISD::DivRem16"; 141 case MipsISD::DivRemU16: return "MipsISD::DivRemU16"; 142 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 143 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 144 case MipsISD::Wrapper: return "MipsISD::Wrapper"; 145 case MipsISD::Sync: return "MipsISD::Sync"; 146 case MipsISD::Ext: return "MipsISD::Ext"; 147 case MipsISD::Ins: return "MipsISD::Ins"; 148 case MipsISD::LWL: return "MipsISD::LWL"; 149 case MipsISD::LWR: return "MipsISD::LWR"; 150 case MipsISD::SWL: return "MipsISD::SWL"; 151 case MipsISD::SWR: return "MipsISD::SWR"; 152 case MipsISD::LDL: return "MipsISD::LDL"; 153 case MipsISD::LDR: return "MipsISD::LDR"; 154 case MipsISD::SDL: return "MipsISD::SDL"; 155 case MipsISD::SDR: return "MipsISD::SDR"; 156 case MipsISD::EXTP: return "MipsISD::EXTP"; 157 case MipsISD::EXTPDP: return "MipsISD::EXTPDP"; 158 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H"; 159 case MipsISD::EXTR_W: return "MipsISD::EXTR_W"; 160 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W"; 161 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W"; 162 case MipsISD::SHILO: return "MipsISD::SHILO"; 163 case MipsISD::MTHLIP: return "MipsISD::MTHLIP"; 164 case MipsISD::MULT: return "MipsISD::MULT"; 165 case MipsISD::MULTU: return "MipsISD::MULTU"; 166 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP"; 167 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP"; 168 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP"; 169 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP"; 170 case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP"; 171 case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP"; 172 case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP"; 173 case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP"; 174 case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP"; 175 case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO"; 176 case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO"; 177 case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO"; 178 case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO"; 179 case MipsISD::VCEQ: return "MipsISD::VCEQ"; 180 case MipsISD::VCLE_S: return "MipsISD::VCLE_S"; 181 case MipsISD::VCLE_U: return "MipsISD::VCLE_U"; 182 case MipsISD::VCLT_S: return "MipsISD::VCLT_S"; 183 case MipsISD::VCLT_U: return "MipsISD::VCLT_U"; 184 case MipsISD::VSMAX: return "MipsISD::VSMAX"; 185 case MipsISD::VSMIN: return "MipsISD::VSMIN"; 186 case MipsISD::VUMAX: return "MipsISD::VUMAX"; 187 case MipsISD::VUMIN: return "MipsISD::VUMIN"; 188 case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT"; 189 case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT"; 190 case MipsISD::VNOR: return "MipsISD::VNOR"; 191 case MipsISD::VSHF: return "MipsISD::VSHF"; 192 case MipsISD::SHF: return "MipsISD::SHF"; 193 case MipsISD::ILVEV: return "MipsISD::ILVEV"; 194 case MipsISD::ILVOD: return "MipsISD::ILVOD"; 195 case MipsISD::ILVL: return "MipsISD::ILVL"; 196 case MipsISD::ILVR: return "MipsISD::ILVR"; 197 case MipsISD::PCKEV: return "MipsISD::PCKEV"; 198 case MipsISD::PCKOD: return "MipsISD::PCKOD"; 199 default: return NULL; 200 } 201} 202 203MipsTargetLowering:: 204MipsTargetLowering(MipsTargetMachine &TM) 205 : TargetLowering(TM, new MipsTargetObjectFile()), 206 Subtarget(&TM.getSubtarget<MipsSubtarget>()), 207 HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()), 208 IsO32(Subtarget->isABI_O32()) { 209 // Mips does not have i1 type, so use i32 for 210 // setcc operations results (slt, sgt, ...). 211 setBooleanContents(ZeroOrOneBooleanContent); 212 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 213 214 // Load extented operations for i1 types must be promoted 215 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 216 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 217 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 218 219 // MIPS doesn't have extending float->double load/store 220 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 221 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 222 223 // Used by legalize types to correctly generate the setcc result. 224 // Without this, every float setcc comes with a AND/OR with the result, 225 // we don't want this, since the fpcmp result goes to a flag register, 226 // which is used implicitly by brcond and select operations. 227 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 228 229 // Mips Custom Operations 230 setOperationAction(ISD::BR_JT, MVT::Other, Custom); 231 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 232 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 233 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 234 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 235 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 236 setOperationAction(ISD::SELECT, MVT::f32, Custom); 237 setOperationAction(ISD::SELECT, MVT::f64, Custom); 238 setOperationAction(ISD::SELECT, MVT::i32, Custom); 239 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 240 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 241 setOperationAction(ISD::SETCC, MVT::f32, Custom); 242 setOperationAction(ISD::SETCC, MVT::f64, Custom); 243 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 244 setOperationAction(ISD::VASTART, MVT::Other, Custom); 245 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 246 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 247 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 248 249 if (!TM.Options.NoNaNsFPMath) { 250 setOperationAction(ISD::FABS, MVT::f32, Custom); 251 setOperationAction(ISD::FABS, MVT::f64, Custom); 252 } 253 254 if (HasMips64) { 255 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 256 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 257 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 258 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 259 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 260 setOperationAction(ISD::SELECT, MVT::i64, Custom); 261 setOperationAction(ISD::LOAD, MVT::i64, Custom); 262 setOperationAction(ISD::STORE, MVT::i64, Custom); 263 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 264 } 265 266 if (!HasMips64) { 267 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 268 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 269 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 270 } 271 272 setOperationAction(ISD::ADD, MVT::i32, Custom); 273 if (HasMips64) 274 setOperationAction(ISD::ADD, MVT::i64, Custom); 275 276 setOperationAction(ISD::SDIV, MVT::i32, Expand); 277 setOperationAction(ISD::SREM, MVT::i32, Expand); 278 setOperationAction(ISD::UDIV, MVT::i32, Expand); 279 setOperationAction(ISD::UREM, MVT::i32, Expand); 280 setOperationAction(ISD::SDIV, MVT::i64, Expand); 281 setOperationAction(ISD::SREM, MVT::i64, Expand); 282 setOperationAction(ISD::UDIV, MVT::i64, Expand); 283 setOperationAction(ISD::UREM, MVT::i64, Expand); 284 285 // Operations not directly supported by Mips. 286 setOperationAction(ISD::BR_CC, MVT::f32, Expand); 287 setOperationAction(ISD::BR_CC, MVT::f64, Expand); 288 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 289 setOperationAction(ISD::BR_CC, MVT::i64, Expand); 290 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 291 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 292 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 293 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 294 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 295 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 296 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 297 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 298 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 299 setOperationAction(ISD::CTTZ, MVT::i64, Expand); 300 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 301 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 302 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 303 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 304 setOperationAction(ISD::ROTL, MVT::i32, Expand); 305 setOperationAction(ISD::ROTL, MVT::i64, Expand); 306 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 307 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 308 309 if (!Subtarget->hasMips32r2()) 310 setOperationAction(ISD::ROTR, MVT::i32, Expand); 311 312 if (!Subtarget->hasMips64r2()) 313 setOperationAction(ISD::ROTR, MVT::i64, Expand); 314 315 setOperationAction(ISD::FSIN, MVT::f32, Expand); 316 setOperationAction(ISD::FSIN, MVT::f64, Expand); 317 setOperationAction(ISD::FCOS, MVT::f32, Expand); 318 setOperationAction(ISD::FCOS, MVT::f64, Expand); 319 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 320 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 321 setOperationAction(ISD::FPOWI, MVT::f32, Expand); 322 setOperationAction(ISD::FPOW, MVT::f32, Expand); 323 setOperationAction(ISD::FPOW, MVT::f64, Expand); 324 setOperationAction(ISD::FLOG, MVT::f32, Expand); 325 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 326 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 327 setOperationAction(ISD::FEXP, MVT::f32, Expand); 328 setOperationAction(ISD::FMA, MVT::f32, Expand); 329 setOperationAction(ISD::FMA, MVT::f64, Expand); 330 setOperationAction(ISD::FREM, MVT::f32, Expand); 331 setOperationAction(ISD::FREM, MVT::f64, Expand); 332 333 if (!TM.Options.NoNaNsFPMath) { 334 setOperationAction(ISD::FNEG, MVT::f32, Expand); 335 setOperationAction(ISD::FNEG, MVT::f64, Expand); 336 } 337 338 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); 339 340 setOperationAction(ISD::VAARG, MVT::Other, Expand); 341 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 342 setOperationAction(ISD::VAEND, MVT::Other, Expand); 343 344 // Use the default for now 345 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 346 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 347 348 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); 349 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); 350 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); 351 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); 352 353 setInsertFencesForAtomic(true); 354 355 if (!Subtarget->hasSEInReg()) { 356 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 357 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 358 } 359 360 if (!Subtarget->hasBitCount()) { 361 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 362 setOperationAction(ISD::CTLZ, MVT::i64, Expand); 363 } 364 365 if (!Subtarget->hasSwap()) { 366 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 367 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 368 } 369 370 if (HasMips64) { 371 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom); 372 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom); 373 setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom); 374 setTruncStoreAction(MVT::i64, MVT::i32, Custom); 375 } 376 377 setOperationAction(ISD::TRAP, MVT::Other, Legal); 378 379 setTargetDAGCombine(ISD::SDIVREM); 380 setTargetDAGCombine(ISD::UDIVREM); 381 setTargetDAGCombine(ISD::SELECT); 382 setTargetDAGCombine(ISD::AND); 383 setTargetDAGCombine(ISD::OR); 384 setTargetDAGCombine(ISD::ADD); 385 386 setMinFunctionAlignment(HasMips64 ? 3 : 2); 387 388 setStackPointerRegisterToSaveRestore(IsN64 ? Mips::SP_64 : Mips::SP); 389 390 setExceptionPointerRegister(IsN64 ? Mips::A0_64 : Mips::A0); 391 setExceptionSelectorRegister(IsN64 ? Mips::A1_64 : Mips::A1); 392 393 MaxStoresPerMemcpy = 16; 394} 395 396const MipsTargetLowering *MipsTargetLowering::create(MipsTargetMachine &TM) { 397 if (TM.getSubtargetImpl()->inMips16Mode()) 398 return llvm::createMips16TargetLowering(TM); 399 400 return llvm::createMipsSETargetLowering(TM); 401} 402 403EVT MipsTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const { 404 if (!VT.isVector()) 405 return MVT::i32; 406 return VT.changeVectorElementTypeToInteger(); 407} 408 409static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG, 410 TargetLowering::DAGCombinerInfo &DCI, 411 const MipsSubtarget *Subtarget) { 412 if (DCI.isBeforeLegalizeOps()) 413 return SDValue(); 414 415 EVT Ty = N->getValueType(0); 416 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64; 417 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64; 418 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 : 419 MipsISD::DivRemU16; 420 SDLoc DL(N); 421 422 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue, 423 N->getOperand(0), N->getOperand(1)); 424 SDValue InChain = DAG.getEntryNode(); 425 SDValue InGlue = DivRem; 426 427 // insert MFLO 428 if (N->hasAnyUseOfValue(0)) { 429 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty, 430 InGlue); 431 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 432 InChain = CopyFromLo.getValue(1); 433 InGlue = CopyFromLo.getValue(2); 434 } 435 436 // insert MFHI 437 if (N->hasAnyUseOfValue(1)) { 438 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL, 439 HI, Ty, InGlue); 440 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 441 } 442 443 return SDValue(); 444} 445 446static Mips::CondCode condCodeToFCC(ISD::CondCode CC) { 447 switch (CC) { 448 default: llvm_unreachable("Unknown fp condition code!"); 449 case ISD::SETEQ: 450 case ISD::SETOEQ: return Mips::FCOND_OEQ; 451 case ISD::SETUNE: return Mips::FCOND_UNE; 452 case ISD::SETLT: 453 case ISD::SETOLT: return Mips::FCOND_OLT; 454 case ISD::SETGT: 455 case ISD::SETOGT: return Mips::FCOND_OGT; 456 case ISD::SETLE: 457 case ISD::SETOLE: return Mips::FCOND_OLE; 458 case ISD::SETGE: 459 case ISD::SETOGE: return Mips::FCOND_OGE; 460 case ISD::SETULT: return Mips::FCOND_ULT; 461 case ISD::SETULE: return Mips::FCOND_ULE; 462 case ISD::SETUGT: return Mips::FCOND_UGT; 463 case ISD::SETUGE: return Mips::FCOND_UGE; 464 case ISD::SETUO: return Mips::FCOND_UN; 465 case ISD::SETO: return Mips::FCOND_OR; 466 case ISD::SETNE: 467 case ISD::SETONE: return Mips::FCOND_ONE; 468 case ISD::SETUEQ: return Mips::FCOND_UEQ; 469 } 470} 471 472 473/// This function returns true if the floating point conditional branches and 474/// conditional moves which use condition code CC should be inverted. 475static bool invertFPCondCodeUser(Mips::CondCode CC) { 476 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 477 return false; 478 479 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 480 "Illegal Condition Code"); 481 482 return true; 483} 484 485// Creates and returns an FPCmp node from a setcc node. 486// Returns Op if setcc is not a floating point comparison. 487static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) { 488 // must be a SETCC node 489 if (Op.getOpcode() != ISD::SETCC) 490 return Op; 491 492 SDValue LHS = Op.getOperand(0); 493 494 if (!LHS.getValueType().isFloatingPoint()) 495 return Op; 496 497 SDValue RHS = Op.getOperand(1); 498 SDLoc DL(Op); 499 500 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 501 // node if necessary. 502 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 503 504 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS, 505 DAG.getConstant(condCodeToFCC(CC), MVT::i32)); 506} 507 508// Creates and returns a CMovFPT/F node. 509static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, 510 SDValue False, SDLoc DL) { 511 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2)); 512 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue()); 513 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 514 515 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 516 True.getValueType(), True, FCC0, False, Cond); 517} 518 519static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, 520 TargetLowering::DAGCombinerInfo &DCI, 521 const MipsSubtarget *Subtarget) { 522 if (DCI.isBeforeLegalizeOps()) 523 return SDValue(); 524 525 SDValue SetCC = N->getOperand(0); 526 527 if ((SetCC.getOpcode() != ISD::SETCC) || 528 !SetCC.getOperand(0).getValueType().isInteger()) 529 return SDValue(); 530 531 SDValue False = N->getOperand(2); 532 EVT FalseTy = False.getValueType(); 533 534 if (!FalseTy.isInteger()) 535 return SDValue(); 536 537 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(False); 538 539 if (!CN || CN->getZExtValue()) 540 return SDValue(); 541 542 const SDLoc DL(N); 543 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 544 SDValue True = N->getOperand(1); 545 546 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 547 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 548 549 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); 550} 551 552static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, 553 TargetLowering::DAGCombinerInfo &DCI, 554 const MipsSubtarget *Subtarget) { 555 // Pattern match EXT. 556 // $dst = and ((sra or srl) $src , pos), (2**size - 1) 557 // => ext $dst, $src, size, pos 558 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasExtractInsert()) 559 return SDValue(); 560 561 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1); 562 unsigned ShiftRightOpc = ShiftRight.getOpcode(); 563 564 // Op's first operand must be a shift right. 565 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL) 566 return SDValue(); 567 568 // The second operand of the shift must be an immediate. 569 ConstantSDNode *CN; 570 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1)))) 571 return SDValue(); 572 573 uint64_t Pos = CN->getZExtValue(); 574 uint64_t SMPos, SMSize; 575 576 // Op's second operand must be a shifted mask. 577 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) || 578 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 579 return SDValue(); 580 581 // Return if the shifted mask does not start at bit 0 or the sum of its size 582 // and Pos exceeds the word's size. 583 EVT ValTy = N->getValueType(0); 584 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits()) 585 return SDValue(); 586 587 return DAG.getNode(MipsISD::Ext, SDLoc(N), ValTy, 588 ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32), 589 DAG.getConstant(SMSize, MVT::i32)); 590} 591 592static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, 593 TargetLowering::DAGCombinerInfo &DCI, 594 const MipsSubtarget *Subtarget) { 595 // Pattern match INS. 596 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), 597 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 598 // => ins $dst, $src, size, pos, $src1 599 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasExtractInsert()) 600 return SDValue(); 601 602 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); 603 uint64_t SMPos0, SMSize0, SMPos1, SMSize1; 604 ConstantSDNode *CN; 605 606 // See if Op's first operand matches (and $src1 , mask0). 607 if (And0.getOpcode() != ISD::AND) 608 return SDValue(); 609 610 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) || 611 !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0)) 612 return SDValue(); 613 614 // See if Op's second operand matches (and (shl $src, pos), mask1). 615 if (And1.getOpcode() != ISD::AND) 616 return SDValue(); 617 618 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || 619 !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1)) 620 return SDValue(); 621 622 // The shift masks must have the same position and size. 623 if (SMPos0 != SMPos1 || SMSize0 != SMSize1) 624 return SDValue(); 625 626 SDValue Shl = And1.getOperand(0); 627 if (Shl.getOpcode() != ISD::SHL) 628 return SDValue(); 629 630 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1)))) 631 return SDValue(); 632 633 unsigned Shamt = CN->getZExtValue(); 634 635 // Return if the shift amount and the first bit position of mask are not the 636 // same. 637 EVT ValTy = N->getValueType(0); 638 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits())) 639 return SDValue(); 640 641 return DAG.getNode(MipsISD::Ins, SDLoc(N), ValTy, Shl.getOperand(0), 642 DAG.getConstant(SMPos0, MVT::i32), 643 DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0)); 644} 645 646static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG, 647 TargetLowering::DAGCombinerInfo &DCI, 648 const MipsSubtarget *Subtarget) { 649 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) 650 651 if (DCI.isBeforeLegalizeOps()) 652 return SDValue(); 653 654 SDValue Add = N->getOperand(1); 655 656 if (Add.getOpcode() != ISD::ADD) 657 return SDValue(); 658 659 SDValue Lo = Add.getOperand(1); 660 661 if ((Lo.getOpcode() != MipsISD::Lo) || 662 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable)) 663 return SDValue(); 664 665 EVT ValTy = N->getValueType(0); 666 SDLoc DL(N); 667 668 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0), 669 Add.getOperand(0)); 670 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo); 671} 672 673SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 674 const { 675 SelectionDAG &DAG = DCI.DAG; 676 unsigned Opc = N->getOpcode(); 677 678 switch (Opc) { 679 default: break; 680 case ISD::SDIVREM: 681 case ISD::UDIVREM: 682 return performDivRemCombine(N, DAG, DCI, Subtarget); 683 case ISD::SELECT: 684 return performSELECTCombine(N, DAG, DCI, Subtarget); 685 case ISD::AND: 686 return performANDCombine(N, DAG, DCI, Subtarget); 687 case ISD::OR: 688 return performORCombine(N, DAG, DCI, Subtarget); 689 case ISD::ADD: 690 return performADDCombine(N, DAG, DCI, Subtarget); 691 } 692 693 return SDValue(); 694} 695 696void 697MipsTargetLowering::LowerOperationWrapper(SDNode *N, 698 SmallVectorImpl<SDValue> &Results, 699 SelectionDAG &DAG) const { 700 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 701 702 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I) 703 Results.push_back(Res.getValue(I)); 704} 705 706void 707MipsTargetLowering::ReplaceNodeResults(SDNode *N, 708 SmallVectorImpl<SDValue> &Results, 709 SelectionDAG &DAG) const { 710 return LowerOperationWrapper(N, Results, DAG); 711} 712 713SDValue MipsTargetLowering:: 714LowerOperation(SDValue Op, SelectionDAG &DAG) const 715{ 716 switch (Op.getOpcode()) 717 { 718 case ISD::BR_JT: return lowerBR_JT(Op, DAG); 719 case ISD::BRCOND: return lowerBRCOND(Op, DAG); 720 case ISD::ConstantPool: return lowerConstantPool(Op, DAG); 721 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG); 722 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG); 723 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG); 724 case ISD::JumpTable: return lowerJumpTable(Op, DAG); 725 case ISD::SELECT: return lowerSELECT(Op, DAG); 726 case ISD::SELECT_CC: return lowerSELECT_CC(Op, DAG); 727 case ISD::SETCC: return lowerSETCC(Op, DAG); 728 case ISD::VASTART: return lowerVASTART(Op, DAG); 729 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG); 730 case ISD::FABS: return lowerFABS(Op, DAG); 731 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG); 732 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG); 733 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG); 734 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG); 735 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG); 736 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true); 737 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false); 738 case ISD::LOAD: return lowerLOAD(Op, DAG); 739 case ISD::STORE: return lowerSTORE(Op, DAG); 740 case ISD::ADD: return lowerADD(Op, DAG); 741 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG); 742 } 743 return SDValue(); 744} 745 746//===----------------------------------------------------------------------===// 747// Lower helper functions 748//===----------------------------------------------------------------------===// 749 750// addLiveIn - This helper function adds the specified physical register to the 751// MachineFunction as a live in value. It also creates a corresponding 752// virtual register for it. 753static unsigned 754addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) 755{ 756 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 757 MF.getRegInfo().addLiveIn(PReg, VReg); 758 return VReg; 759} 760 761static MachineBasicBlock *expandPseudoDIV(MachineInstr *MI, 762 MachineBasicBlock &MBB, 763 const TargetInstrInfo &TII, 764 bool Is64Bit) { 765 if (NoZeroDivCheck) 766 return &MBB; 767 768 // Insert instruction "teq $divisor_reg, $zero, 7". 769 MachineBasicBlock::iterator I(MI); 770 MachineInstrBuilder MIB; 771 MachineOperand &Divisor = MI->getOperand(2); 772 MIB = BuildMI(MBB, llvm::next(I), MI->getDebugLoc(), TII.get(Mips::TEQ)) 773 .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill())) 774 .addReg(Mips::ZERO).addImm(7); 775 776 // Use the 32-bit sub-register if this is a 64-bit division. 777 if (Is64Bit) 778 MIB->getOperand(0).setSubReg(Mips::sub_32); 779 780 // Clear Divisor's kill flag. 781 Divisor.setIsKill(false); 782 return &MBB; 783} 784 785MachineBasicBlock * 786MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 787 MachineBasicBlock *BB) const { 788 switch (MI->getOpcode()) { 789 default: 790 llvm_unreachable("Unexpected instr type to insert"); 791 case Mips::ATOMIC_LOAD_ADD_I8: 792 return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu); 793 case Mips::ATOMIC_LOAD_ADD_I16: 794 return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu); 795 case Mips::ATOMIC_LOAD_ADD_I32: 796 return emitAtomicBinary(MI, BB, 4, Mips::ADDu); 797 case Mips::ATOMIC_LOAD_ADD_I64: 798 return emitAtomicBinary(MI, BB, 8, Mips::DADDu); 799 800 case Mips::ATOMIC_LOAD_AND_I8: 801 return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND); 802 case Mips::ATOMIC_LOAD_AND_I16: 803 return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND); 804 case Mips::ATOMIC_LOAD_AND_I32: 805 return emitAtomicBinary(MI, BB, 4, Mips::AND); 806 case Mips::ATOMIC_LOAD_AND_I64: 807 return emitAtomicBinary(MI, BB, 8, Mips::AND64); 808 809 case Mips::ATOMIC_LOAD_OR_I8: 810 return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR); 811 case Mips::ATOMIC_LOAD_OR_I16: 812 return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR); 813 case Mips::ATOMIC_LOAD_OR_I32: 814 return emitAtomicBinary(MI, BB, 4, Mips::OR); 815 case Mips::ATOMIC_LOAD_OR_I64: 816 return emitAtomicBinary(MI, BB, 8, Mips::OR64); 817 818 case Mips::ATOMIC_LOAD_XOR_I8: 819 return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR); 820 case Mips::ATOMIC_LOAD_XOR_I16: 821 return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR); 822 case Mips::ATOMIC_LOAD_XOR_I32: 823 return emitAtomicBinary(MI, BB, 4, Mips::XOR); 824 case Mips::ATOMIC_LOAD_XOR_I64: 825 return emitAtomicBinary(MI, BB, 8, Mips::XOR64); 826 827 case Mips::ATOMIC_LOAD_NAND_I8: 828 return emitAtomicBinaryPartword(MI, BB, 1, 0, true); 829 case Mips::ATOMIC_LOAD_NAND_I16: 830 return emitAtomicBinaryPartword(MI, BB, 2, 0, true); 831 case Mips::ATOMIC_LOAD_NAND_I32: 832 return emitAtomicBinary(MI, BB, 4, 0, true); 833 case Mips::ATOMIC_LOAD_NAND_I64: 834 return emitAtomicBinary(MI, BB, 8, 0, true); 835 836 case Mips::ATOMIC_LOAD_SUB_I8: 837 return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu); 838 case Mips::ATOMIC_LOAD_SUB_I16: 839 return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu); 840 case Mips::ATOMIC_LOAD_SUB_I32: 841 return emitAtomicBinary(MI, BB, 4, Mips::SUBu); 842 case Mips::ATOMIC_LOAD_SUB_I64: 843 return emitAtomicBinary(MI, BB, 8, Mips::DSUBu); 844 845 case Mips::ATOMIC_SWAP_I8: 846 return emitAtomicBinaryPartword(MI, BB, 1, 0); 847 case Mips::ATOMIC_SWAP_I16: 848 return emitAtomicBinaryPartword(MI, BB, 2, 0); 849 case Mips::ATOMIC_SWAP_I32: 850 return emitAtomicBinary(MI, BB, 4, 0); 851 case Mips::ATOMIC_SWAP_I64: 852 return emitAtomicBinary(MI, BB, 8, 0); 853 854 case Mips::ATOMIC_CMP_SWAP_I8: 855 return emitAtomicCmpSwapPartword(MI, BB, 1); 856 case Mips::ATOMIC_CMP_SWAP_I16: 857 return emitAtomicCmpSwapPartword(MI, BB, 2); 858 case Mips::ATOMIC_CMP_SWAP_I32: 859 return emitAtomicCmpSwap(MI, BB, 4); 860 case Mips::ATOMIC_CMP_SWAP_I64: 861 return emitAtomicCmpSwap(MI, BB, 8); 862 case Mips::PseudoSDIV: 863 case Mips::PseudoUDIV: 864 return expandPseudoDIV(MI, *BB, *getTargetMachine().getInstrInfo(), false); 865 case Mips::PseudoDSDIV: 866 case Mips::PseudoDUDIV: 867 return expandPseudoDIV(MI, *BB, *getTargetMachine().getInstrInfo(), true); 868 } 869} 870 871// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 872// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 873MachineBasicBlock * 874MipsTargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 875 unsigned Size, unsigned BinOpcode, 876 bool Nand) const { 877 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary."); 878 879 MachineFunction *MF = BB->getParent(); 880 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 881 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 882 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 883 DebugLoc DL = MI->getDebugLoc(); 884 unsigned LL, SC, AND, NOR, ZERO, BEQ; 885 886 if (Size == 4) { 887 LL = Mips::LL; 888 SC = Mips::SC; 889 AND = Mips::AND; 890 NOR = Mips::NOR; 891 ZERO = Mips::ZERO; 892 BEQ = Mips::BEQ; 893 } 894 else { 895 LL = Mips::LLD; 896 SC = Mips::SCD; 897 AND = Mips::AND64; 898 NOR = Mips::NOR64; 899 ZERO = Mips::ZERO_64; 900 BEQ = Mips::BEQ64; 901 } 902 903 unsigned OldVal = MI->getOperand(0).getReg(); 904 unsigned Ptr = MI->getOperand(1).getReg(); 905 unsigned Incr = MI->getOperand(2).getReg(); 906 907 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 908 unsigned AndRes = RegInfo.createVirtualRegister(RC); 909 unsigned Success = RegInfo.createVirtualRegister(RC); 910 911 // insert new blocks after the current block 912 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 913 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 914 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 915 MachineFunction::iterator It = BB; 916 ++It; 917 MF->insert(It, loopMBB); 918 MF->insert(It, exitMBB); 919 920 // Transfer the remainder of BB and its successor edges to exitMBB. 921 exitMBB->splice(exitMBB->begin(), BB, 922 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 923 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 924 925 // thisMBB: 926 // ... 927 // fallthrough --> loopMBB 928 BB->addSuccessor(loopMBB); 929 loopMBB->addSuccessor(loopMBB); 930 loopMBB->addSuccessor(exitMBB); 931 932 // loopMBB: 933 // ll oldval, 0(ptr) 934 // <binop> storeval, oldval, incr 935 // sc success, storeval, 0(ptr) 936 // beq success, $0, loopMBB 937 BB = loopMBB; 938 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0); 939 if (Nand) { 940 // and andres, oldval, incr 941 // nor storeval, $0, andres 942 BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr); 943 BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes); 944 } else if (BinOpcode) { 945 // <binop> storeval, oldval, incr 946 BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr); 947 } else { 948 StoreVal = Incr; 949 } 950 BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0); 951 BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB); 952 953 MI->eraseFromParent(); // The instruction is gone now. 954 955 return exitMBB; 956} 957 958MachineBasicBlock * 959MipsTargetLowering::emitAtomicBinaryPartword(MachineInstr *MI, 960 MachineBasicBlock *BB, 961 unsigned Size, unsigned BinOpcode, 962 bool Nand) const { 963 assert((Size == 1 || Size == 2) && 964 "Unsupported size for EmitAtomicBinaryPartial."); 965 966 MachineFunction *MF = BB->getParent(); 967 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 968 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 969 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 970 DebugLoc DL = MI->getDebugLoc(); 971 972 unsigned Dest = MI->getOperand(0).getReg(); 973 unsigned Ptr = MI->getOperand(1).getReg(); 974 unsigned Incr = MI->getOperand(2).getReg(); 975 976 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 977 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 978 unsigned Mask = RegInfo.createVirtualRegister(RC); 979 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 980 unsigned NewVal = RegInfo.createVirtualRegister(RC); 981 unsigned OldVal = RegInfo.createVirtualRegister(RC); 982 unsigned Incr2 = RegInfo.createVirtualRegister(RC); 983 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 984 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 985 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 986 unsigned AndRes = RegInfo.createVirtualRegister(RC); 987 unsigned BinOpRes = RegInfo.createVirtualRegister(RC); 988 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 989 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 990 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 991 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 992 unsigned SllRes = RegInfo.createVirtualRegister(RC); 993 unsigned Success = RegInfo.createVirtualRegister(RC); 994 995 // insert new blocks after the current block 996 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 997 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 998 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 999 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1000 MachineFunction::iterator It = BB; 1001 ++It; 1002 MF->insert(It, loopMBB); 1003 MF->insert(It, sinkMBB); 1004 MF->insert(It, exitMBB); 1005 1006 // Transfer the remainder of BB and its successor edges to exitMBB. 1007 exitMBB->splice(exitMBB->begin(), BB, 1008 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1009 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1010 1011 BB->addSuccessor(loopMBB); 1012 loopMBB->addSuccessor(loopMBB); 1013 loopMBB->addSuccessor(sinkMBB); 1014 sinkMBB->addSuccessor(exitMBB); 1015 1016 // thisMBB: 1017 // addiu masklsb2,$0,-4 # 0xfffffffc 1018 // and alignedaddr,ptr,masklsb2 1019 // andi ptrlsb2,ptr,3 1020 // sll shiftamt,ptrlsb2,3 1021 // ori maskupper,$0,255 # 0xff 1022 // sll mask,maskupper,shiftamt 1023 // nor mask2,$0,mask 1024 // sll incr2,incr,shiftamt 1025 1026 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1027 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2) 1028 .addReg(Mips::ZERO).addImm(-4); 1029 BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr) 1030 .addReg(Ptr).addReg(MaskLSB2); 1031 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1032 if (Subtarget->isLittle()) { 1033 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1034 } else { 1035 unsigned Off = RegInfo.createVirtualRegister(RC); 1036 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1037 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1038 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1039 } 1040 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1041 .addReg(Mips::ZERO).addImm(MaskImm); 1042 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1043 .addReg(MaskUpper).addReg(ShiftAmt); 1044 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1045 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt); 1046 1047 // atomic.load.binop 1048 // loopMBB: 1049 // ll oldval,0(alignedaddr) 1050 // binop binopres,oldval,incr2 1051 // and newval,binopres,mask 1052 // and maskedoldval0,oldval,mask2 1053 // or storeval,maskedoldval0,newval 1054 // sc success,storeval,0(alignedaddr) 1055 // beq success,$0,loopMBB 1056 1057 // atomic.swap 1058 // loopMBB: 1059 // ll oldval,0(alignedaddr) 1060 // and newval,incr2,mask 1061 // and maskedoldval0,oldval,mask2 1062 // or storeval,maskedoldval0,newval 1063 // sc success,storeval,0(alignedaddr) 1064 // beq success,$0,loopMBB 1065 1066 BB = loopMBB; 1067 BuildMI(BB, DL, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0); 1068 if (Nand) { 1069 // and andres, oldval, incr2 1070 // nor binopres, $0, andres 1071 // and newval, binopres, mask 1072 BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2); 1073 BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes) 1074 .addReg(Mips::ZERO).addReg(AndRes); 1075 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1076 } else if (BinOpcode) { 1077 // <binop> binopres, oldval, incr2 1078 // and newval, binopres, mask 1079 BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2); 1080 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1081 } else { // atomic.swap 1082 // and newval, incr2, mask 1083 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask); 1084 } 1085 1086 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0) 1087 .addReg(OldVal).addReg(Mask2); 1088 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal) 1089 .addReg(MaskedOldVal0).addReg(NewVal); 1090 BuildMI(BB, DL, TII->get(Mips::SC), Success) 1091 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1092 BuildMI(BB, DL, TII->get(Mips::BEQ)) 1093 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB); 1094 1095 // sinkMBB: 1096 // and maskedoldval1,oldval,mask 1097 // srl srlres,maskedoldval1,shiftamt 1098 // sll sllres,srlres,24 1099 // sra dest,sllres,24 1100 BB = sinkMBB; 1101 int64_t ShiftImm = (Size == 1) ? 24 : 16; 1102 1103 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1) 1104 .addReg(OldVal).addReg(Mask); 1105 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes) 1106 .addReg(MaskedOldVal1).addReg(ShiftAmt); 1107 BuildMI(BB, DL, TII->get(Mips::SLL), SllRes) 1108 .addReg(SrlRes).addImm(ShiftImm); 1109 BuildMI(BB, DL, TII->get(Mips::SRA), Dest) 1110 .addReg(SllRes).addImm(ShiftImm); 1111 1112 MI->eraseFromParent(); // The instruction is gone now. 1113 1114 return exitMBB; 1115} 1116 1117MachineBasicBlock * MipsTargetLowering::emitAtomicCmpSwap(MachineInstr *MI, 1118 MachineBasicBlock *BB, 1119 unsigned Size) const { 1120 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap."); 1121 1122 MachineFunction *MF = BB->getParent(); 1123 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1124 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1125 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1126 DebugLoc DL = MI->getDebugLoc(); 1127 unsigned LL, SC, ZERO, BNE, BEQ; 1128 1129 if (Size == 4) { 1130 LL = Mips::LL; 1131 SC = Mips::SC; 1132 ZERO = Mips::ZERO; 1133 BNE = Mips::BNE; 1134 BEQ = Mips::BEQ; 1135 } else { 1136 LL = Mips::LLD; 1137 SC = Mips::SCD; 1138 ZERO = Mips::ZERO_64; 1139 BNE = Mips::BNE64; 1140 BEQ = Mips::BEQ64; 1141 } 1142 1143 unsigned Dest = MI->getOperand(0).getReg(); 1144 unsigned Ptr = MI->getOperand(1).getReg(); 1145 unsigned OldVal = MI->getOperand(2).getReg(); 1146 unsigned NewVal = MI->getOperand(3).getReg(); 1147 1148 unsigned Success = RegInfo.createVirtualRegister(RC); 1149 1150 // insert new blocks after the current block 1151 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1152 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1153 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1154 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1155 MachineFunction::iterator It = BB; 1156 ++It; 1157 MF->insert(It, loop1MBB); 1158 MF->insert(It, loop2MBB); 1159 MF->insert(It, exitMBB); 1160 1161 // Transfer the remainder of BB and its successor edges to exitMBB. 1162 exitMBB->splice(exitMBB->begin(), BB, 1163 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1164 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1165 1166 // thisMBB: 1167 // ... 1168 // fallthrough --> loop1MBB 1169 BB->addSuccessor(loop1MBB); 1170 loop1MBB->addSuccessor(exitMBB); 1171 loop1MBB->addSuccessor(loop2MBB); 1172 loop2MBB->addSuccessor(loop1MBB); 1173 loop2MBB->addSuccessor(exitMBB); 1174 1175 // loop1MBB: 1176 // ll dest, 0(ptr) 1177 // bne dest, oldval, exitMBB 1178 BB = loop1MBB; 1179 BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0); 1180 BuildMI(BB, DL, TII->get(BNE)) 1181 .addReg(Dest).addReg(OldVal).addMBB(exitMBB); 1182 1183 // loop2MBB: 1184 // sc success, newval, 0(ptr) 1185 // beq success, $0, loop1MBB 1186 BB = loop2MBB; 1187 BuildMI(BB, DL, TII->get(SC), Success) 1188 .addReg(NewVal).addReg(Ptr).addImm(0); 1189 BuildMI(BB, DL, TII->get(BEQ)) 1190 .addReg(Success).addReg(ZERO).addMBB(loop1MBB); 1191 1192 MI->eraseFromParent(); // The instruction is gone now. 1193 1194 return exitMBB; 1195} 1196 1197MachineBasicBlock * 1198MipsTargetLowering::emitAtomicCmpSwapPartword(MachineInstr *MI, 1199 MachineBasicBlock *BB, 1200 unsigned Size) const { 1201 assert((Size == 1 || Size == 2) && 1202 "Unsupported size for EmitAtomicCmpSwapPartial."); 1203 1204 MachineFunction *MF = BB->getParent(); 1205 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1206 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1207 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1208 DebugLoc DL = MI->getDebugLoc(); 1209 1210 unsigned Dest = MI->getOperand(0).getReg(); 1211 unsigned Ptr = MI->getOperand(1).getReg(); 1212 unsigned CmpVal = MI->getOperand(2).getReg(); 1213 unsigned NewVal = MI->getOperand(3).getReg(); 1214 1215 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 1216 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1217 unsigned Mask = RegInfo.createVirtualRegister(RC); 1218 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1219 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC); 1220 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1221 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1222 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC); 1223 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 1224 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1225 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1226 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC); 1227 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC); 1228 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1229 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1230 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1231 unsigned SllRes = RegInfo.createVirtualRegister(RC); 1232 unsigned Success = RegInfo.createVirtualRegister(RC); 1233 1234 // insert new blocks after the current block 1235 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1236 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1237 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1238 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1239 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1240 MachineFunction::iterator It = BB; 1241 ++It; 1242 MF->insert(It, loop1MBB); 1243 MF->insert(It, loop2MBB); 1244 MF->insert(It, sinkMBB); 1245 MF->insert(It, exitMBB); 1246 1247 // Transfer the remainder of BB and its successor edges to exitMBB. 1248 exitMBB->splice(exitMBB->begin(), BB, 1249 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1250 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1251 1252 BB->addSuccessor(loop1MBB); 1253 loop1MBB->addSuccessor(sinkMBB); 1254 loop1MBB->addSuccessor(loop2MBB); 1255 loop2MBB->addSuccessor(loop1MBB); 1256 loop2MBB->addSuccessor(sinkMBB); 1257 sinkMBB->addSuccessor(exitMBB); 1258 1259 // FIXME: computation of newval2 can be moved to loop2MBB. 1260 // thisMBB: 1261 // addiu masklsb2,$0,-4 # 0xfffffffc 1262 // and alignedaddr,ptr,masklsb2 1263 // andi ptrlsb2,ptr,3 1264 // sll shiftamt,ptrlsb2,3 1265 // ori maskupper,$0,255 # 0xff 1266 // sll mask,maskupper,shiftamt 1267 // nor mask2,$0,mask 1268 // andi maskedcmpval,cmpval,255 1269 // sll shiftedcmpval,maskedcmpval,shiftamt 1270 // andi maskednewval,newval,255 1271 // sll shiftednewval,maskednewval,shiftamt 1272 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1273 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2) 1274 .addReg(Mips::ZERO).addImm(-4); 1275 BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr) 1276 .addReg(Ptr).addReg(MaskLSB2); 1277 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1278 if (Subtarget->isLittle()) { 1279 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1280 } else { 1281 unsigned Off = RegInfo.createVirtualRegister(RC); 1282 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1283 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1284 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1285 } 1286 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1287 .addReg(Mips::ZERO).addImm(MaskImm); 1288 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1289 .addReg(MaskUpper).addReg(ShiftAmt); 1290 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1291 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal) 1292 .addReg(CmpVal).addImm(MaskImm); 1293 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal) 1294 .addReg(MaskedCmpVal).addReg(ShiftAmt); 1295 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal) 1296 .addReg(NewVal).addImm(MaskImm); 1297 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal) 1298 .addReg(MaskedNewVal).addReg(ShiftAmt); 1299 1300 // loop1MBB: 1301 // ll oldval,0(alginedaddr) 1302 // and maskedoldval0,oldval,mask 1303 // bne maskedoldval0,shiftedcmpval,sinkMBB 1304 BB = loop1MBB; 1305 BuildMI(BB, DL, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0); 1306 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0) 1307 .addReg(OldVal).addReg(Mask); 1308 BuildMI(BB, DL, TII->get(Mips::BNE)) 1309 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB); 1310 1311 // loop2MBB: 1312 // and maskedoldval1,oldval,mask2 1313 // or storeval,maskedoldval1,shiftednewval 1314 // sc success,storeval,0(alignedaddr) 1315 // beq success,$0,loop1MBB 1316 BB = loop2MBB; 1317 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1) 1318 .addReg(OldVal).addReg(Mask2); 1319 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal) 1320 .addReg(MaskedOldVal1).addReg(ShiftedNewVal); 1321 BuildMI(BB, DL, TII->get(Mips::SC), Success) 1322 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1323 BuildMI(BB, DL, TII->get(Mips::BEQ)) 1324 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB); 1325 1326 // sinkMBB: 1327 // srl srlres,maskedoldval0,shiftamt 1328 // sll sllres,srlres,24 1329 // sra dest,sllres,24 1330 BB = sinkMBB; 1331 int64_t ShiftImm = (Size == 1) ? 24 : 16; 1332 1333 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes) 1334 .addReg(MaskedOldVal0).addReg(ShiftAmt); 1335 BuildMI(BB, DL, TII->get(Mips::SLL), SllRes) 1336 .addReg(SrlRes).addImm(ShiftImm); 1337 BuildMI(BB, DL, TII->get(Mips::SRA), Dest) 1338 .addReg(SllRes).addImm(ShiftImm); 1339 1340 MI->eraseFromParent(); // The instruction is gone now. 1341 1342 return exitMBB; 1343} 1344 1345//===----------------------------------------------------------------------===// 1346// Misc Lower Operation implementation 1347//===----------------------------------------------------------------------===// 1348SDValue MipsTargetLowering::lowerBR_JT(SDValue Op, SelectionDAG &DAG) const { 1349 SDValue Chain = Op.getOperand(0); 1350 SDValue Table = Op.getOperand(1); 1351 SDValue Index = Op.getOperand(2); 1352 SDLoc DL(Op); 1353 EVT PTy = getPointerTy(); 1354 unsigned EntrySize = 1355 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(*getDataLayout()); 1356 1357 Index = DAG.getNode(ISD::MUL, DL, PTy, Index, 1358 DAG.getConstant(EntrySize, PTy)); 1359 SDValue Addr = DAG.getNode(ISD::ADD, DL, PTy, Index, Table); 1360 1361 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8); 1362 Addr = DAG.getExtLoad(ISD::SEXTLOAD, DL, PTy, Chain, Addr, 1363 MachinePointerInfo::getJumpTable(), MemVT, false, false, 1364 0); 1365 Chain = Addr.getValue(1); 1366 1367 if ((getTargetMachine().getRelocationModel() == Reloc::PIC_) || IsN64) { 1368 // For PIC, the sequence is: 1369 // BRIND(load(Jumptable + index) + RelocBase) 1370 // RelocBase can be JumpTable, GOT or some sort of global base. 1371 Addr = DAG.getNode(ISD::ADD, DL, PTy, Addr, 1372 getPICJumpTableRelocBase(Table, DAG)); 1373 } 1374 1375 return DAG.getNode(ISD::BRIND, DL, MVT::Other, Chain, Addr); 1376} 1377 1378SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 1379 // The first operand is the chain, the second is the condition, the third is 1380 // the block to branch to if the condition is true. 1381 SDValue Chain = Op.getOperand(0); 1382 SDValue Dest = Op.getOperand(2); 1383 SDLoc DL(Op); 1384 1385 SDValue CondRes = createFPCmp(DAG, Op.getOperand(1)); 1386 1387 // Return if flag is not set by a floating point comparison. 1388 if (CondRes.getOpcode() != MipsISD::FPCmp) 1389 return Op; 1390 1391 SDValue CCNode = CondRes.getOperand(2); 1392 Mips::CondCode CC = 1393 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 1394 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T; 1395 SDValue BrCode = DAG.getConstant(Opc, MVT::i32); 1396 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 1397 return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode, 1398 FCC0, Dest, CondRes); 1399} 1400 1401SDValue MipsTargetLowering:: 1402lowerSELECT(SDValue Op, SelectionDAG &DAG) const 1403{ 1404 SDValue Cond = createFPCmp(DAG, Op.getOperand(0)); 1405 1406 // Return if flag is not set by a floating point comparison. 1407 if (Cond.getOpcode() != MipsISD::FPCmp) 1408 return Op; 1409 1410 return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 1411 SDLoc(Op)); 1412} 1413 1414SDValue MipsTargetLowering:: 1415lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const 1416{ 1417 SDLoc DL(Op); 1418 EVT Ty = Op.getOperand(0).getValueType(); 1419 SDValue Cond = DAG.getNode(ISD::SETCC, DL, 1420 getSetCCResultType(*DAG.getContext(), Ty), 1421 Op.getOperand(0), Op.getOperand(1), 1422 Op.getOperand(4)); 1423 1424 return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2), 1425 Op.getOperand(3)); 1426} 1427 1428SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const { 1429 SDValue Cond = createFPCmp(DAG, Op); 1430 1431 assert(Cond.getOpcode() == MipsISD::FPCmp && 1432 "Floating point operand expected."); 1433 1434 SDValue True = DAG.getConstant(1, MVT::i32); 1435 SDValue False = DAG.getConstant(0, MVT::i32); 1436 1437 return createCMovFP(DAG, Cond, True, False, SDLoc(Op)); 1438} 1439 1440SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op, 1441 SelectionDAG &DAG) const { 1442 // FIXME there isn't actually debug info here 1443 SDLoc DL(Op); 1444 EVT Ty = Op.getValueType(); 1445 GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op); 1446 const GlobalValue *GV = N->getGlobal(); 1447 1448 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) { 1449 const MipsTargetObjectFile &TLOF = 1450 (const MipsTargetObjectFile&)getObjFileLowering(); 1451 1452 // %gp_rel relocation 1453 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) { 1454 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, 0, 1455 MipsII::MO_GPREL); 1456 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, DL, 1457 DAG.getVTList(MVT::i32), &GA, 1); 1458 SDValue GPReg = DAG.getRegister(Mips::GP, MVT::i32); 1459 return DAG.getNode(ISD::ADD, DL, MVT::i32, GPReg, GPRelNode); 1460 } 1461 1462 // %hi/%lo relocation 1463 return getAddrNonPIC(N, Ty, DAG); 1464 } 1465 1466 if (GV->hasInternalLinkage() || (GV->hasLocalLinkage() && !isa<Function>(GV))) 1467 return getAddrLocal(N, Ty, DAG, HasMips64); 1468 1469 if (LargeGOT) 1470 return getAddrGlobalLargeGOT(N, Ty, DAG, MipsII::MO_GOT_HI16, 1471 MipsII::MO_GOT_LO16, DAG.getEntryNode(), 1472 MachinePointerInfo::getGOT()); 1473 1474 return getAddrGlobal(N, Ty, DAG, 1475 HasMips64 ? MipsII::MO_GOT_DISP : MipsII::MO_GOT16, 1476 DAG.getEntryNode(), MachinePointerInfo::getGOT()); 1477} 1478 1479SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op, 1480 SelectionDAG &DAG) const { 1481 BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op); 1482 EVT Ty = Op.getValueType(); 1483 1484 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) 1485 return getAddrNonPIC(N, Ty, DAG); 1486 1487 return getAddrLocal(N, Ty, DAG, HasMips64); 1488} 1489 1490SDValue MipsTargetLowering:: 1491lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 1492{ 1493 // If the relocation model is PIC, use the General Dynamic TLS Model or 1494 // Local Dynamic TLS model, otherwise use the Initial Exec or 1495 // Local Exec TLS Model. 1496 1497 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1498 SDLoc DL(GA); 1499 const GlobalValue *GV = GA->getGlobal(); 1500 EVT PtrVT = getPointerTy(); 1501 1502 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 1503 1504 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) { 1505 // General Dynamic and Local Dynamic TLS Model. 1506 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM 1507 : MipsII::MO_TLSGD; 1508 1509 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag); 1510 SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, 1511 getGlobalReg(DAG, PtrVT), TGA); 1512 unsigned PtrSize = PtrVT.getSizeInBits(); 1513 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize); 1514 1515 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT); 1516 1517 ArgListTy Args; 1518 ArgListEntry Entry; 1519 Entry.Node = Argument; 1520 Entry.Ty = PtrTy; 1521 Args.push_back(Entry); 1522 1523 TargetLowering::CallLoweringInfo CLI(DAG.getEntryNode(), PtrTy, 1524 false, false, false, false, 0, CallingConv::C, 1525 /*IsTailCall=*/false, /*doesNotRet=*/false, 1526 /*isReturnValueUsed=*/true, 1527 TlsGetAddr, Args, DAG, DL); 1528 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 1529 1530 SDValue Ret = CallResult.first; 1531 1532 if (model != TLSModel::LocalDynamic) 1533 return Ret; 1534 1535 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1536 MipsII::MO_DTPREL_HI); 1537 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi); 1538 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1539 MipsII::MO_DTPREL_LO); 1540 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 1541 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret); 1542 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo); 1543 } 1544 1545 SDValue Offset; 1546 if (model == TLSModel::InitialExec) { 1547 // Initial Exec TLS Model 1548 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1549 MipsII::MO_GOTTPREL); 1550 TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT), 1551 TGA); 1552 Offset = DAG.getLoad(PtrVT, DL, 1553 DAG.getEntryNode(), TGA, MachinePointerInfo(), 1554 false, false, false, 0); 1555 } else { 1556 // Local Exec TLS Model 1557 assert(model == TLSModel::LocalExec); 1558 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1559 MipsII::MO_TPREL_HI); 1560 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1561 MipsII::MO_TPREL_LO); 1562 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi); 1563 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 1564 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 1565 } 1566 1567 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT); 1568 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset); 1569} 1570 1571SDValue MipsTargetLowering:: 1572lowerJumpTable(SDValue Op, SelectionDAG &DAG) const 1573{ 1574 JumpTableSDNode *N = cast<JumpTableSDNode>(Op); 1575 EVT Ty = Op.getValueType(); 1576 1577 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) 1578 return getAddrNonPIC(N, Ty, DAG); 1579 1580 return getAddrLocal(N, Ty, DAG, HasMips64); 1581} 1582 1583SDValue MipsTargetLowering:: 1584lowerConstantPool(SDValue Op, SelectionDAG &DAG) const 1585{ 1586 // gp_rel relocation 1587 // FIXME: we should reference the constant pool using small data sections, 1588 // but the asm printer currently doesn't support this feature without 1589 // hacking it. This feature should come soon so we can uncomment the 1590 // stuff below. 1591 //if (IsInSmallSection(C->getType())) { 1592 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP); 1593 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); 1594 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode); 1595 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 1596 EVT Ty = Op.getValueType(); 1597 1598 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) 1599 return getAddrNonPIC(N, Ty, DAG); 1600 1601 return getAddrLocal(N, Ty, DAG, HasMips64); 1602} 1603 1604SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const { 1605 MachineFunction &MF = DAG.getMachineFunction(); 1606 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 1607 1608 SDLoc DL(Op); 1609 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1610 getPointerTy()); 1611 1612 // vastart just stores the address of the VarArgsFrameIndex slot into the 1613 // memory location argument. 1614 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1615 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1), 1616 MachinePointerInfo(SV), false, false, 0); 1617} 1618 1619static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, 1620 bool HasExtractInsert) { 1621 EVT TyX = Op.getOperand(0).getValueType(); 1622 EVT TyY = Op.getOperand(1).getValueType(); 1623 SDValue Const1 = DAG.getConstant(1, MVT::i32); 1624 SDValue Const31 = DAG.getConstant(31, MVT::i32); 1625 SDLoc DL(Op); 1626 SDValue Res; 1627 1628 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 1629 // to i32. 1630 SDValue X = (TyX == MVT::f32) ? 1631 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 1632 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 1633 Const1); 1634 SDValue Y = (TyY == MVT::f32) ? 1635 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) : 1636 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1), 1637 Const1); 1638 1639 if (HasExtractInsert) { 1640 // ext E, Y, 31, 1 ; extract bit31 of Y 1641 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X 1642 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1); 1643 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X); 1644 } else { 1645 // sll SllX, X, 1 1646 // srl SrlX, SllX, 1 1647 // srl SrlY, Y, 31 1648 // sll SllY, SrlX, 31 1649 // or Or, SrlX, SllY 1650 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 1651 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 1652 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); 1653 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31); 1654 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY); 1655 } 1656 1657 if (TyX == MVT::f32) 1658 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res); 1659 1660 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 1661 Op.getOperand(0), DAG.getConstant(0, MVT::i32)); 1662 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 1663} 1664 1665static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, 1666 bool HasExtractInsert) { 1667 unsigned WidthX = Op.getOperand(0).getValueSizeInBits(); 1668 unsigned WidthY = Op.getOperand(1).getValueSizeInBits(); 1669 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY); 1670 SDValue Const1 = DAG.getConstant(1, MVT::i32); 1671 SDLoc DL(Op); 1672 1673 // Bitcast to integer nodes. 1674 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0)); 1675 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1)); 1676 1677 if (HasExtractInsert) { 1678 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y 1679 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X 1680 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y, 1681 DAG.getConstant(WidthY - 1, MVT::i32), Const1); 1682 1683 if (WidthX > WidthY) 1684 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E); 1685 else if (WidthY > WidthX) 1686 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E); 1687 1688 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E, 1689 DAG.getConstant(WidthX - 1, MVT::i32), Const1, X); 1690 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I); 1691 } 1692 1693 // (d)sll SllX, X, 1 1694 // (d)srl SrlX, SllX, 1 1695 // (d)srl SrlY, Y, width(Y)-1 1696 // (d)sll SllY, SrlX, width(Y)-1 1697 // or Or, SrlX, SllY 1698 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1); 1699 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); 1700 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, 1701 DAG.getConstant(WidthY - 1, MVT::i32)); 1702 1703 if (WidthX > WidthY) 1704 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY); 1705 else if (WidthY > WidthX) 1706 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY); 1707 1708 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY, 1709 DAG.getConstant(WidthX - 1, MVT::i32)); 1710 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY); 1711 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or); 1712} 1713 1714SDValue 1715MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 1716 if (Subtarget->hasMips64()) 1717 return lowerFCOPYSIGN64(Op, DAG, Subtarget->hasExtractInsert()); 1718 1719 return lowerFCOPYSIGN32(Op, DAG, Subtarget->hasExtractInsert()); 1720} 1721 1722static SDValue lowerFABS32(SDValue Op, SelectionDAG &DAG, 1723 bool HasExtractInsert) { 1724 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32); 1725 SDLoc DL(Op); 1726 1727 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 1728 // to i32. 1729 SDValue X = (Op.getValueType() == MVT::f32) ? 1730 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 1731 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 1732 Const1); 1733 1734 // Clear MSB. 1735 if (HasExtractInsert) 1736 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, 1737 DAG.getRegister(Mips::ZERO, MVT::i32), 1738 DAG.getConstant(31, MVT::i32), Const1, X); 1739 else { 1740 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 1741 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 1742 } 1743 1744 if (Op.getValueType() == MVT::f32) 1745 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res); 1746 1747 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 1748 Op.getOperand(0), DAG.getConstant(0, MVT::i32)); 1749 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 1750} 1751 1752static SDValue lowerFABS64(SDValue Op, SelectionDAG &DAG, 1753 bool HasExtractInsert) { 1754 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32); 1755 SDLoc DL(Op); 1756 1757 // Bitcast to integer node. 1758 SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0)); 1759 1760 // Clear MSB. 1761 if (HasExtractInsert) 1762 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64, 1763 DAG.getRegister(Mips::ZERO_64, MVT::i64), 1764 DAG.getConstant(63, MVT::i32), Const1, X); 1765 else { 1766 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1); 1767 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1); 1768 } 1769 1770 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res); 1771} 1772 1773SDValue 1774MipsTargetLowering::lowerFABS(SDValue Op, SelectionDAG &DAG) const { 1775 if (Subtarget->hasMips64() && (Op.getValueType() == MVT::f64)) 1776 return lowerFABS64(Op, DAG, Subtarget->hasExtractInsert()); 1777 1778 return lowerFABS32(Op, DAG, Subtarget->hasExtractInsert()); 1779} 1780 1781SDValue MipsTargetLowering:: 1782lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 1783 // check the depth 1784 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 1785 "Frame address can only be determined for current frame."); 1786 1787 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1788 MFI->setFrameAddressIsTaken(true); 1789 EVT VT = Op.getValueType(); 1790 SDLoc DL(Op); 1791 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL, 1792 IsN64 ? Mips::FP_64 : Mips::FP, VT); 1793 return FrameAddr; 1794} 1795 1796SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op, 1797 SelectionDAG &DAG) const { 1798 // check the depth 1799 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 1800 "Return address can be determined only for current frame."); 1801 1802 MachineFunction &MF = DAG.getMachineFunction(); 1803 MachineFrameInfo *MFI = MF.getFrameInfo(); 1804 MVT VT = Op.getSimpleValueType(); 1805 unsigned RA = IsN64 ? Mips::RA_64 : Mips::RA; 1806 MFI->setReturnAddressIsTaken(true); 1807 1808 // Return RA, which contains the return address. Mark it an implicit live-in. 1809 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); 1810 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT); 1811} 1812 1813// An EH_RETURN is the result of lowering llvm.eh.return which in turn is 1814// generated from __builtin_eh_return (offset, handler) 1815// The effect of this is to adjust the stack pointer by "offset" 1816// and then branch to "handler". 1817SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) 1818 const { 1819 MachineFunction &MF = DAG.getMachineFunction(); 1820 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 1821 1822 MipsFI->setCallsEhReturn(); 1823 SDValue Chain = Op.getOperand(0); 1824 SDValue Offset = Op.getOperand(1); 1825 SDValue Handler = Op.getOperand(2); 1826 SDLoc DL(Op); 1827 EVT Ty = IsN64 ? MVT::i64 : MVT::i32; 1828 1829 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and 1830 // EH_RETURN nodes, so that instructions are emitted back-to-back. 1831 unsigned OffsetReg = IsN64 ? Mips::V1_64 : Mips::V1; 1832 unsigned AddrReg = IsN64 ? Mips::V0_64 : Mips::V0; 1833 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue()); 1834 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1)); 1835 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain, 1836 DAG.getRegister(OffsetReg, Ty), 1837 DAG.getRegister(AddrReg, getPointerTy()), 1838 Chain.getValue(1)); 1839} 1840 1841SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op, 1842 SelectionDAG &DAG) const { 1843 // FIXME: Need pseudo-fence for 'singlethread' fences 1844 // FIXME: Set SType for weaker fences where supported/appropriate. 1845 unsigned SType = 0; 1846 SDLoc DL(Op); 1847 return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0), 1848 DAG.getConstant(SType, MVT::i32)); 1849} 1850 1851SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op, 1852 SelectionDAG &DAG) const { 1853 SDLoc DL(Op); 1854 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 1855 SDValue Shamt = Op.getOperand(2); 1856 1857 // if shamt < 32: 1858 // lo = (shl lo, shamt) 1859 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt)) 1860 // else: 1861 // lo = 0 1862 // hi = (shl lo, shamt[4:0]) 1863 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 1864 DAG.getConstant(-1, MVT::i32)); 1865 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, 1866 DAG.getConstant(1, MVT::i32)); 1867 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo, 1868 Not); 1869 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt); 1870 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo); 1871 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt); 1872 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 1873 DAG.getConstant(0x20, MVT::i32)); 1874 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, 1875 DAG.getConstant(0, MVT::i32), ShiftLeftLo); 1876 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or); 1877 1878 SDValue Ops[2] = {Lo, Hi}; 1879 return DAG.getMergeValues(Ops, 2, DL); 1880} 1881 1882SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, 1883 bool IsSRA) const { 1884 SDLoc DL(Op); 1885 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 1886 SDValue Shamt = Op.getOperand(2); 1887 1888 // if shamt < 32: 1889 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt)) 1890 // if isSRA: 1891 // hi = (sra hi, shamt) 1892 // else: 1893 // hi = (srl hi, shamt) 1894 // else: 1895 // if isSRA: 1896 // lo = (sra hi, shamt[4:0]) 1897 // hi = (sra hi, 31) 1898 // else: 1899 // lo = (srl hi, shamt[4:0]) 1900 // hi = 0 1901 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 1902 DAG.getConstant(-1, MVT::i32)); 1903 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, 1904 DAG.getConstant(1, MVT::i32)); 1905 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not); 1906 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt); 1907 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo); 1908 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32, 1909 Hi, Shamt); 1910 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 1911 DAG.getConstant(0x20, MVT::i32)); 1912 SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi, 1913 DAG.getConstant(31, MVT::i32)); 1914 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or); 1915 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, 1916 IsSRA ? Shift31 : DAG.getConstant(0, MVT::i32), 1917 ShiftRightHi); 1918 1919 SDValue Ops[2] = {Lo, Hi}; 1920 return DAG.getMergeValues(Ops, 2, DL); 1921} 1922 1923static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, 1924 SDValue Chain, SDValue Src, unsigned Offset) { 1925 SDValue Ptr = LD->getBasePtr(); 1926 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT(); 1927 EVT BasePtrVT = Ptr.getValueType(); 1928 SDLoc DL(LD); 1929 SDVTList VTList = DAG.getVTList(VT, MVT::Other); 1930 1931 if (Offset) 1932 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 1933 DAG.getConstant(Offset, BasePtrVT)); 1934 1935 SDValue Ops[] = { Chain, Ptr, Src }; 1936 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT, 1937 LD->getMemOperand()); 1938} 1939 1940// Expand an unaligned 32 or 64-bit integer load node. 1941SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const { 1942 LoadSDNode *LD = cast<LoadSDNode>(Op); 1943 EVT MemVT = LD->getMemoryVT(); 1944 1945 // Return if load is aligned or if MemVT is neither i32 nor i64. 1946 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) || 1947 ((MemVT != MVT::i32) && (MemVT != MVT::i64))) 1948 return SDValue(); 1949 1950 bool IsLittle = Subtarget->isLittle(); 1951 EVT VT = Op.getValueType(); 1952 ISD::LoadExtType ExtType = LD->getExtensionType(); 1953 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT); 1954 1955 assert((VT == MVT::i32) || (VT == MVT::i64)); 1956 1957 // Expand 1958 // (set dst, (i64 (load baseptr))) 1959 // to 1960 // (set tmp, (ldl (add baseptr, 7), undef)) 1961 // (set dst, (ldr baseptr, tmp)) 1962 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) { 1963 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef, 1964 IsLittle ? 7 : 0); 1965 return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL, 1966 IsLittle ? 0 : 7); 1967 } 1968 1969 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, 1970 IsLittle ? 3 : 0); 1971 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, 1972 IsLittle ? 0 : 3); 1973 1974 // Expand 1975 // (set dst, (i32 (load baseptr))) or 1976 // (set dst, (i64 (sextload baseptr))) or 1977 // (set dst, (i64 (extload baseptr))) 1978 // to 1979 // (set tmp, (lwl (add baseptr, 3), undef)) 1980 // (set dst, (lwr baseptr, tmp)) 1981 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) || 1982 (ExtType == ISD::EXTLOAD)) 1983 return LWR; 1984 1985 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)); 1986 1987 // Expand 1988 // (set dst, (i64 (zextload baseptr))) 1989 // to 1990 // (set tmp0, (lwl (add baseptr, 3), undef)) 1991 // (set tmp1, (lwr baseptr, tmp0)) 1992 // (set tmp2, (shl tmp1, 32)) 1993 // (set dst, (srl tmp2, 32)) 1994 SDLoc DL(LD); 1995 SDValue Const32 = DAG.getConstant(32, MVT::i32); 1996 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); 1997 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); 1998 SDValue Ops[] = { SRL, LWR.getValue(1) }; 1999 return DAG.getMergeValues(Ops, 2, DL); 2000} 2001 2002static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, 2003 SDValue Chain, unsigned Offset) { 2004 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue(); 2005 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType(); 2006 SDLoc DL(SD); 2007 SDVTList VTList = DAG.getVTList(MVT::Other); 2008 2009 if (Offset) 2010 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2011 DAG.getConstant(Offset, BasePtrVT)); 2012 2013 SDValue Ops[] = { Chain, Value, Ptr }; 2014 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT, 2015 SD->getMemOperand()); 2016} 2017 2018// Expand an unaligned 32 or 64-bit integer store node. 2019static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG, 2020 bool IsLittle) { 2021 SDValue Value = SD->getValue(), Chain = SD->getChain(); 2022 EVT VT = Value.getValueType(); 2023 2024 // Expand 2025 // (store val, baseptr) or 2026 // (truncstore val, baseptr) 2027 // to 2028 // (swl val, (add baseptr, 3)) 2029 // (swr val, baseptr) 2030 if ((VT == MVT::i32) || SD->isTruncatingStore()) { 2031 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain, 2032 IsLittle ? 3 : 0); 2033 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); 2034 } 2035 2036 assert(VT == MVT::i64); 2037 2038 // Expand 2039 // (store val, baseptr) 2040 // to 2041 // (sdl val, (add baseptr, 7)) 2042 // (sdr val, baseptr) 2043 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0); 2044 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7); 2045} 2046 2047// Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr). 2048static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG) { 2049 SDValue Val = SD->getValue(); 2050 2051 if (Val.getOpcode() != ISD::FP_TO_SINT) 2052 return SDValue(); 2053 2054 EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits()); 2055 SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy, 2056 Val.getOperand(0)); 2057 2058 return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(), 2059 SD->getPointerInfo(), SD->isVolatile(), 2060 SD->isNonTemporal(), SD->getAlignment()); 2061} 2062 2063SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const { 2064 StoreSDNode *SD = cast<StoreSDNode>(Op); 2065 EVT MemVT = SD->getMemoryVT(); 2066 2067 // Lower unaligned integer stores. 2068 if ((SD->getAlignment() < MemVT.getSizeInBits() / 8) && 2069 ((MemVT == MVT::i32) || (MemVT == MVT::i64))) 2070 return lowerUnalignedIntStore(SD, DAG, Subtarget->isLittle()); 2071 2072 return lowerFP_TO_SINT_STORE(SD, DAG); 2073} 2074 2075SDValue MipsTargetLowering::lowerADD(SDValue Op, SelectionDAG &DAG) const { 2076 if (Op->getOperand(0).getOpcode() != ISD::FRAMEADDR 2077 || cast<ConstantSDNode> 2078 (Op->getOperand(0).getOperand(0))->getZExtValue() != 0 2079 || Op->getOperand(1).getOpcode() != ISD::FRAME_TO_ARGS_OFFSET) 2080 return SDValue(); 2081 2082 // The pattern 2083 // (add (frameaddr 0), (frame_to_args_offset)) 2084 // results from lowering llvm.eh.dwarf.cfa intrinsic. Transform it to 2085 // (add FrameObject, 0) 2086 // where FrameObject is a fixed StackObject with offset 0 which points to 2087 // the old stack pointer. 2088 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2089 EVT ValTy = Op->getValueType(0); 2090 int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false); 2091 SDValue InArgsAddr = DAG.getFrameIndex(FI, ValTy); 2092 return DAG.getNode(ISD::ADD, SDLoc(Op), ValTy, InArgsAddr, 2093 DAG.getConstant(0, ValTy)); 2094} 2095 2096SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op, 2097 SelectionDAG &DAG) const { 2098 EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits()); 2099 SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy, 2100 Op.getOperand(0)); 2101 return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc); 2102} 2103 2104//===----------------------------------------------------------------------===// 2105// Calling Convention Implementation 2106//===----------------------------------------------------------------------===// 2107 2108//===----------------------------------------------------------------------===// 2109// TODO: Implement a generic logic using tblgen that can support this. 2110// Mips O32 ABI rules: 2111// --- 2112// i32 - Passed in A0, A1, A2, A3 and stack 2113// f32 - Only passed in f32 registers if no int reg has been used yet to hold 2114// an argument. Otherwise, passed in A1, A2, A3 and stack. 2115// f64 - Only passed in two aliased f32 registers if no int reg has been used 2116// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 2117// not used, it must be shadowed. If only A3 is avaiable, shadow it and 2118// go to stack. 2119// 2120// For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 2121//===----------------------------------------------------------------------===// 2122 2123static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, 2124 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, 2125 CCState &State, const uint16_t *F64Regs) { 2126 2127 static const unsigned IntRegsSize = 4, FloatRegsSize = 2; 2128 2129 static const uint16_t IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 }; 2130 static const uint16_t F32Regs[] = { Mips::F12, Mips::F14 }; 2131 2132 // Do not process byval args here. 2133 if (ArgFlags.isByVal()) 2134 return true; 2135 2136 // Promote i8 and i16 2137 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 2138 LocVT = MVT::i32; 2139 if (ArgFlags.isSExt()) 2140 LocInfo = CCValAssign::SExt; 2141 else if (ArgFlags.isZExt()) 2142 LocInfo = CCValAssign::ZExt; 2143 else 2144 LocInfo = CCValAssign::AExt; 2145 } 2146 2147 unsigned Reg; 2148 2149 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 2150 // is true: function is vararg, argument is 3rd or higher, there is previous 2151 // argument which is not f32 or f64. 2152 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 2153 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo; 2154 unsigned OrigAlign = ArgFlags.getOrigAlign(); 2155 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8); 2156 2157 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 2158 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2159 // If this is the first part of an i64 arg, 2160 // the allocated register must be either A0 or A2. 2161 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 2162 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2163 LocVT = MVT::i32; 2164 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 2165 // Allocate int register and shadow next int register. If first 2166 // available register is Mips::A1 or Mips::A3, shadow it too. 2167 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2168 if (Reg == Mips::A1 || Reg == Mips::A3) 2169 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2170 State.AllocateReg(IntRegs, IntRegsSize); 2171 LocVT = MVT::i32; 2172 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 2173 // we are guaranteed to find an available float register 2174 if (ValVT == MVT::f32) { 2175 Reg = State.AllocateReg(F32Regs, FloatRegsSize); 2176 // Shadow int register 2177 State.AllocateReg(IntRegs, IntRegsSize); 2178 } else { 2179 Reg = State.AllocateReg(F64Regs, FloatRegsSize); 2180 // Shadow int registers 2181 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize); 2182 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 2183 State.AllocateReg(IntRegs, IntRegsSize); 2184 State.AllocateReg(IntRegs, IntRegsSize); 2185 } 2186 } else 2187 llvm_unreachable("Cannot handle this ValVT."); 2188 2189 if (!Reg) { 2190 unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3, 2191 OrigAlign); 2192 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 2193 } else 2194 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2195 2196 return false; 2197} 2198 2199static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, 2200 MVT LocVT, CCValAssign::LocInfo LocInfo, 2201 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2202 static const uint16_t F64Regs[] = { Mips::D6, Mips::D7 }; 2203 2204 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2205} 2206 2207static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, 2208 MVT LocVT, CCValAssign::LocInfo LocInfo, 2209 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2210 static const uint16_t F64Regs[] = { Mips::D12_64, Mips::D12_64 }; 2211 2212 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2213} 2214 2215#include "MipsGenCallingConv.inc" 2216 2217//===----------------------------------------------------------------------===// 2218// Call Calling Convention Implementation 2219//===----------------------------------------------------------------------===// 2220 2221// Return next O32 integer argument register. 2222static unsigned getNextIntArgReg(unsigned Reg) { 2223 assert((Reg == Mips::A0) || (Reg == Mips::A2)); 2224 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3; 2225} 2226 2227SDValue 2228MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset, 2229 SDValue Chain, SDValue Arg, SDLoc DL, 2230 bool IsTailCall, SelectionDAG &DAG) const { 2231 if (!IsTailCall) { 2232 SDValue PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, 2233 DAG.getIntPtrConstant(Offset)); 2234 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), false, 2235 false, 0); 2236 } 2237 2238 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2239 int FI = MFI->CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false); 2240 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2241 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(), 2242 /*isVolatile=*/ true, false, 0); 2243} 2244 2245void MipsTargetLowering:: 2246getOpndList(SmallVectorImpl<SDValue> &Ops, 2247 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 2248 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 2249 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const { 2250 // Insert node "GP copy globalreg" before call to function. 2251 // 2252 // R_MIPS_CALL* operators (emitted when non-internal functions are called 2253 // in PIC mode) allow symbols to be resolved via lazy binding. 2254 // The lazy binding stub requires GP to point to the GOT. 2255 if (IsPICCall && !InternalLinkage) { 2256 unsigned GPReg = IsN64 ? Mips::GP_64 : Mips::GP; 2257 EVT Ty = IsN64 ? MVT::i64 : MVT::i32; 2258 RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty))); 2259 } 2260 2261 // Build a sequence of copy-to-reg nodes chained together with token 2262 // chain and flag operands which copy the outgoing args into registers. 2263 // The InFlag in necessary since all emitted instructions must be 2264 // stuck together. 2265 SDValue InFlag; 2266 2267 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2268 Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first, 2269 RegsToPass[i].second, InFlag); 2270 InFlag = Chain.getValue(1); 2271 } 2272 2273 // Add argument registers to the end of the list so that they are 2274 // known live into the call. 2275 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2276 Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first, 2277 RegsToPass[i].second.getValueType())); 2278 2279 // Add a register mask operand representing the call-preserved registers. 2280 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 2281 const uint32_t *Mask = TRI->getCallPreservedMask(CLI.CallConv); 2282 assert(Mask && "Missing call preserved mask for calling convention"); 2283 if (Subtarget->inMips16HardFloat()) { 2284 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) { 2285 llvm::StringRef Sym = G->getGlobal()->getName(); 2286 Function *F = G->getGlobal()->getParent()->getFunction(Sym); 2287 if (F->hasFnAttribute("__Mips16RetHelper")) { 2288 Mask = MipsRegisterInfo::getMips16RetHelperMask(); 2289 } 2290 } 2291 } 2292 Ops.push_back(CLI.DAG.getRegisterMask(Mask)); 2293 2294 if (InFlag.getNode()) 2295 Ops.push_back(InFlag); 2296} 2297 2298/// LowerCall - functions arguments are copied from virtual regs to 2299/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 2300SDValue 2301MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 2302 SmallVectorImpl<SDValue> &InVals) const { 2303 SelectionDAG &DAG = CLI.DAG; 2304 SDLoc DL = CLI.DL; 2305 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 2306 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 2307 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 2308 SDValue Chain = CLI.Chain; 2309 SDValue Callee = CLI.Callee; 2310 bool &IsTailCall = CLI.IsTailCall; 2311 CallingConv::ID CallConv = CLI.CallConv; 2312 bool IsVarArg = CLI.IsVarArg; 2313 2314 MachineFunction &MF = DAG.getMachineFunction(); 2315 MachineFrameInfo *MFI = MF.getFrameInfo(); 2316 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering(); 2317 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 2318 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 2319 2320 // Analyze operands of the call, assigning locations to each operand. 2321 SmallVector<CCValAssign, 16> ArgLocs; 2322 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 2323 getTargetMachine(), ArgLocs, *DAG.getContext()); 2324 MipsCC::SpecialCallingConvType SpecialCallingConv = 2325 getSpecialCallingConv(Callee); 2326 MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo, 2327 SpecialCallingConv); 2328 2329 MipsCCInfo.analyzeCallOperands(Outs, IsVarArg, 2330 Subtarget->mipsSEUsesSoftFloat(), 2331 Callee.getNode(), CLI.Args); 2332 2333 // Get a count of how many bytes are to be pushed on the stack. 2334 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 2335 2336 // Check if it's really possible to do a tail call. 2337 if (IsTailCall) 2338 IsTailCall = 2339 isEligibleForTailCallOptimization(MipsCCInfo, NextStackOffset, 2340 *MF.getInfo<MipsFunctionInfo>()); 2341 2342 if (IsTailCall) 2343 ++NumTailCalls; 2344 2345 // Chain is the output chain of the last Load/Store or CopyToReg node. 2346 // ByValChain is the output chain of the last Memcpy node created for copying 2347 // byval arguments to the stack. 2348 unsigned StackAlignment = TFL->getStackAlignment(); 2349 NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment); 2350 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true); 2351 2352 if (!IsTailCall) 2353 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL); 2354 2355 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, 2356 IsN64 ? Mips::SP_64 : Mips::SP, 2357 getPointerTy()); 2358 2359 // With EABI is it possible to have 16 args on registers. 2360 std::deque< std::pair<unsigned, SDValue> > RegsToPass; 2361 SmallVector<SDValue, 8> MemOpChains; 2362 MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin(); 2363 2364 // Walk the register/memloc assignments, inserting copies/loads. 2365 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2366 SDValue Arg = OutVals[i]; 2367 CCValAssign &VA = ArgLocs[i]; 2368 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); 2369 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2370 2371 // ByVal Arg. 2372 if (Flags.isByVal()) { 2373 assert(Flags.getByValSize() && 2374 "ByVal args of size 0 should have been ignored by front-end."); 2375 assert(ByValArg != MipsCCInfo.byval_end()); 2376 assert(!IsTailCall && 2377 "Do not tail-call optimize if there is a byval argument."); 2378 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg, 2379 MipsCCInfo, *ByValArg, Flags, Subtarget->isLittle()); 2380 ++ByValArg; 2381 continue; 2382 } 2383 2384 // Promote the value if needed. 2385 switch (VA.getLocInfo()) { 2386 default: llvm_unreachable("Unknown loc info!"); 2387 case CCValAssign::Full: 2388 if (VA.isRegLoc()) { 2389 if ((ValVT == MVT::f32 && LocVT == MVT::i32) || 2390 (ValVT == MVT::f64 && LocVT == MVT::i64) || 2391 (ValVT == MVT::i64 && LocVT == MVT::f64)) 2392 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 2393 else if (ValVT == MVT::f64 && LocVT == MVT::i32) { 2394 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2395 Arg, DAG.getConstant(0, MVT::i32)); 2396 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2397 Arg, DAG.getConstant(1, MVT::i32)); 2398 if (!Subtarget->isLittle()) 2399 std::swap(Lo, Hi); 2400 unsigned LocRegLo = VA.getLocReg(); 2401 unsigned LocRegHigh = getNextIntArgReg(LocRegLo); 2402 RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); 2403 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); 2404 continue; 2405 } 2406 } 2407 break; 2408 case CCValAssign::SExt: 2409 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg); 2410 break; 2411 case CCValAssign::ZExt: 2412 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg); 2413 break; 2414 case CCValAssign::AExt: 2415 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg); 2416 break; 2417 } 2418 2419 // Arguments that can be passed on register must be kept at 2420 // RegsToPass vector 2421 if (VA.isRegLoc()) { 2422 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2423 continue; 2424 } 2425 2426 // Register can't get to this point... 2427 assert(VA.isMemLoc()); 2428 2429 // emit ISD::STORE whichs stores the 2430 // parameter value to a stack Location 2431 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(), 2432 Chain, Arg, DL, IsTailCall, DAG)); 2433 } 2434 2435 // Transform all store nodes into one single node because all store 2436 // nodes are independent of each other. 2437 if (!MemOpChains.empty()) 2438 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 2439 &MemOpChains[0], MemOpChains.size()); 2440 2441 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 2442 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 2443 // node so that legalize doesn't hack it. 2444 bool IsPICCall = (IsN64 || IsPIC); // true if calls are translated to jalr $25 2445 bool GlobalOrExternal = false, InternalLinkage = false; 2446 SDValue CalleeLo; 2447 EVT Ty = Callee.getValueType(); 2448 2449 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2450 if (IsPICCall) { 2451 const GlobalValue *Val = G->getGlobal(); 2452 InternalLinkage = Val->hasInternalLinkage(); 2453 2454 if (InternalLinkage) 2455 Callee = getAddrLocal(G, Ty, DAG, HasMips64); 2456 else if (LargeGOT) 2457 Callee = getAddrGlobalLargeGOT(G, Ty, DAG, MipsII::MO_CALL_HI16, 2458 MipsII::MO_CALL_LO16, Chain, 2459 FuncInfo->callPtrInfo(Val)); 2460 else 2461 Callee = getAddrGlobal(G, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 2462 FuncInfo->callPtrInfo(Val)); 2463 } else 2464 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, getPointerTy(), 0, 2465 MipsII::MO_NO_FLAG); 2466 GlobalOrExternal = true; 2467 } 2468 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2469 const char *Sym = S->getSymbol(); 2470 2471 if (!IsN64 && !IsPIC) // !N64 && static 2472 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), 2473 MipsII::MO_NO_FLAG); 2474 else if (LargeGOT) 2475 Callee = getAddrGlobalLargeGOT(S, Ty, DAG, MipsII::MO_CALL_HI16, 2476 MipsII::MO_CALL_LO16, Chain, 2477 FuncInfo->callPtrInfo(Sym)); 2478 else // N64 || PIC 2479 Callee = getAddrGlobal(S, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 2480 FuncInfo->callPtrInfo(Sym)); 2481 2482 GlobalOrExternal = true; 2483 } 2484 2485 SmallVector<SDValue, 8> Ops(1, Chain); 2486 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2487 2488 getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, InternalLinkage, 2489 CLI, Callee, Chain); 2490 2491 if (IsTailCall) 2492 return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, &Ops[0], Ops.size()); 2493 2494 Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, &Ops[0], Ops.size()); 2495 SDValue InFlag = Chain.getValue(1); 2496 2497 // Create the CALLSEQ_END node. 2498 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal, 2499 DAG.getIntPtrConstant(0, true), InFlag, DL); 2500 InFlag = Chain.getValue(1); 2501 2502 // Handle result values, copying them out of physregs into vregs that we 2503 // return. 2504 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, 2505 Ins, DL, DAG, InVals, CLI.Callee.getNode(), CLI.RetTy); 2506} 2507 2508/// LowerCallResult - Lower the result values of a call into the 2509/// appropriate copies out of appropriate physical registers. 2510SDValue 2511MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 2512 CallingConv::ID CallConv, bool IsVarArg, 2513 const SmallVectorImpl<ISD::InputArg> &Ins, 2514 SDLoc DL, SelectionDAG &DAG, 2515 SmallVectorImpl<SDValue> &InVals, 2516 const SDNode *CallNode, 2517 const Type *RetTy) const { 2518 // Assign locations to each value returned by this call. 2519 SmallVector<CCValAssign, 16> RVLocs; 2520 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 2521 getTargetMachine(), RVLocs, *DAG.getContext()); 2522 MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo); 2523 2524 MipsCCInfo.analyzeCallResult(Ins, Subtarget->mipsSEUsesSoftFloat(), 2525 CallNode, RetTy); 2526 2527 // Copy all of the result registers out of their specified physreg. 2528 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2529 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), 2530 RVLocs[i].getLocVT(), InFlag); 2531 Chain = Val.getValue(1); 2532 InFlag = Val.getValue(2); 2533 2534 if (RVLocs[i].getValVT() != RVLocs[i].getLocVT()) 2535 Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getValVT(), Val); 2536 2537 InVals.push_back(Val); 2538 } 2539 2540 return Chain; 2541} 2542 2543//===----------------------------------------------------------------------===// 2544// Formal Arguments Calling Convention Implementation 2545//===----------------------------------------------------------------------===// 2546/// LowerFormalArguments - transform physical registers into virtual registers 2547/// and generate load operations for arguments places on the stack. 2548SDValue 2549MipsTargetLowering::LowerFormalArguments(SDValue Chain, 2550 CallingConv::ID CallConv, 2551 bool IsVarArg, 2552 const SmallVectorImpl<ISD::InputArg> &Ins, 2553 SDLoc DL, SelectionDAG &DAG, 2554 SmallVectorImpl<SDValue> &InVals) 2555 const { 2556 MachineFunction &MF = DAG.getMachineFunction(); 2557 MachineFrameInfo *MFI = MF.getFrameInfo(); 2558 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2559 2560 MipsFI->setVarArgsFrameIndex(0); 2561 2562 // Used with vargs to acumulate store chains. 2563 std::vector<SDValue> OutChains; 2564 2565 // Assign locations to all of the incoming arguments. 2566 SmallVector<CCValAssign, 16> ArgLocs; 2567 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 2568 getTargetMachine(), ArgLocs, *DAG.getContext()); 2569 MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo); 2570 Function::const_arg_iterator FuncArg = 2571 DAG.getMachineFunction().getFunction()->arg_begin(); 2572 bool UseSoftFloat = Subtarget->mipsSEUsesSoftFloat(); 2573 2574 MipsCCInfo.analyzeFormalArguments(Ins, UseSoftFloat, FuncArg); 2575 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(), 2576 MipsCCInfo.hasByValArg()); 2577 2578 unsigned CurArgIdx = 0; 2579 MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin(); 2580 2581 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2582 CCValAssign &VA = ArgLocs[i]; 2583 std::advance(FuncArg, Ins[i].OrigArgIndex - CurArgIdx); 2584 CurArgIdx = Ins[i].OrigArgIndex; 2585 EVT ValVT = VA.getValVT(); 2586 ISD::ArgFlagsTy Flags = Ins[i].Flags; 2587 bool IsRegLoc = VA.isRegLoc(); 2588 2589 if (Flags.isByVal()) { 2590 assert(Flags.getByValSize() && 2591 "ByVal args of size 0 should have been ignored by front-end."); 2592 assert(ByValArg != MipsCCInfo.byval_end()); 2593 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg, 2594 MipsCCInfo, *ByValArg); 2595 ++ByValArg; 2596 continue; 2597 } 2598 2599 // Arguments stored on registers 2600 if (IsRegLoc) { 2601 MVT RegVT = VA.getLocVT(); 2602 unsigned ArgReg = VA.getLocReg(); 2603 const TargetRegisterClass *RC = getRegClassFor(RegVT); 2604 2605 // Transform the arguments stored on 2606 // physical registers into virtual ones 2607 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC); 2608 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); 2609 2610 // If this is an 8 or 16-bit value, it has been passed promoted 2611 // to 32 bits. Insert an assert[sz]ext to capture this, then 2612 // truncate to the right size. 2613 if (VA.getLocInfo() != CCValAssign::Full) { 2614 unsigned Opcode = 0; 2615 if (VA.getLocInfo() == CCValAssign::SExt) 2616 Opcode = ISD::AssertSext; 2617 else if (VA.getLocInfo() == CCValAssign::ZExt) 2618 Opcode = ISD::AssertZext; 2619 if (Opcode) 2620 ArgValue = DAG.getNode(Opcode, DL, RegVT, ArgValue, 2621 DAG.getValueType(ValVT)); 2622 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, ValVT, ArgValue); 2623 } 2624 2625 // Handle floating point arguments passed in integer registers and 2626 // long double arguments passed in floating point registers. 2627 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || 2628 (RegVT == MVT::i64 && ValVT == MVT::f64) || 2629 (RegVT == MVT::f64 && ValVT == MVT::i64)) 2630 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue); 2631 else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) { 2632 unsigned Reg2 = addLiveIn(DAG.getMachineFunction(), 2633 getNextIntArgReg(ArgReg), RC); 2634 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); 2635 if (!Subtarget->isLittle()) 2636 std::swap(ArgValue, ArgValue2); 2637 ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, 2638 ArgValue, ArgValue2); 2639 } 2640 2641 InVals.push_back(ArgValue); 2642 } else { // VA.isRegLoc() 2643 2644 // sanity check 2645 assert(VA.isMemLoc()); 2646 2647 // The stack pointer offset is relative to the caller stack frame. 2648 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 2649 VA.getLocMemOffset(), true); 2650 2651 // Create load nodes to retrieve arguments from the stack 2652 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2653 SDValue Load = DAG.getLoad(ValVT, DL, Chain, FIN, 2654 MachinePointerInfo::getFixedStack(FI), 2655 false, false, false, 0); 2656 InVals.push_back(Load); 2657 OutChains.push_back(Load.getValue(1)); 2658 } 2659 } 2660 2661 // The mips ABIs for returning structs by value requires that we copy 2662 // the sret argument into $v0 for the return. Save the argument into 2663 // a virtual register so that we can access it from the return points. 2664 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 2665 unsigned Reg = MipsFI->getSRetReturnReg(); 2666 if (!Reg) { 2667 Reg = MF.getRegInfo(). 2668 createVirtualRegister(getRegClassFor(IsN64 ? MVT::i64 : MVT::i32)); 2669 MipsFI->setSRetReturnReg(Reg); 2670 } 2671 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[0]); 2672 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain); 2673 } 2674 2675 if (IsVarArg) 2676 writeVarArgRegs(OutChains, MipsCCInfo, Chain, DL, DAG); 2677 2678 // All stores are grouped in one node to allow the matching between 2679 // the size of Ins and InVals. This only happens when on varg functions 2680 if (!OutChains.empty()) { 2681 OutChains.push_back(Chain); 2682 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 2683 &OutChains[0], OutChains.size()); 2684 } 2685 2686 return Chain; 2687} 2688 2689//===----------------------------------------------------------------------===// 2690// Return Value Calling Convention Implementation 2691//===----------------------------------------------------------------------===// 2692 2693bool 2694MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv, 2695 MachineFunction &MF, bool IsVarArg, 2696 const SmallVectorImpl<ISD::OutputArg> &Outs, 2697 LLVMContext &Context) const { 2698 SmallVector<CCValAssign, 16> RVLocs; 2699 CCState CCInfo(CallConv, IsVarArg, MF, getTargetMachine(), 2700 RVLocs, Context); 2701 return CCInfo.CheckReturn(Outs, RetCC_Mips); 2702} 2703 2704SDValue 2705MipsTargetLowering::LowerReturn(SDValue Chain, 2706 CallingConv::ID CallConv, bool IsVarArg, 2707 const SmallVectorImpl<ISD::OutputArg> &Outs, 2708 const SmallVectorImpl<SDValue> &OutVals, 2709 SDLoc DL, SelectionDAG &DAG) const { 2710 // CCValAssign - represent the assignment of 2711 // the return value to a location 2712 SmallVector<CCValAssign, 16> RVLocs; 2713 MachineFunction &MF = DAG.getMachineFunction(); 2714 2715 // CCState - Info about the registers and stack slot. 2716 CCState CCInfo(CallConv, IsVarArg, MF, getTargetMachine(), RVLocs, 2717 *DAG.getContext()); 2718 MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo); 2719 2720 // Analyze return values. 2721 MipsCCInfo.analyzeReturn(Outs, Subtarget->mipsSEUsesSoftFloat(), 2722 MF.getFunction()->getReturnType()); 2723 2724 SDValue Flag; 2725 SmallVector<SDValue, 4> RetOps(1, Chain); 2726 2727 // Copy the result values into the output registers. 2728 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2729 SDValue Val = OutVals[i]; 2730 CCValAssign &VA = RVLocs[i]; 2731 assert(VA.isRegLoc() && "Can only return in registers!"); 2732 2733 if (RVLocs[i].getValVT() != RVLocs[i].getLocVT()) 2734 Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getLocVT(), Val); 2735 2736 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag); 2737 2738 // Guarantee that all emitted copies are stuck together with flags. 2739 Flag = Chain.getValue(1); 2740 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 2741 } 2742 2743 // The mips ABIs for returning structs by value requires that we copy 2744 // the sret argument into $v0 for the return. We saved the argument into 2745 // a virtual register in the entry block, so now we copy the value out 2746 // and into $v0. 2747 if (MF.getFunction()->hasStructRetAttr()) { 2748 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2749 unsigned Reg = MipsFI->getSRetReturnReg(); 2750 2751 if (!Reg) 2752 llvm_unreachable("sret virtual register not created in the entry block"); 2753 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy()); 2754 unsigned V0 = IsN64 ? Mips::V0_64 : Mips::V0; 2755 2756 Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag); 2757 Flag = Chain.getValue(1); 2758 RetOps.push_back(DAG.getRegister(V0, getPointerTy())); 2759 } 2760 2761 RetOps[0] = Chain; // Update chain. 2762 2763 // Add the flag if we have it. 2764 if (Flag.getNode()) 2765 RetOps.push_back(Flag); 2766 2767 // Return on Mips is always a "jr $ra" 2768 return DAG.getNode(MipsISD::Ret, DL, MVT::Other, &RetOps[0], RetOps.size()); 2769} 2770 2771//===----------------------------------------------------------------------===// 2772// Mips Inline Assembly Support 2773//===----------------------------------------------------------------------===// 2774 2775/// getConstraintType - Given a constraint letter, return the type of 2776/// constraint it is for this target. 2777MipsTargetLowering::ConstraintType MipsTargetLowering:: 2778getConstraintType(const std::string &Constraint) const 2779{ 2780 // Mips specific constrainy 2781 // GCC config/mips/constraints.md 2782 // 2783 // 'd' : An address register. Equivalent to r 2784 // unless generating MIPS16 code. 2785 // 'y' : Equivalent to r; retained for 2786 // backwards compatibility. 2787 // 'c' : A register suitable for use in an indirect 2788 // jump. This will always be $25 for -mabicalls. 2789 // 'l' : The lo register. 1 word storage. 2790 // 'x' : The hilo register pair. Double word storage. 2791 if (Constraint.size() == 1) { 2792 switch (Constraint[0]) { 2793 default : break; 2794 case 'd': 2795 case 'y': 2796 case 'f': 2797 case 'c': 2798 case 'l': 2799 case 'x': 2800 return C_RegisterClass; 2801 case 'R': 2802 return C_Memory; 2803 } 2804 } 2805 return TargetLowering::getConstraintType(Constraint); 2806} 2807 2808/// Examine constraint type and operand type and determine a weight value. 2809/// This object must already have been set up with the operand type 2810/// and the current alternative constraint selected. 2811TargetLowering::ConstraintWeight 2812MipsTargetLowering::getSingleConstraintMatchWeight( 2813 AsmOperandInfo &info, const char *constraint) const { 2814 ConstraintWeight weight = CW_Invalid; 2815 Value *CallOperandVal = info.CallOperandVal; 2816 // If we don't have a value, we can't do a match, 2817 // but allow it at the lowest weight. 2818 if (CallOperandVal == NULL) 2819 return CW_Default; 2820 Type *type = CallOperandVal->getType(); 2821 // Look at the constraint type. 2822 switch (*constraint) { 2823 default: 2824 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 2825 break; 2826 case 'd': 2827 case 'y': 2828 if (type->isIntegerTy()) 2829 weight = CW_Register; 2830 break; 2831 case 'f': 2832 if (type->isFloatTy()) 2833 weight = CW_Register; 2834 break; 2835 case 'c': // $25 for indirect jumps 2836 case 'l': // lo register 2837 case 'x': // hilo register pair 2838 if (type->isIntegerTy()) 2839 weight = CW_SpecificReg; 2840 break; 2841 case 'I': // signed 16 bit immediate 2842 case 'J': // integer zero 2843 case 'K': // unsigned 16 bit immediate 2844 case 'L': // signed 32 bit immediate where lower 16 bits are 0 2845 case 'N': // immediate in the range of -65535 to -1 (inclusive) 2846 case 'O': // signed 15 bit immediate (+- 16383) 2847 case 'P': // immediate in the range of 65535 to 1 (inclusive) 2848 if (isa<ConstantInt>(CallOperandVal)) 2849 weight = CW_Constant; 2850 break; 2851 case 'R': 2852 weight = CW_Memory; 2853 break; 2854 } 2855 return weight; 2856} 2857 2858/// This is a helper function to parse a physical register string and split it 2859/// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag 2860/// that is returned indicates whether parsing was successful. The second flag 2861/// is true if the numeric part exists. 2862static std::pair<bool, bool> 2863parsePhysicalReg(const StringRef &C, std::string &Prefix, 2864 unsigned long long &Reg) { 2865 if (C.front() != '{' || C.back() != '}') 2866 return std::make_pair(false, false); 2867 2868 // Search for the first numeric character. 2869 StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1; 2870 I = std::find_if(B, E, std::ptr_fun(isdigit)); 2871 2872 Prefix.assign(B, I - B); 2873 2874 // The second flag is set to false if no numeric characters were found. 2875 if (I == E) 2876 return std::make_pair(true, false); 2877 2878 // Parse the numeric characters. 2879 return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg), 2880 true); 2881} 2882 2883std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering:: 2884parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const { 2885 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 2886 const TargetRegisterClass *RC; 2887 std::string Prefix; 2888 unsigned long long Reg; 2889 2890 std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg); 2891 2892 if (!R.first) 2893 return std::make_pair((unsigned)0, (const TargetRegisterClass*)0); 2894 2895 if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo. 2896 // No numeric characters follow "hi" or "lo". 2897 if (R.second) 2898 return std::make_pair((unsigned)0, (const TargetRegisterClass*)0); 2899 2900 RC = TRI->getRegClass(Prefix == "hi" ? 2901 Mips::HI32RegClassID : Mips::LO32RegClassID); 2902 return std::make_pair(*(RC->begin()), RC); 2903 } 2904 2905 if (!R.second) 2906 return std::make_pair((unsigned)0, (const TargetRegisterClass*)0); 2907 2908 if (Prefix == "$f") { // Parse $f0-$f31. 2909 // If the size of FP registers is 64-bit or Reg is an even number, select 2910 // the 64-bit register class. Otherwise, select the 32-bit register class. 2911 if (VT == MVT::Other) 2912 VT = (Subtarget->isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32; 2913 2914 RC = getRegClassFor(VT); 2915 2916 if (RC == &Mips::AFGR64RegClass) { 2917 assert(Reg % 2 == 0); 2918 Reg >>= 1; 2919 } 2920 } else if (Prefix == "$fcc") { // Parse $fcc0-$fcc7. 2921 RC = TRI->getRegClass(Mips::FCCRegClassID); 2922 } else { // Parse $0-$31. 2923 assert(Prefix == "$"); 2924 RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT); 2925 } 2926 2927 assert(Reg < RC->getNumRegs()); 2928 return std::make_pair(*(RC->begin() + Reg), RC); 2929} 2930 2931/// Given a register class constraint, like 'r', if this corresponds directly 2932/// to an LLVM register class, return a register of 0 and the register class 2933/// pointer. 2934std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering:: 2935getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const 2936{ 2937 if (Constraint.size() == 1) { 2938 switch (Constraint[0]) { 2939 case 'd': // Address register. Same as 'r' unless generating MIPS16 code. 2940 case 'y': // Same as 'r'. Exists for compatibility. 2941 case 'r': 2942 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { 2943 if (Subtarget->inMips16Mode()) 2944 return std::make_pair(0U, &Mips::CPU16RegsRegClass); 2945 return std::make_pair(0U, &Mips::GPR32RegClass); 2946 } 2947 if (VT == MVT::i64 && !HasMips64) 2948 return std::make_pair(0U, &Mips::GPR32RegClass); 2949 if (VT == MVT::i64 && HasMips64) 2950 return std::make_pair(0U, &Mips::GPR64RegClass); 2951 // This will generate an error message 2952 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 2953 case 'f': 2954 if (VT == MVT::f32) 2955 return std::make_pair(0U, &Mips::FGR32RegClass); 2956 if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) { 2957 if (Subtarget->isFP64bit()) 2958 return std::make_pair(0U, &Mips::FGR64RegClass); 2959 return std::make_pair(0U, &Mips::AFGR64RegClass); 2960 } 2961 break; 2962 case 'c': // register suitable for indirect jump 2963 if (VT == MVT::i32) 2964 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass); 2965 assert(VT == MVT::i64 && "Unexpected type."); 2966 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass); 2967 case 'l': // register suitable for indirect jump 2968 if (VT == MVT::i32) 2969 return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass); 2970 return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass); 2971 case 'x': // register suitable for indirect jump 2972 // Fixme: Not triggering the use of both hi and low 2973 // This will generate an error message 2974 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 2975 } 2976 } 2977 2978 std::pair<unsigned, const TargetRegisterClass *> R; 2979 R = parseRegForInlineAsmConstraint(Constraint, VT); 2980 2981 if (R.second) 2982 return R; 2983 2984 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 2985} 2986 2987/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 2988/// vector. If it is invalid, don't add anything to Ops. 2989void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 2990 std::string &Constraint, 2991 std::vector<SDValue>&Ops, 2992 SelectionDAG &DAG) const { 2993 SDValue Result(0, 0); 2994 2995 // Only support length 1 constraints for now. 2996 if (Constraint.length() > 1) return; 2997 2998 char ConstraintLetter = Constraint[0]; 2999 switch (ConstraintLetter) { 3000 default: break; // This will fall through to the generic implementation 3001 case 'I': // Signed 16 bit constant 3002 // If this fails, the parent routine will give an error 3003 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3004 EVT Type = Op.getValueType(); 3005 int64_t Val = C->getSExtValue(); 3006 if (isInt<16>(Val)) { 3007 Result = DAG.getTargetConstant(Val, Type); 3008 break; 3009 } 3010 } 3011 return; 3012 case 'J': // integer zero 3013 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3014 EVT Type = Op.getValueType(); 3015 int64_t Val = C->getZExtValue(); 3016 if (Val == 0) { 3017 Result = DAG.getTargetConstant(0, Type); 3018 break; 3019 } 3020 } 3021 return; 3022 case 'K': // unsigned 16 bit immediate 3023 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3024 EVT Type = Op.getValueType(); 3025 uint64_t Val = (uint64_t)C->getZExtValue(); 3026 if (isUInt<16>(Val)) { 3027 Result = DAG.getTargetConstant(Val, Type); 3028 break; 3029 } 3030 } 3031 return; 3032 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3033 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3034 EVT Type = Op.getValueType(); 3035 int64_t Val = C->getSExtValue(); 3036 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){ 3037 Result = DAG.getTargetConstant(Val, Type); 3038 break; 3039 } 3040 } 3041 return; 3042 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3043 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3044 EVT Type = Op.getValueType(); 3045 int64_t Val = C->getSExtValue(); 3046 if ((Val >= -65535) && (Val <= -1)) { 3047 Result = DAG.getTargetConstant(Val, Type); 3048 break; 3049 } 3050 } 3051 return; 3052 case 'O': // signed 15 bit immediate 3053 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3054 EVT Type = Op.getValueType(); 3055 int64_t Val = C->getSExtValue(); 3056 if ((isInt<15>(Val))) { 3057 Result = DAG.getTargetConstant(Val, Type); 3058 break; 3059 } 3060 } 3061 return; 3062 case 'P': // immediate in the range of 1 to 65535 (inclusive) 3063 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3064 EVT Type = Op.getValueType(); 3065 int64_t Val = C->getSExtValue(); 3066 if ((Val <= 65535) && (Val >= 1)) { 3067 Result = DAG.getTargetConstant(Val, Type); 3068 break; 3069 } 3070 } 3071 return; 3072 } 3073 3074 if (Result.getNode()) { 3075 Ops.push_back(Result); 3076 return; 3077 } 3078 3079 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 3080} 3081 3082bool MipsTargetLowering::isLegalAddressingMode(const AddrMode &AM, 3083 Type *Ty) const { 3084 // No global is ever allowed as a base. 3085 if (AM.BaseGV) 3086 return false; 3087 3088 switch (AM.Scale) { 3089 case 0: // "r+i" or just "i", depending on HasBaseReg. 3090 break; 3091 case 1: 3092 if (!AM.HasBaseReg) // allow "r+i". 3093 break; 3094 return false; // disallow "r+r" or "r+r+i". 3095 default: 3096 return false; 3097 } 3098 3099 return true; 3100} 3101 3102bool 3103MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 3104 // The Mips target isn't yet aware of offsets. 3105 return false; 3106} 3107 3108EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 3109 unsigned SrcAlign, 3110 bool IsMemset, bool ZeroMemset, 3111 bool MemcpyStrSrc, 3112 MachineFunction &MF) const { 3113 if (Subtarget->hasMips64()) 3114 return MVT::i64; 3115 3116 return MVT::i32; 3117} 3118 3119bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3120 if (VT != MVT::f32 && VT != MVT::f64) 3121 return false; 3122 if (Imm.isNegZero()) 3123 return false; 3124 return Imm.isZero(); 3125} 3126 3127unsigned MipsTargetLowering::getJumpTableEncoding() const { 3128 if (IsN64) 3129 return MachineJumpTableInfo::EK_GPRel64BlockAddress; 3130 3131 return TargetLowering::getJumpTableEncoding(); 3132} 3133 3134/// This function returns true if CallSym is a long double emulation routine. 3135static bool isF128SoftLibCall(const char *CallSym) { 3136 const char *const LibCalls[] = 3137 {"__addtf3", "__divtf3", "__eqtf2", "__extenddftf2", "__extendsftf2", 3138 "__fixtfdi", "__fixtfsi", "__fixtfti", "__fixunstfdi", "__fixunstfsi", 3139 "__fixunstfti", "__floatditf", "__floatsitf", "__floattitf", 3140 "__floatunditf", "__floatunsitf", "__floatuntitf", "__getf2", "__gttf2", 3141 "__letf2", "__lttf2", "__multf3", "__netf2", "__powitf2", "__subtf3", 3142 "__trunctfdf2", "__trunctfsf2", "__unordtf2", 3143 "ceill", "copysignl", "cosl", "exp2l", "expl", "floorl", "fmal", "fmodl", 3144 "log10l", "log2l", "logl", "nearbyintl", "powl", "rintl", "sinl", "sqrtl", 3145 "truncl"}; 3146 3147 const char *const *End = LibCalls + array_lengthof(LibCalls); 3148 3149 // Check that LibCalls is sorted alphabetically. 3150 MipsTargetLowering::LTStr Comp; 3151 3152#ifndef NDEBUG 3153 for (const char *const *I = LibCalls; I < End - 1; ++I) 3154 assert(Comp(*I, *(I + 1))); 3155#endif 3156 3157 return std::binary_search(LibCalls, End, CallSym, Comp); 3158} 3159 3160/// This function returns true if Ty is fp128 or i128 which was originally a 3161/// fp128. 3162static bool originalTypeIsF128(const Type *Ty, const SDNode *CallNode) { 3163 if (Ty->isFP128Ty()) 3164 return true; 3165 3166 const ExternalSymbolSDNode *ES = 3167 dyn_cast_or_null<const ExternalSymbolSDNode>(CallNode); 3168 3169 // If the Ty is i128 and the function being called is a long double emulation 3170 // routine, then the original type is f128. 3171 return (ES && Ty->isIntegerTy(128) && isF128SoftLibCall(ES->getSymbol())); 3172} 3173 3174MipsTargetLowering::MipsCC::SpecialCallingConvType 3175 MipsTargetLowering::getSpecialCallingConv(SDValue Callee) const { 3176 MipsCC::SpecialCallingConvType SpecialCallingConv = 3177 MipsCC::NoSpecialCallingConv;; 3178 if (Subtarget->inMips16HardFloat()) { 3179 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 3180 llvm::StringRef Sym = G->getGlobal()->getName(); 3181 Function *F = G->getGlobal()->getParent()->getFunction(Sym); 3182 if (F->hasFnAttribute("__Mips16RetHelper")) { 3183 SpecialCallingConv = MipsCC::Mips16RetHelperConv; 3184 } 3185 } 3186 } 3187 return SpecialCallingConv; 3188} 3189 3190MipsTargetLowering::MipsCC::MipsCC( 3191 CallingConv::ID CC, bool IsO32_, bool IsFP64_, CCState &Info, 3192 MipsCC::SpecialCallingConvType SpecialCallingConv_) 3193 : CCInfo(Info), CallConv(CC), IsO32(IsO32_), IsFP64(IsFP64_), 3194 SpecialCallingConv(SpecialCallingConv_){ 3195 // Pre-allocate reserved argument area. 3196 CCInfo.AllocateStack(reservedArgArea(), 1); 3197} 3198 3199 3200void MipsTargetLowering::MipsCC:: 3201analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Args, 3202 bool IsVarArg, bool IsSoftFloat, const SDNode *CallNode, 3203 std::vector<ArgListEntry> &FuncArgs) { 3204 assert((CallConv != CallingConv::Fast || !IsVarArg) && 3205 "CallingConv::Fast shouldn't be used for vararg functions."); 3206 3207 unsigned NumOpnds = Args.size(); 3208 llvm::CCAssignFn *FixedFn = fixedArgFn(), *VarFn = varArgFn(); 3209 3210 for (unsigned I = 0; I != NumOpnds; ++I) { 3211 MVT ArgVT = Args[I].VT; 3212 ISD::ArgFlagsTy ArgFlags = Args[I].Flags; 3213 bool R; 3214 3215 if (ArgFlags.isByVal()) { 3216 handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags); 3217 continue; 3218 } 3219 3220 if (IsVarArg && !Args[I].IsFixed) 3221 R = VarFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo); 3222 else { 3223 MVT RegVT = getRegVT(ArgVT, FuncArgs[Args[I].OrigArgIndex].Ty, CallNode, 3224 IsSoftFloat); 3225 R = FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, CCInfo); 3226 } 3227 3228 if (R) { 3229#ifndef NDEBUG 3230 dbgs() << "Call operand #" << I << " has unhandled type " 3231 << EVT(ArgVT).getEVTString(); 3232#endif 3233 llvm_unreachable(0); 3234 } 3235 } 3236} 3237 3238void MipsTargetLowering::MipsCC:: 3239analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Args, 3240 bool IsSoftFloat, Function::const_arg_iterator FuncArg) { 3241 unsigned NumArgs = Args.size(); 3242 llvm::CCAssignFn *FixedFn = fixedArgFn(); 3243 unsigned CurArgIdx = 0; 3244 3245 for (unsigned I = 0; I != NumArgs; ++I) { 3246 MVT ArgVT = Args[I].VT; 3247 ISD::ArgFlagsTy ArgFlags = Args[I].Flags; 3248 std::advance(FuncArg, Args[I].OrigArgIndex - CurArgIdx); 3249 CurArgIdx = Args[I].OrigArgIndex; 3250 3251 if (ArgFlags.isByVal()) { 3252 handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags); 3253 continue; 3254 } 3255 3256 MVT RegVT = getRegVT(ArgVT, FuncArg->getType(), 0, IsSoftFloat); 3257 3258 if (!FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, CCInfo)) 3259 continue; 3260 3261#ifndef NDEBUG 3262 dbgs() << "Formal Arg #" << I << " has unhandled type " 3263 << EVT(ArgVT).getEVTString(); 3264#endif 3265 llvm_unreachable(0); 3266 } 3267} 3268 3269template<typename Ty> 3270void MipsTargetLowering::MipsCC:: 3271analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat, 3272 const SDNode *CallNode, const Type *RetTy) const { 3273 CCAssignFn *Fn; 3274 3275 if (IsSoftFloat && originalTypeIsF128(RetTy, CallNode)) 3276 Fn = RetCC_F128Soft; 3277 else 3278 Fn = RetCC_Mips; 3279 3280 for (unsigned I = 0, E = RetVals.size(); I < E; ++I) { 3281 MVT VT = RetVals[I].VT; 3282 ISD::ArgFlagsTy Flags = RetVals[I].Flags; 3283 MVT RegVT = this->getRegVT(VT, RetTy, CallNode, IsSoftFloat); 3284 3285 if (Fn(I, VT, RegVT, CCValAssign::Full, Flags, this->CCInfo)) { 3286#ifndef NDEBUG 3287 dbgs() << "Call result #" << I << " has unhandled type " 3288 << EVT(VT).getEVTString() << '\n'; 3289#endif 3290 llvm_unreachable(0); 3291 } 3292 } 3293} 3294 3295void MipsTargetLowering::MipsCC:: 3296analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, bool IsSoftFloat, 3297 const SDNode *CallNode, const Type *RetTy) const { 3298 analyzeReturn(Ins, IsSoftFloat, CallNode, RetTy); 3299} 3300 3301void MipsTargetLowering::MipsCC:: 3302analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsSoftFloat, 3303 const Type *RetTy) const { 3304 analyzeReturn(Outs, IsSoftFloat, 0, RetTy); 3305} 3306 3307void MipsTargetLowering::MipsCC::handleByValArg(unsigned ValNo, MVT ValVT, 3308 MVT LocVT, 3309 CCValAssign::LocInfo LocInfo, 3310 ISD::ArgFlagsTy ArgFlags) { 3311 assert(ArgFlags.getByValSize() && "Byval argument's size shouldn't be 0."); 3312 3313 struct ByValArgInfo ByVal; 3314 unsigned RegSize = regSize(); 3315 unsigned ByValSize = RoundUpToAlignment(ArgFlags.getByValSize(), RegSize); 3316 unsigned Align = std::min(std::max(ArgFlags.getByValAlign(), RegSize), 3317 RegSize * 2); 3318 3319 if (useRegsForByval()) 3320 allocateRegs(ByVal, ByValSize, Align); 3321 3322 // Allocate space on caller's stack. 3323 ByVal.Address = CCInfo.AllocateStack(ByValSize - RegSize * ByVal.NumRegs, 3324 Align); 3325 CCInfo.addLoc(CCValAssign::getMem(ValNo, ValVT, ByVal.Address, LocVT, 3326 LocInfo)); 3327 ByValArgs.push_back(ByVal); 3328} 3329 3330unsigned MipsTargetLowering::MipsCC::numIntArgRegs() const { 3331 return IsO32 ? array_lengthof(O32IntRegs) : array_lengthof(Mips64IntRegs); 3332} 3333 3334unsigned MipsTargetLowering::MipsCC::reservedArgArea() const { 3335 return (IsO32 && (CallConv != CallingConv::Fast)) ? 16 : 0; 3336} 3337 3338const uint16_t *MipsTargetLowering::MipsCC::intArgRegs() const { 3339 return IsO32 ? O32IntRegs : Mips64IntRegs; 3340} 3341 3342llvm::CCAssignFn *MipsTargetLowering::MipsCC::fixedArgFn() const { 3343 if (CallConv == CallingConv::Fast) 3344 return CC_Mips_FastCC; 3345 3346 if (SpecialCallingConv == Mips16RetHelperConv) 3347 return CC_Mips16RetHelper; 3348 return IsO32 ? (IsFP64 ? CC_MipsO32_FP64 : CC_MipsO32_FP32) : CC_MipsN; 3349} 3350 3351llvm::CCAssignFn *MipsTargetLowering::MipsCC::varArgFn() const { 3352 return IsO32 ? (IsFP64 ? CC_MipsO32_FP64 : CC_MipsO32_FP32) : CC_MipsN_VarArg; 3353} 3354 3355const uint16_t *MipsTargetLowering::MipsCC::shadowRegs() const { 3356 return IsO32 ? O32IntRegs : Mips64DPRegs; 3357} 3358 3359void MipsTargetLowering::MipsCC::allocateRegs(ByValArgInfo &ByVal, 3360 unsigned ByValSize, 3361 unsigned Align) { 3362 unsigned RegSize = regSize(), NumIntArgRegs = numIntArgRegs(); 3363 const uint16_t *IntArgRegs = intArgRegs(), *ShadowRegs = shadowRegs(); 3364 assert(!(ByValSize % RegSize) && !(Align % RegSize) && 3365 "Byval argument's size and alignment should be a multiple of" 3366 "RegSize."); 3367 3368 ByVal.FirstIdx = CCInfo.getFirstUnallocated(IntArgRegs, NumIntArgRegs); 3369 3370 // If Align > RegSize, the first arg register must be even. 3371 if ((Align > RegSize) && (ByVal.FirstIdx % 2)) { 3372 CCInfo.AllocateReg(IntArgRegs[ByVal.FirstIdx], ShadowRegs[ByVal.FirstIdx]); 3373 ++ByVal.FirstIdx; 3374 } 3375 3376 // Mark the registers allocated. 3377 for (unsigned I = ByVal.FirstIdx; ByValSize && (I < NumIntArgRegs); 3378 ByValSize -= RegSize, ++I, ++ByVal.NumRegs) 3379 CCInfo.AllocateReg(IntArgRegs[I], ShadowRegs[I]); 3380} 3381 3382MVT MipsTargetLowering::MipsCC::getRegVT(MVT VT, const Type *OrigTy, 3383 const SDNode *CallNode, 3384 bool IsSoftFloat) const { 3385 if (IsSoftFloat || IsO32) 3386 return VT; 3387 3388 // Check if the original type was fp128. 3389 if (originalTypeIsF128(OrigTy, CallNode)) { 3390 assert(VT == MVT::i64); 3391 return MVT::f64; 3392 } 3393 3394 return VT; 3395} 3396 3397void MipsTargetLowering:: 3398copyByValRegs(SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains, 3399 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags, 3400 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg, 3401 const MipsCC &CC, const ByValArgInfo &ByVal) const { 3402 MachineFunction &MF = DAG.getMachineFunction(); 3403 MachineFrameInfo *MFI = MF.getFrameInfo(); 3404 unsigned RegAreaSize = ByVal.NumRegs * CC.regSize(); 3405 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize); 3406 int FrameObjOffset; 3407 3408 if (RegAreaSize) 3409 FrameObjOffset = (int)CC.reservedArgArea() - 3410 (int)((CC.numIntArgRegs() - ByVal.FirstIdx) * CC.regSize()); 3411 else 3412 FrameObjOffset = ByVal.Address; 3413 3414 // Create frame object. 3415 EVT PtrTy = getPointerTy(); 3416 int FI = MFI->CreateFixedObject(FrameObjSize, FrameObjOffset, true); 3417 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 3418 InVals.push_back(FIN); 3419 3420 if (!ByVal.NumRegs) 3421 return; 3422 3423 // Copy arg registers. 3424 MVT RegTy = MVT::getIntegerVT(CC.regSize() * 8); 3425 const TargetRegisterClass *RC = getRegClassFor(RegTy); 3426 3427 for (unsigned I = 0; I < ByVal.NumRegs; ++I) { 3428 unsigned ArgReg = CC.intArgRegs()[ByVal.FirstIdx + I]; 3429 unsigned VReg = addLiveIn(MF, ArgReg, RC); 3430 unsigned Offset = I * CC.regSize(); 3431 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN, 3432 DAG.getConstant(Offset, PtrTy)); 3433 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy), 3434 StorePtr, MachinePointerInfo(FuncArg, Offset), 3435 false, false, 0); 3436 OutChains.push_back(Store); 3437 } 3438} 3439 3440// Copy byVal arg to registers and stack. 3441void MipsTargetLowering:: 3442passByValArg(SDValue Chain, SDLoc DL, 3443 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 3444 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, 3445 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, 3446 const MipsCC &CC, const ByValArgInfo &ByVal, 3447 const ISD::ArgFlagsTy &Flags, bool isLittle) const { 3448 unsigned ByValSize = Flags.getByValSize(); 3449 unsigned Offset = 0; // Offset in # of bytes from the beginning of struct. 3450 unsigned RegSize = CC.regSize(); 3451 unsigned Alignment = std::min(Flags.getByValAlign(), RegSize); 3452 EVT PtrTy = getPointerTy(), RegTy = MVT::getIntegerVT(RegSize * 8); 3453 3454 if (ByVal.NumRegs) { 3455 const uint16_t *ArgRegs = CC.intArgRegs(); 3456 bool LeftoverBytes = (ByVal.NumRegs * RegSize > ByValSize); 3457 unsigned I = 0; 3458 3459 // Copy words to registers. 3460 for (; I < ByVal.NumRegs - LeftoverBytes; ++I, Offset += RegSize) { 3461 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3462 DAG.getConstant(Offset, PtrTy)); 3463 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr, 3464 MachinePointerInfo(), false, false, false, 3465 Alignment); 3466 MemOpChains.push_back(LoadVal.getValue(1)); 3467 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I]; 3468 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal)); 3469 } 3470 3471 // Return if the struct has been fully copied. 3472 if (ByValSize == Offset) 3473 return; 3474 3475 // Copy the remainder of the byval argument with sub-word loads and shifts. 3476 if (LeftoverBytes) { 3477 assert((ByValSize > Offset) && (ByValSize < Offset + RegSize) && 3478 "Size of the remainder should be smaller than RegSize."); 3479 SDValue Val; 3480 3481 for (unsigned LoadSize = RegSize / 2, TotalSizeLoaded = 0; 3482 Offset < ByValSize; LoadSize /= 2) { 3483 unsigned RemSize = ByValSize - Offset; 3484 3485 if (RemSize < LoadSize) 3486 continue; 3487 3488 // Load subword. 3489 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3490 DAG.getConstant(Offset, PtrTy)); 3491 SDValue LoadVal = 3492 DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, 3493 MachinePointerInfo(), MVT::getIntegerVT(LoadSize * 8), 3494 false, false, Alignment); 3495 MemOpChains.push_back(LoadVal.getValue(1)); 3496 3497 // Shift the loaded value. 3498 unsigned Shamt; 3499 3500 if (isLittle) 3501 Shamt = TotalSizeLoaded; 3502 else 3503 Shamt = (RegSize - (TotalSizeLoaded + LoadSize)) * 8; 3504 3505 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal, 3506 DAG.getConstant(Shamt, MVT::i32)); 3507 3508 if (Val.getNode()) 3509 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift); 3510 else 3511 Val = Shift; 3512 3513 Offset += LoadSize; 3514 TotalSizeLoaded += LoadSize; 3515 Alignment = std::min(Alignment, LoadSize); 3516 } 3517 3518 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I]; 3519 RegsToPass.push_back(std::make_pair(ArgReg, Val)); 3520 return; 3521 } 3522 } 3523 3524 // Copy remainder of byval arg to it with memcpy. 3525 unsigned MemCpySize = ByValSize - Offset; 3526 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3527 DAG.getConstant(Offset, PtrTy)); 3528 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr, 3529 DAG.getIntPtrConstant(ByVal.Address)); 3530 Chain = DAG.getMemcpy(Chain, DL, Dst, Src, DAG.getConstant(MemCpySize, PtrTy), 3531 Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false, 3532 MachinePointerInfo(0), MachinePointerInfo(0)); 3533 MemOpChains.push_back(Chain); 3534} 3535 3536void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains, 3537 const MipsCC &CC, SDValue Chain, 3538 SDLoc DL, SelectionDAG &DAG) const { 3539 unsigned NumRegs = CC.numIntArgRegs(); 3540 const uint16_t *ArgRegs = CC.intArgRegs(); 3541 const CCState &CCInfo = CC.getCCInfo(); 3542 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumRegs); 3543 unsigned RegSize = CC.regSize(); 3544 MVT RegTy = MVT::getIntegerVT(RegSize * 8); 3545 const TargetRegisterClass *RC = getRegClassFor(RegTy); 3546 MachineFunction &MF = DAG.getMachineFunction(); 3547 MachineFrameInfo *MFI = MF.getFrameInfo(); 3548 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3549 3550 // Offset of the first variable argument from stack pointer. 3551 int VaArgOffset; 3552 3553 if (NumRegs == Idx) 3554 VaArgOffset = RoundUpToAlignment(CCInfo.getNextStackOffset(), RegSize); 3555 else 3556 VaArgOffset = (int)CC.reservedArgArea() - (int)(RegSize * (NumRegs - Idx)); 3557 3558 // Record the frame index of the first variable argument 3559 // which is a value necessary to VASTART. 3560 int FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true); 3561 MipsFI->setVarArgsFrameIndex(FI); 3562 3563 // Copy the integer registers that have not been used for argument passing 3564 // to the argument register save area. For O32, the save area is allocated 3565 // in the caller's stack frame, while for N32/64, it is allocated in the 3566 // callee's stack frame. 3567 for (unsigned I = Idx; I < NumRegs; ++I, VaArgOffset += RegSize) { 3568 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC); 3569 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy); 3570 FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true); 3571 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy()); 3572 SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff, 3573 MachinePointerInfo(), false, false, 0); 3574 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(0); 3575 OutChains.push_back(Store); 3576 } 3577} 3578