MipsISelLowering.cpp revision b7656a9cc4bf36752df38e7c02b910c9390b9c39
1//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that Mips uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14#define DEBUG_TYPE "mips-lower" 15#include <set> 16#include "MipsISelLowering.h" 17#include "InstPrinter/MipsInstPrinter.h" 18#include "MCTargetDesc/MipsBaseInfo.h" 19#include "MipsMachineFunction.h" 20#include "MipsSubtarget.h" 21#include "MipsTargetMachine.h" 22#include "MipsTargetObjectFile.h" 23#include "llvm/ADT/Statistic.h" 24#include "llvm/CodeGen/CallingConvLower.h" 25#include "llvm/CodeGen/MachineFrameInfo.h" 26#include "llvm/CodeGen/MachineFunction.h" 27#include "llvm/CodeGen/MachineInstrBuilder.h" 28#include "llvm/CodeGen/MachineRegisterInfo.h" 29#include "llvm/CodeGen/SelectionDAGISel.h" 30#include "llvm/CodeGen/ValueTypes.h" 31#include "llvm/IR/CallingConv.h" 32#include "llvm/IR/DerivedTypes.h" 33#include "llvm/IR/GlobalVariable.h" 34#include "llvm/IR/Intrinsics.h" 35#include "llvm/Support/CommandLine.h" 36#include "llvm/Support/Debug.h" 37#include "llvm/Support/ErrorHandling.h" 38#include "llvm/Support/raw_ostream.h" 39 40using namespace llvm; 41 42STATISTIC(NumTailCalls, "Number of tail calls"); 43 44static cl::opt<bool> 45EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden, 46 cl::desc("MIPS: Enable tail calls."), cl::init(false)); 47 48static cl::opt<bool> 49LargeGOT("mxgot", cl::Hidden, 50 cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false)); 51 52static cl::opt<bool> 53Mips16HardFloat("mips16-hard-float", cl::NotHidden, 54 cl::desc("MIPS: mips16 hard float enable."), 55 cl::init(false)); 56 57static cl::opt<bool> DontExpandCondPseudos16( 58 "mips16-dont-expand-cond-pseudo", 59 cl::init(false), 60 cl::desc("Dont expand conditional move related " 61 "pseudos for Mips 16"), 62 cl::Hidden); 63 64 65static const uint16_t O32IntRegs[4] = { 66 Mips::A0, Mips::A1, Mips::A2, Mips::A3 67}; 68 69static const uint16_t Mips64IntRegs[8] = { 70 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, 71 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64 72}; 73 74static const uint16_t Mips64DPRegs[8] = { 75 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, 76 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64 77}; 78 79// If I is a shifted mask, set the size (Size) and the first bit of the 80// mask (Pos), and return true. 81// For example, if I is 0x003ff800, (Pos, Size) = (11, 11). 82static bool IsShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { 83 if (!isShiftedMask_64(I)) 84 return false; 85 86 Size = CountPopulation_64(I); 87 Pos = CountTrailingZeros_64(I); 88 return true; 89} 90 91static SDValue GetGlobalReg(SelectionDAG &DAG, EVT Ty) { 92 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>(); 93 return DAG.getRegister(FI->getGlobalBaseReg(), Ty); 94} 95 96static SDValue getTargetNode(SDValue Op, SelectionDAG &DAG, unsigned Flag) { 97 EVT Ty = Op.getValueType(); 98 99 if (GlobalAddressSDNode *N = dyn_cast<GlobalAddressSDNode>(Op)) 100 return DAG.getTargetGlobalAddress(N->getGlobal(), Op.getDebugLoc(), Ty, 0, 101 Flag); 102 if (ExternalSymbolSDNode *N = dyn_cast<ExternalSymbolSDNode>(Op)) 103 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag); 104 if (BlockAddressSDNode *N = dyn_cast<BlockAddressSDNode>(Op)) 105 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag); 106 if (JumpTableSDNode *N = dyn_cast<JumpTableSDNode>(Op)) 107 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag); 108 if (ConstantPoolSDNode *N = dyn_cast<ConstantPoolSDNode>(Op)) 109 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(), 110 N->getOffset(), Flag); 111 112 llvm_unreachable("Unexpected node type."); 113 return SDValue(); 114} 115 116static SDValue getAddrNonPIC(SDValue Op, SelectionDAG &DAG) { 117 DebugLoc DL = Op.getDebugLoc(); 118 EVT Ty = Op.getValueType(); 119 SDValue Hi = getTargetNode(Op, DAG, MipsII::MO_ABS_HI); 120 SDValue Lo = getTargetNode(Op, DAG, MipsII::MO_ABS_LO); 121 return DAG.getNode(ISD::ADD, DL, Ty, 122 DAG.getNode(MipsISD::Hi, DL, Ty, Hi), 123 DAG.getNode(MipsISD::Lo, DL, Ty, Lo)); 124} 125 126static SDValue getAddrLocal(SDValue Op, SelectionDAG &DAG, bool HasMips64) { 127 DebugLoc DL = Op.getDebugLoc(); 128 EVT Ty = Op.getValueType(); 129 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT; 130 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, GetGlobalReg(DAG, Ty), 131 getTargetNode(Op, DAG, GOTFlag)); 132 SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT, 133 MachinePointerInfo::getGOT(), false, false, false, 134 0); 135 unsigned LoFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO; 136 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty, getTargetNode(Op, DAG, LoFlag)); 137 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo); 138} 139 140static SDValue getAddrGlobal(SDValue Op, SelectionDAG &DAG, unsigned Flag) { 141 DebugLoc DL = Op.getDebugLoc(); 142 EVT Ty = Op.getValueType(); 143 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, GetGlobalReg(DAG, Ty), 144 getTargetNode(Op, DAG, Flag)); 145 return DAG.getLoad(Ty, DL, DAG.getEntryNode(), Tgt, 146 MachinePointerInfo::getGOT(), false, false, false, 0); 147} 148 149static SDValue getAddrGlobalLargeGOT(SDValue Op, SelectionDAG &DAG, 150 unsigned HiFlag, unsigned LoFlag) { 151 DebugLoc DL = Op.getDebugLoc(); 152 EVT Ty = Op.getValueType(); 153 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, Ty, getTargetNode(Op, DAG, HiFlag)); 154 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, GetGlobalReg(DAG, Ty)); 155 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi, 156 getTargetNode(Op, DAG, LoFlag)); 157 return DAG.getLoad(Ty, DL, DAG.getEntryNode(), Wrapper, 158 MachinePointerInfo::getGOT(), false, false, false, 0); 159} 160 161const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 162 switch (Opcode) { 163 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 164 case MipsISD::TailCall: return "MipsISD::TailCall"; 165 case MipsISD::Hi: return "MipsISD::Hi"; 166 case MipsISD::Lo: return "MipsISD::Lo"; 167 case MipsISD::GPRel: return "MipsISD::GPRel"; 168 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; 169 case MipsISD::Ret: return "MipsISD::Ret"; 170 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN"; 171 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 172 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 173 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 174 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 175 case MipsISD::FPRound: return "MipsISD::FPRound"; 176 case MipsISD::MAdd: return "MipsISD::MAdd"; 177 case MipsISD::MAddu: return "MipsISD::MAddu"; 178 case MipsISD::MSub: return "MipsISD::MSub"; 179 case MipsISD::MSubu: return "MipsISD::MSubu"; 180 case MipsISD::DivRem: return "MipsISD::DivRem"; 181 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 182 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 183 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 184 case MipsISD::Wrapper: return "MipsISD::Wrapper"; 185 case MipsISD::Sync: return "MipsISD::Sync"; 186 case MipsISD::Ext: return "MipsISD::Ext"; 187 case MipsISD::Ins: return "MipsISD::Ins"; 188 case MipsISD::LWL: return "MipsISD::LWL"; 189 case MipsISD::LWR: return "MipsISD::LWR"; 190 case MipsISD::SWL: return "MipsISD::SWL"; 191 case MipsISD::SWR: return "MipsISD::SWR"; 192 case MipsISD::LDL: return "MipsISD::LDL"; 193 case MipsISD::LDR: return "MipsISD::LDR"; 194 case MipsISD::SDL: return "MipsISD::SDL"; 195 case MipsISD::SDR: return "MipsISD::SDR"; 196 case MipsISD::EXTP: return "MipsISD::EXTP"; 197 case MipsISD::EXTPDP: return "MipsISD::EXTPDP"; 198 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H"; 199 case MipsISD::EXTR_W: return "MipsISD::EXTR_W"; 200 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W"; 201 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W"; 202 case MipsISD::SHILO: return "MipsISD::SHILO"; 203 case MipsISD::MTHLIP: return "MipsISD::MTHLIP"; 204 case MipsISD::MULT: return "MipsISD::MULT"; 205 case MipsISD::MULTU: return "MipsISD::MULTU"; 206 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP"; 207 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP"; 208 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP"; 209 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP"; 210 default: return NULL; 211 } 212} 213 214namespace { 215 struct ltstr { 216 bool operator()(const char *s1, const char *s2) const 217 { 218 return strcmp(s1, s2) < 0; 219 } 220 }; 221 222 std::set<const char*, ltstr> noHelperNeeded; 223} 224 225void MipsTargetLowering::SetMips16LibcallName 226 (RTLIB::Libcall l, const char *Name) { 227 setLibcallName(l, Name); 228 noHelperNeeded.insert(Name); 229} 230 231void MipsTargetLowering::setMips16HardFloatLibCalls() { 232 SetMips16LibcallName(RTLIB::ADD_F32, "__mips16_addsf3"); 233 SetMips16LibcallName(RTLIB::ADD_F64, "__mips16_adddf3"); 234 SetMips16LibcallName(RTLIB::SUB_F32, "__mips16_subsf3"); 235 SetMips16LibcallName(RTLIB::SUB_F64, "__mips16_subdf3"); 236 SetMips16LibcallName(RTLIB::MUL_F32, "__mips16_mulsf3"); 237 SetMips16LibcallName(RTLIB::MUL_F64, "__mips16_muldf3"); 238 SetMips16LibcallName(RTLIB::DIV_F32, "__mips16_divsf3"); 239 SetMips16LibcallName(RTLIB::DIV_F64, "__mips16_divdf3"); 240 SetMips16LibcallName(RTLIB::FPEXT_F32_F64, "__mips16_extendsfdf2"); 241 SetMips16LibcallName(RTLIB::FPROUND_F64_F32, "__mips16_truncdfsf2"); 242 SetMips16LibcallName(RTLIB::FPTOSINT_F32_I32, "__mips16_fix_truncsfsi"); 243 SetMips16LibcallName(RTLIB::FPTOSINT_F64_I32, "__mips16_fix_truncdfsi"); 244 SetMips16LibcallName(RTLIB::SINTTOFP_I32_F32, "__mips16_floatsisf"); 245 SetMips16LibcallName(RTLIB::SINTTOFP_I32_F64, "__mips16_floatsidf"); 246 SetMips16LibcallName(RTLIB::UINTTOFP_I32_F32, "__mips16_floatunsisf"); 247 SetMips16LibcallName(RTLIB::UINTTOFP_I32_F64, "__mips16_floatunsidf"); 248 SetMips16LibcallName(RTLIB::OEQ_F32, "__mips16_eqsf2"); 249 SetMips16LibcallName(RTLIB::OEQ_F64, "__mips16_eqdf2"); 250 SetMips16LibcallName(RTLIB::UNE_F32, "__mips16_nesf2"); 251 SetMips16LibcallName(RTLIB::UNE_F64, "__mips16_nedf2"); 252 SetMips16LibcallName(RTLIB::OGE_F32, "__mips16_gesf2"); 253 SetMips16LibcallName(RTLIB::OGE_F64, "__mips16_gedf2"); 254 SetMips16LibcallName(RTLIB::OLT_F32, "__mips16_ltsf2"); 255 SetMips16LibcallName(RTLIB::OLT_F64, "__mips16_ltdf2"); 256 SetMips16LibcallName(RTLIB::OLE_F32, "__mips16_lesf2"); 257 SetMips16LibcallName(RTLIB::OLE_F64, "__mips16_ledf2"); 258 SetMips16LibcallName(RTLIB::OGT_F32, "__mips16_gtsf2"); 259 SetMips16LibcallName(RTLIB::OGT_F64, "__mips16_gtdf2"); 260 SetMips16LibcallName(RTLIB::UO_F32, "__mips16_unordsf2"); 261 SetMips16LibcallName(RTLIB::UO_F64, "__mips16_unorddf2"); 262 SetMips16LibcallName(RTLIB::O_F32, "__mips16_unordsf2"); 263 SetMips16LibcallName(RTLIB::O_F64, "__mips16_unorddf2"); 264} 265 266MipsTargetLowering:: 267MipsTargetLowering(MipsTargetMachine &TM) 268 : TargetLowering(TM, new MipsTargetObjectFile()), 269 Subtarget(&TM.getSubtarget<MipsSubtarget>()), 270 HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()), 271 IsO32(Subtarget->isABI_O32()) { 272 273 // Mips does not have i1 type, so use i32 for 274 // setcc operations results (slt, sgt, ...). 275 setBooleanContents(ZeroOrOneBooleanContent); 276 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct? 277 278 // Set up the register classes 279 addRegisterClass(MVT::i32, &Mips::CPURegsRegClass); 280 281 if (HasMips64) 282 addRegisterClass(MVT::i64, &Mips::CPU64RegsRegClass); 283 284 if (Subtarget->inMips16Mode()) { 285 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass); 286 if (Mips16HardFloat) 287 setMips16HardFloatLibCalls(); 288 } 289 290 if (Subtarget->hasDSP()) { 291 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8}; 292 293 for (unsigned i = 0; i < array_lengthof(VecTys); ++i) { 294 addRegisterClass(VecTys[i], &Mips::DSPRegsRegClass); 295 296 // Expand all builtin opcodes. 297 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc) 298 setOperationAction(Opc, VecTys[i], Expand); 299 300 setOperationAction(ISD::LOAD, VecTys[i], Legal); 301 setOperationAction(ISD::STORE, VecTys[i], Legal); 302 setOperationAction(ISD::BITCAST, VecTys[i], Legal); 303 } 304 } 305 306 if (!TM.Options.UseSoftFloat) { 307 addRegisterClass(MVT::f32, &Mips::FGR32RegClass); 308 309 // When dealing with single precision only, use libcalls 310 if (!Subtarget->isSingleFloat()) { 311 if (HasMips64) 312 addRegisterClass(MVT::f64, &Mips::FGR64RegClass); 313 else 314 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass); 315 } 316 } 317 318 // Load extented operations for i1 types must be promoted 319 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 320 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 321 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 322 323 // MIPS doesn't have extending float->double load/store 324 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 325 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 326 327 // Used by legalize types to correctly generate the setcc result. 328 // Without this, every float setcc comes with a AND/OR with the result, 329 // we don't want this, since the fpcmp result goes to a flag register, 330 // which is used implicitly by brcond and select operations. 331 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 332 333 // Mips Custom Operations 334 setOperationAction(ISD::BR_JT, MVT::Other, Custom); 335 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 336 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 337 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 338 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 339 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 340 setOperationAction(ISD::SELECT, MVT::f32, Custom); 341 setOperationAction(ISD::SELECT, MVT::f64, Custom); 342 setOperationAction(ISD::SELECT, MVT::i32, Custom); 343 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 344 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 345 setOperationAction(ISD::SETCC, MVT::f32, Custom); 346 setOperationAction(ISD::SETCC, MVT::f64, Custom); 347 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 348 setOperationAction(ISD::VASTART, MVT::Other, Custom); 349 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 350 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 351 if (Subtarget->inMips16Mode()) { 352 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); 353 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand); 354 } 355 else { 356 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom); 357 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); 358 } 359 if (!Subtarget->inMips16Mode()) { 360 setOperationAction(ISD::LOAD, MVT::i32, Custom); 361 setOperationAction(ISD::STORE, MVT::i32, Custom); 362 } 363 364 if (!TM.Options.NoNaNsFPMath) { 365 setOperationAction(ISD::FABS, MVT::f32, Custom); 366 setOperationAction(ISD::FABS, MVT::f64, Custom); 367 } 368 369 if (HasMips64) { 370 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 371 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 372 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 373 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 374 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 375 setOperationAction(ISD::SELECT, MVT::i64, Custom); 376 setOperationAction(ISD::LOAD, MVT::i64, Custom); 377 setOperationAction(ISD::STORE, MVT::i64, Custom); 378 } 379 380 if (!HasMips64) { 381 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 382 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 383 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 384 } 385 386 setOperationAction(ISD::ADD, MVT::i32, Custom); 387 if (HasMips64) 388 setOperationAction(ISD::ADD, MVT::i64, Custom); 389 390 setOperationAction(ISD::SDIV, MVT::i32, Expand); 391 setOperationAction(ISD::SREM, MVT::i32, Expand); 392 setOperationAction(ISD::UDIV, MVT::i32, Expand); 393 setOperationAction(ISD::UREM, MVT::i32, Expand); 394 setOperationAction(ISD::SDIV, MVT::i64, Expand); 395 setOperationAction(ISD::SREM, MVT::i64, Expand); 396 setOperationAction(ISD::UDIV, MVT::i64, Expand); 397 setOperationAction(ISD::UREM, MVT::i64, Expand); 398 399 // Operations not directly supported by Mips. 400 setOperationAction(ISD::BR_CC, MVT::Other, Expand); 401 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 402 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 403 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 404 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 405 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 406 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 407 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 408 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 409 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 410 setOperationAction(ISD::CTTZ, MVT::i64, Expand); 411 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 412 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 413 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 414 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 415 setOperationAction(ISD::ROTL, MVT::i32, Expand); 416 setOperationAction(ISD::ROTL, MVT::i64, Expand); 417 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 418 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 419 420 if (!Subtarget->hasMips32r2()) 421 setOperationAction(ISD::ROTR, MVT::i32, Expand); 422 423 if (!Subtarget->hasMips64r2()) 424 setOperationAction(ISD::ROTR, MVT::i64, Expand); 425 426 setOperationAction(ISD::FSIN, MVT::f32, Expand); 427 setOperationAction(ISD::FSIN, MVT::f64, Expand); 428 setOperationAction(ISD::FCOS, MVT::f32, Expand); 429 setOperationAction(ISD::FCOS, MVT::f64, Expand); 430 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 431 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 432 setOperationAction(ISD::FPOWI, MVT::f32, Expand); 433 setOperationAction(ISD::FPOW, MVT::f32, Expand); 434 setOperationAction(ISD::FPOW, MVT::f64, Expand); 435 setOperationAction(ISD::FLOG, MVT::f32, Expand); 436 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 437 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 438 setOperationAction(ISD::FEXP, MVT::f32, Expand); 439 setOperationAction(ISD::FMA, MVT::f32, Expand); 440 setOperationAction(ISD::FMA, MVT::f64, Expand); 441 setOperationAction(ISD::FREM, MVT::f32, Expand); 442 setOperationAction(ISD::FREM, MVT::f64, Expand); 443 444 if (!TM.Options.NoNaNsFPMath) { 445 setOperationAction(ISD::FNEG, MVT::f32, Expand); 446 setOperationAction(ISD::FNEG, MVT::f64, Expand); 447 } 448 449 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 450 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 451 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 452 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 453 454 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); 455 456 setOperationAction(ISD::VAARG, MVT::Other, Expand); 457 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 458 setOperationAction(ISD::VAEND, MVT::Other, Expand); 459 460 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom); 461 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom); 462 463 // Use the default for now 464 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 465 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 466 467 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); 468 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); 469 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); 470 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); 471 472 if (Subtarget->inMips16Mode()) { 473 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand); 474 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand); 475 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand); 476 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand); 477 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand); 478 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand); 479 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand); 480 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand); 481 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand); 482 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand); 483 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand); 484 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand); 485 } 486 487 setInsertFencesForAtomic(true); 488 489 if (!Subtarget->hasSEInReg()) { 490 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 491 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 492 } 493 494 if (!Subtarget->hasBitCount()) { 495 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 496 setOperationAction(ISD::CTLZ, MVT::i64, Expand); 497 } 498 499 if (!Subtarget->hasSwap()) { 500 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 501 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 502 } 503 504 if (HasMips64) { 505 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom); 506 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom); 507 setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom); 508 setTruncStoreAction(MVT::i64, MVT::i32, Custom); 509 } 510 511 setTargetDAGCombine(ISD::ADDE); 512 setTargetDAGCombine(ISD::SUBE); 513 setTargetDAGCombine(ISD::SDIVREM); 514 setTargetDAGCombine(ISD::UDIVREM); 515 setTargetDAGCombine(ISD::SELECT); 516 setTargetDAGCombine(ISD::AND); 517 setTargetDAGCombine(ISD::OR); 518 setTargetDAGCombine(ISD::ADD); 519 520 setMinFunctionAlignment(HasMips64 ? 3 : 2); 521 522 setStackPointerRegisterToSaveRestore(IsN64 ? Mips::SP_64 : Mips::SP); 523 computeRegisterProperties(); 524 525 setExceptionPointerRegister(IsN64 ? Mips::A0_64 : Mips::A0); 526 setExceptionSelectorRegister(IsN64 ? Mips::A1_64 : Mips::A1); 527 528 MaxStoresPerMemcpy = 16; 529} 530 531bool 532MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const { 533 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy; 534 535 if (Subtarget->inMips16Mode()) 536 return false; 537 538 switch (SVT) { 539 case MVT::i64: 540 case MVT::i32: 541 if (Fast) 542 *Fast = true; 543 return true; 544 default: 545 return false; 546 } 547} 548 549EVT MipsTargetLowering::getSetCCResultType(EVT VT) const { 550 if (!VT.isVector()) 551 return MVT::i32; 552 return VT.changeVectorElementTypeToInteger(); 553} 554 555// SelectMadd - 556// Transforms a subgraph in CurDAG if the following pattern is found: 557// (addc multLo, Lo0), (adde multHi, Hi0), 558// where, 559// multHi/Lo: product of multiplication 560// Lo0: initial value of Lo register 561// Hi0: initial value of Hi register 562// Return true if pattern matching was successful. 563static bool SelectMadd(SDNode *ADDENode, SelectionDAG *CurDAG) { 564 // ADDENode's second operand must be a flag output of an ADDC node in order 565 // for the matching to be successful. 566 SDNode *ADDCNode = ADDENode->getOperand(2).getNode(); 567 568 if (ADDCNode->getOpcode() != ISD::ADDC) 569 return false; 570 571 SDValue MultHi = ADDENode->getOperand(0); 572 SDValue MultLo = ADDCNode->getOperand(0); 573 SDNode *MultNode = MultHi.getNode(); 574 unsigned MultOpc = MultHi.getOpcode(); 575 576 // MultHi and MultLo must be generated by the same node, 577 if (MultLo.getNode() != MultNode) 578 return false; 579 580 // and it must be a multiplication. 581 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 582 return false; 583 584 // MultLo amd MultHi must be the first and second output of MultNode 585 // respectively. 586 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 587 return false; 588 589 // Transform this to a MADD only if ADDENode and ADDCNode are the only users 590 // of the values of MultNode, in which case MultNode will be removed in later 591 // phases. 592 // If there exist users other than ADDENode or ADDCNode, this function returns 593 // here, which will result in MultNode being mapped to a single MULT 594 // instruction node rather than a pair of MULT and MADD instructions being 595 // produced. 596 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 597 return false; 598 599 SDValue Chain = CurDAG->getEntryNode(); 600 DebugLoc dl = ADDENode->getDebugLoc(); 601 602 // create MipsMAdd(u) node 603 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd; 604 605 SDValue MAdd = CurDAG->getNode(MultOpc, dl, MVT::Glue, 606 MultNode->getOperand(0),// Factor 0 607 MultNode->getOperand(1),// Factor 1 608 ADDCNode->getOperand(1),// Lo0 609 ADDENode->getOperand(1));// Hi0 610 611 // create CopyFromReg nodes 612 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32, 613 MAdd); 614 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl, 615 Mips::HI, MVT::i32, 616 CopyFromLo.getValue(2)); 617 618 // replace uses of adde and addc here 619 if (!SDValue(ADDCNode, 0).use_empty()) 620 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo); 621 622 if (!SDValue(ADDENode, 0).use_empty()) 623 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi); 624 625 return true; 626} 627 628// SelectMsub - 629// Transforms a subgraph in CurDAG if the following pattern is found: 630// (addc Lo0, multLo), (sube Hi0, multHi), 631// where, 632// multHi/Lo: product of multiplication 633// Lo0: initial value of Lo register 634// Hi0: initial value of Hi register 635// Return true if pattern matching was successful. 636static bool SelectMsub(SDNode *SUBENode, SelectionDAG *CurDAG) { 637 // SUBENode's second operand must be a flag output of an SUBC node in order 638 // for the matching to be successful. 639 SDNode *SUBCNode = SUBENode->getOperand(2).getNode(); 640 641 if (SUBCNode->getOpcode() != ISD::SUBC) 642 return false; 643 644 SDValue MultHi = SUBENode->getOperand(1); 645 SDValue MultLo = SUBCNode->getOperand(1); 646 SDNode *MultNode = MultHi.getNode(); 647 unsigned MultOpc = MultHi.getOpcode(); 648 649 // MultHi and MultLo must be generated by the same node, 650 if (MultLo.getNode() != MultNode) 651 return false; 652 653 // and it must be a multiplication. 654 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 655 return false; 656 657 // MultLo amd MultHi must be the first and second output of MultNode 658 // respectively. 659 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 660 return false; 661 662 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users 663 // of the values of MultNode, in which case MultNode will be removed in later 664 // phases. 665 // If there exist users other than SUBENode or SUBCNode, this function returns 666 // here, which will result in MultNode being mapped to a single MULT 667 // instruction node rather than a pair of MULT and MSUB instructions being 668 // produced. 669 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 670 return false; 671 672 SDValue Chain = CurDAG->getEntryNode(); 673 DebugLoc dl = SUBENode->getDebugLoc(); 674 675 // create MipsSub(u) node 676 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub; 677 678 SDValue MSub = CurDAG->getNode(MultOpc, dl, MVT::Glue, 679 MultNode->getOperand(0),// Factor 0 680 MultNode->getOperand(1),// Factor 1 681 SUBCNode->getOperand(0),// Lo0 682 SUBENode->getOperand(0));// Hi0 683 684 // create CopyFromReg nodes 685 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32, 686 MSub); 687 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl, 688 Mips::HI, MVT::i32, 689 CopyFromLo.getValue(2)); 690 691 // replace uses of sube and subc here 692 if (!SDValue(SUBCNode, 0).use_empty()) 693 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo); 694 695 if (!SDValue(SUBENode, 0).use_empty()) 696 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi); 697 698 return true; 699} 700 701static SDValue PerformADDECombine(SDNode *N, SelectionDAG &DAG, 702 TargetLowering::DAGCombinerInfo &DCI, 703 const MipsSubtarget *Subtarget) { 704 if (DCI.isBeforeLegalize()) 705 return SDValue(); 706 707 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 && 708 SelectMadd(N, &DAG)) 709 return SDValue(N, 0); 710 711 return SDValue(); 712} 713 714static SDValue PerformSUBECombine(SDNode *N, SelectionDAG &DAG, 715 TargetLowering::DAGCombinerInfo &DCI, 716 const MipsSubtarget *Subtarget) { 717 if (DCI.isBeforeLegalize()) 718 return SDValue(); 719 720 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 && 721 SelectMsub(N, &DAG)) 722 return SDValue(N, 0); 723 724 return SDValue(); 725} 726 727static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG &DAG, 728 TargetLowering::DAGCombinerInfo &DCI, 729 const MipsSubtarget *Subtarget) { 730 if (DCI.isBeforeLegalizeOps()) 731 return SDValue(); 732 733 EVT Ty = N->getValueType(0); 734 unsigned LO = (Ty == MVT::i32) ? Mips::LO : Mips::LO64; 735 unsigned HI = (Ty == MVT::i32) ? Mips::HI : Mips::HI64; 736 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem : 737 MipsISD::DivRemU; 738 DebugLoc dl = N->getDebugLoc(); 739 740 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue, 741 N->getOperand(0), N->getOperand(1)); 742 SDValue InChain = DAG.getEntryNode(); 743 SDValue InGlue = DivRem; 744 745 // insert MFLO 746 if (N->hasAnyUseOfValue(0)) { 747 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, LO, Ty, 748 InGlue); 749 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 750 InChain = CopyFromLo.getValue(1); 751 InGlue = CopyFromLo.getValue(2); 752 } 753 754 // insert MFHI 755 if (N->hasAnyUseOfValue(1)) { 756 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl, 757 HI, Ty, InGlue); 758 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 759 } 760 761 return SDValue(); 762} 763 764static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) { 765 switch (CC) { 766 default: llvm_unreachable("Unknown fp condition code!"); 767 case ISD::SETEQ: 768 case ISD::SETOEQ: return Mips::FCOND_OEQ; 769 case ISD::SETUNE: return Mips::FCOND_UNE; 770 case ISD::SETLT: 771 case ISD::SETOLT: return Mips::FCOND_OLT; 772 case ISD::SETGT: 773 case ISD::SETOGT: return Mips::FCOND_OGT; 774 case ISD::SETLE: 775 case ISD::SETOLE: return Mips::FCOND_OLE; 776 case ISD::SETGE: 777 case ISD::SETOGE: return Mips::FCOND_OGE; 778 case ISD::SETULT: return Mips::FCOND_ULT; 779 case ISD::SETULE: return Mips::FCOND_ULE; 780 case ISD::SETUGT: return Mips::FCOND_UGT; 781 case ISD::SETUGE: return Mips::FCOND_UGE; 782 case ISD::SETUO: return Mips::FCOND_UN; 783 case ISD::SETO: return Mips::FCOND_OR; 784 case ISD::SETNE: 785 case ISD::SETONE: return Mips::FCOND_ONE; 786 case ISD::SETUEQ: return Mips::FCOND_UEQ; 787 } 788} 789 790 791// Returns true if condition code has to be inverted. 792static bool InvertFPCondCode(Mips::CondCode CC) { 793 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 794 return false; 795 796 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 797 "Illegal Condition Code"); 798 799 return true; 800} 801 802// Creates and returns an FPCmp node from a setcc node. 803// Returns Op if setcc is not a floating point comparison. 804static SDValue CreateFPCmp(SelectionDAG &DAG, const SDValue &Op) { 805 // must be a SETCC node 806 if (Op.getOpcode() != ISD::SETCC) 807 return Op; 808 809 SDValue LHS = Op.getOperand(0); 810 811 if (!LHS.getValueType().isFloatingPoint()) 812 return Op; 813 814 SDValue RHS = Op.getOperand(1); 815 DebugLoc dl = Op.getDebugLoc(); 816 817 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 818 // node if necessary. 819 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 820 821 return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS, 822 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32)); 823} 824 825// Creates and returns a CMovFPT/F node. 826static SDValue CreateCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, 827 SDValue False, DebugLoc DL) { 828 bool invert = InvertFPCondCode((Mips::CondCode) 829 cast<ConstantSDNode>(Cond.getOperand(2)) 830 ->getSExtValue()); 831 832 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 833 True.getValueType(), True, False, Cond); 834} 835 836static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 837 TargetLowering::DAGCombinerInfo &DCI, 838 const MipsSubtarget *Subtarget) { 839 if (DCI.isBeforeLegalizeOps()) 840 return SDValue(); 841 842 SDValue SetCC = N->getOperand(0); 843 844 if ((SetCC.getOpcode() != ISD::SETCC) || 845 !SetCC.getOperand(0).getValueType().isInteger()) 846 return SDValue(); 847 848 SDValue False = N->getOperand(2); 849 EVT FalseTy = False.getValueType(); 850 851 if (!FalseTy.isInteger()) 852 return SDValue(); 853 854 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(False); 855 856 if (!CN || CN->getZExtValue()) 857 return SDValue(); 858 859 const DebugLoc DL = N->getDebugLoc(); 860 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 861 SDValue True = N->getOperand(1); 862 863 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 864 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 865 866 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); 867} 868 869static SDValue PerformANDCombine(SDNode *N, SelectionDAG &DAG, 870 TargetLowering::DAGCombinerInfo &DCI, 871 const MipsSubtarget *Subtarget) { 872 // Pattern match EXT. 873 // $dst = and ((sra or srl) $src , pos), (2**size - 1) 874 // => ext $dst, $src, size, pos 875 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2()) 876 return SDValue(); 877 878 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1); 879 unsigned ShiftRightOpc = ShiftRight.getOpcode(); 880 881 // Op's first operand must be a shift right. 882 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL) 883 return SDValue(); 884 885 // The second operand of the shift must be an immediate. 886 ConstantSDNode *CN; 887 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1)))) 888 return SDValue(); 889 890 uint64_t Pos = CN->getZExtValue(); 891 uint64_t SMPos, SMSize; 892 893 // Op's second operand must be a shifted mask. 894 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) || 895 !IsShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 896 return SDValue(); 897 898 // Return if the shifted mask does not start at bit 0 or the sum of its size 899 // and Pos exceeds the word's size. 900 EVT ValTy = N->getValueType(0); 901 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits()) 902 return SDValue(); 903 904 return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), ValTy, 905 ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32), 906 DAG.getConstant(SMSize, MVT::i32)); 907} 908 909static SDValue PerformORCombine(SDNode *N, SelectionDAG &DAG, 910 TargetLowering::DAGCombinerInfo &DCI, 911 const MipsSubtarget *Subtarget) { 912 // Pattern match INS. 913 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), 914 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 915 // => ins $dst, $src, size, pos, $src1 916 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2()) 917 return SDValue(); 918 919 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); 920 uint64_t SMPos0, SMSize0, SMPos1, SMSize1; 921 ConstantSDNode *CN; 922 923 // See if Op's first operand matches (and $src1 , mask0). 924 if (And0.getOpcode() != ISD::AND) 925 return SDValue(); 926 927 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) || 928 !IsShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0)) 929 return SDValue(); 930 931 // See if Op's second operand matches (and (shl $src, pos), mask1). 932 if (And1.getOpcode() != ISD::AND) 933 return SDValue(); 934 935 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || 936 !IsShiftedMask(CN->getZExtValue(), SMPos1, SMSize1)) 937 return SDValue(); 938 939 // The shift masks must have the same position and size. 940 if (SMPos0 != SMPos1 || SMSize0 != SMSize1) 941 return SDValue(); 942 943 SDValue Shl = And1.getOperand(0); 944 if (Shl.getOpcode() != ISD::SHL) 945 return SDValue(); 946 947 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1)))) 948 return SDValue(); 949 950 unsigned Shamt = CN->getZExtValue(); 951 952 // Return if the shift amount and the first bit position of mask are not the 953 // same. 954 EVT ValTy = N->getValueType(0); 955 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits())) 956 return SDValue(); 957 958 return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), ValTy, Shl.getOperand(0), 959 DAG.getConstant(SMPos0, MVT::i32), 960 DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0)); 961} 962 963static SDValue PerformADDCombine(SDNode *N, SelectionDAG &DAG, 964 TargetLowering::DAGCombinerInfo &DCI, 965 const MipsSubtarget *Subtarget) { 966 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) 967 968 if (DCI.isBeforeLegalizeOps()) 969 return SDValue(); 970 971 SDValue Add = N->getOperand(1); 972 973 if (Add.getOpcode() != ISD::ADD) 974 return SDValue(); 975 976 SDValue Lo = Add.getOperand(1); 977 978 if ((Lo.getOpcode() != MipsISD::Lo) || 979 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable)) 980 return SDValue(); 981 982 EVT ValTy = N->getValueType(0); 983 DebugLoc DL = N->getDebugLoc(); 984 985 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0), 986 Add.getOperand(0)); 987 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo); 988} 989 990SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 991 const { 992 SelectionDAG &DAG = DCI.DAG; 993 unsigned opc = N->getOpcode(); 994 995 switch (opc) { 996 default: break; 997 case ISD::ADDE: 998 return PerformADDECombine(N, DAG, DCI, Subtarget); 999 case ISD::SUBE: 1000 return PerformSUBECombine(N, DAG, DCI, Subtarget); 1001 case ISD::SDIVREM: 1002 case ISD::UDIVREM: 1003 return PerformDivRemCombine(N, DAG, DCI, Subtarget); 1004 case ISD::SELECT: 1005 return PerformSELECTCombine(N, DAG, DCI, Subtarget); 1006 case ISD::AND: 1007 return PerformANDCombine(N, DAG, DCI, Subtarget); 1008 case ISD::OR: 1009 return PerformORCombine(N, DAG, DCI, Subtarget); 1010 case ISD::ADD: 1011 return PerformADDCombine(N, DAG, DCI, Subtarget); 1012 } 1013 1014 return SDValue(); 1015} 1016 1017void 1018MipsTargetLowering::LowerOperationWrapper(SDNode *N, 1019 SmallVectorImpl<SDValue> &Results, 1020 SelectionDAG &DAG) const { 1021 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 1022 1023 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I) 1024 Results.push_back(Res.getValue(I)); 1025} 1026 1027void 1028MipsTargetLowering::ReplaceNodeResults(SDNode *N, 1029 SmallVectorImpl<SDValue> &Results, 1030 SelectionDAG &DAG) const { 1031 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 1032 1033 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I) 1034 Results.push_back(Res.getValue(I)); 1035} 1036 1037SDValue MipsTargetLowering:: 1038LowerOperation(SDValue Op, SelectionDAG &DAG) const 1039{ 1040 switch (Op.getOpcode()) 1041 { 1042 case ISD::BR_JT: return LowerBR_JT(Op, DAG); 1043 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 1044 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 1045 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 1046 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 1047 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 1048 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 1049 case ISD::SELECT: return LowerSELECT(Op, DAG); 1050 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 1051 case ISD::SETCC: return LowerSETCC(Op, DAG); 1052 case ISD::VASTART: return LowerVASTART(Op, DAG); 1053 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 1054 case ISD::FABS: return LowerFABS(Op, DAG); 1055 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 1056 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 1057 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 1058 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG); 1059 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG); 1060 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG); 1061 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG, true); 1062 case ISD::SRL_PARTS: return LowerShiftRightParts(Op, DAG, false); 1063 case ISD::LOAD: return LowerLOAD(Op, DAG); 1064 case ISD::STORE: return LowerSTORE(Op, DAG); 1065 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 1066 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG); 1067 case ISD::ADD: return LowerADD(Op, DAG); 1068 } 1069 return SDValue(); 1070} 1071 1072//===----------------------------------------------------------------------===// 1073// Lower helper functions 1074//===----------------------------------------------------------------------===// 1075 1076// AddLiveIn - This helper function adds the specified physical register to the 1077// MachineFunction as a live in value. It also creates a corresponding 1078// virtual register for it. 1079static unsigned 1080AddLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) 1081{ 1082 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 1083 MF.getRegInfo().addLiveIn(PReg, VReg); 1084 return VReg; 1085} 1086 1087// Get fp branch code (not opcode) from condition code. 1088static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) { 1089 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 1090 return Mips::BRANCH_T; 1091 1092 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 1093 "Invalid CondCode."); 1094 1095 return Mips::BRANCH_F; 1096} 1097 1098/* 1099static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB, 1100 DebugLoc dl, 1101 const MipsSubtarget *Subtarget, 1102 const TargetInstrInfo *TII, 1103 bool isFPCmp, unsigned Opc) { 1104 // There is no need to expand CMov instructions if target has 1105 // conditional moves. 1106 if (Subtarget->hasCondMov()) 1107 return BB; 1108 1109 // To "insert" a SELECT_CC instruction, we actually have to insert the 1110 // diamond control-flow pattern. The incoming instruction knows the 1111 // destination vreg to set, the condition code register to branch on, the 1112 // true/false values to select between, and a branch opcode to use. 1113 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1114 MachineFunction::iterator It = BB; 1115 ++It; 1116 1117 // thisMBB: 1118 // ... 1119 // TrueVal = ... 1120 // setcc r1, r2, r3 1121 // bNE r1, r0, copy1MBB 1122 // fallthrough --> copy0MBB 1123 MachineBasicBlock *thisMBB = BB; 1124 MachineFunction *F = BB->getParent(); 1125 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 1126 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 1127 F->insert(It, copy0MBB); 1128 F->insert(It, sinkMBB); 1129 1130 // Transfer the remainder of BB and its successor edges to sinkMBB. 1131 sinkMBB->splice(sinkMBB->begin(), BB, 1132 llvm::next(MachineBasicBlock::iterator(MI)), 1133 BB->end()); 1134 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 1135 1136 // Next, add the true and fallthrough blocks as its successors. 1137 BB->addSuccessor(copy0MBB); 1138 BB->addSuccessor(sinkMBB); 1139 1140 // Emit the right instruction according to the type of the operands compared 1141 if (isFPCmp) 1142 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB); 1143 else 1144 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg()) 1145 .addReg(Mips::ZERO).addMBB(sinkMBB); 1146 1147 // copy0MBB: 1148 // %FalseValue = ... 1149 // # fallthrough to sinkMBB 1150 BB = copy0MBB; 1151 1152 // Update machine-CFG edges 1153 BB->addSuccessor(sinkMBB); 1154 1155 // sinkMBB: 1156 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 1157 // ... 1158 BB = sinkMBB; 1159 1160 if (isFPCmp) 1161 BuildMI(*BB, BB->begin(), dl, 1162 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 1163 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB) 1164 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB); 1165 else 1166 BuildMI(*BB, BB->begin(), dl, 1167 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 1168 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB) 1169 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB); 1170 1171 MI->eraseFromParent(); // The pseudo instruction is gone now. 1172 return BB; 1173} 1174*/ 1175 1176MachineBasicBlock * 1177MipsTargetLowering::EmitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{ 1178 // $bb: 1179 // bposge32_pseudo $vr0 1180 // => 1181 // $bb: 1182 // bposge32 $tbb 1183 // $fbb: 1184 // li $vr2, 0 1185 // b $sink 1186 // $tbb: 1187 // li $vr1, 1 1188 // $sink: 1189 // $vr0 = phi($vr2, $fbb, $vr1, $tbb) 1190 1191 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 1192 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1193 const TargetRegisterClass *RC = &Mips::CPURegsRegClass; 1194 DebugLoc DL = MI->getDebugLoc(); 1195 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1196 MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB)); 1197 MachineFunction *F = BB->getParent(); 1198 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB); 1199 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB); 1200 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB); 1201 F->insert(It, FBB); 1202 F->insert(It, TBB); 1203 F->insert(It, Sink); 1204 1205 // Transfer the remainder of BB and its successor edges to Sink. 1206 Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)), 1207 BB->end()); 1208 Sink->transferSuccessorsAndUpdatePHIs(BB); 1209 1210 // Add successors. 1211 BB->addSuccessor(FBB); 1212 BB->addSuccessor(TBB); 1213 FBB->addSuccessor(Sink); 1214 TBB->addSuccessor(Sink); 1215 1216 // Insert the real bposge32 instruction to $BB. 1217 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB); 1218 1219 // Fill $FBB. 1220 unsigned VR2 = RegInfo.createVirtualRegister(RC); 1221 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2) 1222 .addReg(Mips::ZERO).addImm(0); 1223 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink); 1224 1225 // Fill $TBB. 1226 unsigned VR1 = RegInfo.createVirtualRegister(RC); 1227 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1) 1228 .addReg(Mips::ZERO).addImm(1); 1229 1230 // Insert phi function to $Sink. 1231 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI), 1232 MI->getOperand(0).getReg()) 1233 .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB); 1234 1235 MI->eraseFromParent(); // The pseudo instruction is gone now. 1236 return Sink; 1237} 1238 1239MachineBasicBlock *MipsTargetLowering::EmitSel16(unsigned Opc, MachineInstr *MI, 1240 MachineBasicBlock *BB) const { 1241 if (DontExpandCondPseudos16) 1242 return BB; 1243 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1244 DebugLoc dl = MI->getDebugLoc(); 1245 // To "insert" a SELECT_CC instruction, we actually have to insert the 1246 // diamond control-flow pattern. The incoming instruction knows the 1247 // destination vreg to set, the condition code register to branch on, the 1248 // true/false values to select between, and a branch opcode to use. 1249 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1250 MachineFunction::iterator It = BB; 1251 ++It; 1252 1253 // thisMBB: 1254 // ... 1255 // TrueVal = ... 1256 // setcc r1, r2, r3 1257 // bNE r1, r0, copy1MBB 1258 // fallthrough --> copy0MBB 1259 MachineBasicBlock *thisMBB = BB; 1260 MachineFunction *F = BB->getParent(); 1261 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 1262 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 1263 F->insert(It, copy0MBB); 1264 F->insert(It, sinkMBB); 1265 1266 // Transfer the remainder of BB and its successor edges to sinkMBB. 1267 sinkMBB->splice(sinkMBB->begin(), BB, 1268 llvm::next(MachineBasicBlock::iterator(MI)), 1269 BB->end()); 1270 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 1271 1272 // Next, add the true and fallthrough blocks as its successors. 1273 BB->addSuccessor(copy0MBB); 1274 BB->addSuccessor(sinkMBB); 1275 1276 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(3).getReg()) 1277 .addMBB(sinkMBB); 1278 1279 // copy0MBB: 1280 // %FalseValue = ... 1281 // # fallthrough to sinkMBB 1282 BB = copy0MBB; 1283 1284 // Update machine-CFG edges 1285 BB->addSuccessor(sinkMBB); 1286 1287 // sinkMBB: 1288 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 1289 // ... 1290 BB = sinkMBB; 1291 1292 BuildMI(*BB, BB->begin(), dl, 1293 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 1294 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB) 1295 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB); 1296 1297 MI->eraseFromParent(); // The pseudo instruction is gone now. 1298 return BB; 1299} 1300 1301MachineBasicBlock *MipsTargetLowering::EmitSelT16 1302 (unsigned Opc1, unsigned Opc2, 1303 MachineInstr *MI, MachineBasicBlock *BB) const { 1304 if (DontExpandCondPseudos16) 1305 return BB; 1306 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1307 DebugLoc dl = MI->getDebugLoc(); 1308 // To "insert" a SELECT_CC instruction, we actually have to insert the 1309 // diamond control-flow pattern. The incoming instruction knows the 1310 // destination vreg to set, the condition code register to branch on, the 1311 // true/false values to select between, and a branch opcode to use. 1312 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1313 MachineFunction::iterator It = BB; 1314 ++It; 1315 1316 // thisMBB: 1317 // ... 1318 // TrueVal = ... 1319 // setcc r1, r2, r3 1320 // bNE r1, r0, copy1MBB 1321 // fallthrough --> copy0MBB 1322 MachineBasicBlock *thisMBB = BB; 1323 MachineFunction *F = BB->getParent(); 1324 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 1325 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 1326 F->insert(It, copy0MBB); 1327 F->insert(It, sinkMBB); 1328 1329 // Transfer the remainder of BB and its successor edges to sinkMBB. 1330 sinkMBB->splice(sinkMBB->begin(), BB, 1331 llvm::next(MachineBasicBlock::iterator(MI)), 1332 BB->end()); 1333 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 1334 1335 // Next, add the true and fallthrough blocks as its successors. 1336 BB->addSuccessor(copy0MBB); 1337 BB->addSuccessor(sinkMBB); 1338 1339 BuildMI(BB, dl, TII->get(Opc2)).addReg(MI->getOperand(3).getReg()) 1340 .addReg(MI->getOperand(4).getReg()); 1341 BuildMI(BB, dl, TII->get(Opc1)).addMBB(sinkMBB); 1342 1343 // copy0MBB: 1344 // %FalseValue = ... 1345 // # fallthrough to sinkMBB 1346 BB = copy0MBB; 1347 1348 // Update machine-CFG edges 1349 BB->addSuccessor(sinkMBB); 1350 1351 // sinkMBB: 1352 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 1353 // ... 1354 BB = sinkMBB; 1355 1356 BuildMI(*BB, BB->begin(), dl, 1357 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 1358 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB) 1359 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB); 1360 1361 MI->eraseFromParent(); // The pseudo instruction is gone now. 1362 return BB; 1363 1364} 1365 1366 1367MachineBasicBlock *MipsTargetLowering::EmitSeliT16 1368 (unsigned Opc1, unsigned Opc2, 1369 MachineInstr *MI, MachineBasicBlock *BB) const { 1370 if (DontExpandCondPseudos16) 1371 return BB; 1372 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1373 DebugLoc dl = MI->getDebugLoc(); 1374 // To "insert" a SELECT_CC instruction, we actually have to insert the 1375 // diamond control-flow pattern. The incoming instruction knows the 1376 // destination vreg to set, the condition code register to branch on, the 1377 // true/false values to select between, and a branch opcode to use. 1378 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1379 MachineFunction::iterator It = BB; 1380 ++It; 1381 1382 // thisMBB: 1383 // ... 1384 // TrueVal = ... 1385 // setcc r1, r2, r3 1386 // bNE r1, r0, copy1MBB 1387 // fallthrough --> copy0MBB 1388 MachineBasicBlock *thisMBB = BB; 1389 MachineFunction *F = BB->getParent(); 1390 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 1391 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 1392 F->insert(It, copy0MBB); 1393 F->insert(It, sinkMBB); 1394 1395 // Transfer the remainder of BB and its successor edges to sinkMBB. 1396 sinkMBB->splice(sinkMBB->begin(), BB, 1397 llvm::next(MachineBasicBlock::iterator(MI)), 1398 BB->end()); 1399 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 1400 1401 // Next, add the true and fallthrough blocks as its successors. 1402 BB->addSuccessor(copy0MBB); 1403 BB->addSuccessor(sinkMBB); 1404 1405 BuildMI(BB, dl, TII->get(Opc2)).addReg(MI->getOperand(3).getReg()) 1406 .addImm(MI->getOperand(4).getImm()); 1407 BuildMI(BB, dl, TII->get(Opc1)).addMBB(sinkMBB); 1408 1409 // copy0MBB: 1410 // %FalseValue = ... 1411 // # fallthrough to sinkMBB 1412 BB = copy0MBB; 1413 1414 // Update machine-CFG edges 1415 BB->addSuccessor(sinkMBB); 1416 1417 // sinkMBB: 1418 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 1419 // ... 1420 BB = sinkMBB; 1421 1422 BuildMI(*BB, BB->begin(), dl, 1423 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 1424 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB) 1425 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB); 1426 1427 MI->eraseFromParent(); // The pseudo instruction is gone now. 1428 return BB; 1429 1430} 1431 1432 1433MachineBasicBlock 1434 *MipsTargetLowering::EmitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc, 1435 MachineInstr *MI, 1436 MachineBasicBlock *BB) const { 1437 if (DontExpandCondPseudos16) 1438 return BB; 1439 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1440 unsigned regX = MI->getOperand(0).getReg(); 1441 unsigned regY = MI->getOperand(1).getReg(); 1442 MachineBasicBlock *target = MI->getOperand(2).getMBB(); 1443 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX).addReg(regY); 1444 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target); 1445 MI->eraseFromParent(); // The pseudo instruction is gone now. 1446 return BB; 1447} 1448 1449 1450MachineBasicBlock *MipsTargetLowering::EmitFEXT_T8I8I16_ins( 1451 unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc, 1452 MachineInstr *MI, MachineBasicBlock *BB) const { 1453 if (DontExpandCondPseudos16) 1454 return BB; 1455 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1456 unsigned regX = MI->getOperand(0).getReg(); 1457 int64_t imm = MI->getOperand(1).getImm(); 1458 MachineBasicBlock *target = MI->getOperand(2).getMBB(); 1459 unsigned CmpOpc; 1460 if (isUInt<8>(imm)) 1461 CmpOpc = CmpiOpc; 1462 else if (isUInt<16>(imm)) 1463 CmpOpc = CmpiXOpc; 1464 else 1465 llvm_unreachable("immediate field not usable"); 1466 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX).addImm(imm); 1467 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target); 1468 MI->eraseFromParent(); // The pseudo instruction is gone now. 1469 return BB; 1470} 1471 1472 1473static unsigned Mips16WhichOp8uOr16simm 1474 (unsigned shortOp, unsigned longOp, int64_t Imm) { 1475 if (isUInt<8>(Imm)) 1476 return shortOp; 1477 else if (isInt<16>(Imm)) 1478 return longOp; 1479 else 1480 llvm_unreachable("immediate field not usable"); 1481} 1482 1483MachineBasicBlock *MipsTargetLowering::EmitFEXT_CCRX16_ins( 1484 unsigned SltOpc, 1485 MachineInstr *MI, MachineBasicBlock *BB) const { 1486 if (DontExpandCondPseudos16) 1487 return BB; 1488 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1489 unsigned CC = MI->getOperand(0).getReg(); 1490 unsigned regX = MI->getOperand(1).getReg(); 1491 unsigned regY = MI->getOperand(2).getReg(); 1492 BuildMI(*BB, MI, MI->getDebugLoc(), 1493 TII->get(SltOpc)).addReg(regX).addReg(regY); 1494 BuildMI(*BB, MI, MI->getDebugLoc(), 1495 TII->get(Mips::MoveR3216), CC).addReg(Mips::T8); 1496 MI->eraseFromParent(); // The pseudo instruction is gone now. 1497 return BB; 1498} 1499MachineBasicBlock *MipsTargetLowering::EmitFEXT_CCRXI16_ins( 1500 unsigned SltiOpc, unsigned SltiXOpc, 1501 MachineInstr *MI, MachineBasicBlock *BB )const { 1502 if (DontExpandCondPseudos16) 1503 return BB; 1504 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1505 unsigned CC = MI->getOperand(0).getReg(); 1506 unsigned regX = MI->getOperand(1).getReg(); 1507 int64_t Imm = MI->getOperand(2).getImm(); 1508 unsigned SltOpc = Mips16WhichOp8uOr16simm(SltiOpc, SltiXOpc, Imm); 1509 BuildMI(*BB, MI, MI->getDebugLoc(), 1510 TII->get(SltOpc)).addReg(regX).addImm(Imm); 1511 BuildMI(*BB, MI, MI->getDebugLoc(), 1512 TII->get(Mips::MoveR3216), CC).addReg(Mips::T8); 1513 MI->eraseFromParent(); // The pseudo instruction is gone now. 1514 return BB; 1515 1516} 1517MachineBasicBlock * 1518MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 1519 MachineBasicBlock *BB) const { 1520 switch (MI->getOpcode()) { 1521 default: 1522 llvm_unreachable("Unexpected instr type to insert"); 1523 case Mips::ATOMIC_LOAD_ADD_I8: 1524 case Mips::ATOMIC_LOAD_ADD_I8_P8: 1525 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu); 1526 case Mips::ATOMIC_LOAD_ADD_I16: 1527 case Mips::ATOMIC_LOAD_ADD_I16_P8: 1528 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu); 1529 case Mips::ATOMIC_LOAD_ADD_I32: 1530 case Mips::ATOMIC_LOAD_ADD_I32_P8: 1531 return EmitAtomicBinary(MI, BB, 4, Mips::ADDu); 1532 case Mips::ATOMIC_LOAD_ADD_I64: 1533 case Mips::ATOMIC_LOAD_ADD_I64_P8: 1534 return EmitAtomicBinary(MI, BB, 8, Mips::DADDu); 1535 1536 case Mips::ATOMIC_LOAD_AND_I8: 1537 case Mips::ATOMIC_LOAD_AND_I8_P8: 1538 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::AND); 1539 case Mips::ATOMIC_LOAD_AND_I16: 1540 case Mips::ATOMIC_LOAD_AND_I16_P8: 1541 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::AND); 1542 case Mips::ATOMIC_LOAD_AND_I32: 1543 case Mips::ATOMIC_LOAD_AND_I32_P8: 1544 return EmitAtomicBinary(MI, BB, 4, Mips::AND); 1545 case Mips::ATOMIC_LOAD_AND_I64: 1546 case Mips::ATOMIC_LOAD_AND_I64_P8: 1547 return EmitAtomicBinary(MI, BB, 8, Mips::AND64); 1548 1549 case Mips::ATOMIC_LOAD_OR_I8: 1550 case Mips::ATOMIC_LOAD_OR_I8_P8: 1551 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::OR); 1552 case Mips::ATOMIC_LOAD_OR_I16: 1553 case Mips::ATOMIC_LOAD_OR_I16_P8: 1554 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::OR); 1555 case Mips::ATOMIC_LOAD_OR_I32: 1556 case Mips::ATOMIC_LOAD_OR_I32_P8: 1557 return EmitAtomicBinary(MI, BB, 4, Mips::OR); 1558 case Mips::ATOMIC_LOAD_OR_I64: 1559 case Mips::ATOMIC_LOAD_OR_I64_P8: 1560 return EmitAtomicBinary(MI, BB, 8, Mips::OR64); 1561 1562 case Mips::ATOMIC_LOAD_XOR_I8: 1563 case Mips::ATOMIC_LOAD_XOR_I8_P8: 1564 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::XOR); 1565 case Mips::ATOMIC_LOAD_XOR_I16: 1566 case Mips::ATOMIC_LOAD_XOR_I16_P8: 1567 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::XOR); 1568 case Mips::ATOMIC_LOAD_XOR_I32: 1569 case Mips::ATOMIC_LOAD_XOR_I32_P8: 1570 return EmitAtomicBinary(MI, BB, 4, Mips::XOR); 1571 case Mips::ATOMIC_LOAD_XOR_I64: 1572 case Mips::ATOMIC_LOAD_XOR_I64_P8: 1573 return EmitAtomicBinary(MI, BB, 8, Mips::XOR64); 1574 1575 case Mips::ATOMIC_LOAD_NAND_I8: 1576 case Mips::ATOMIC_LOAD_NAND_I8_P8: 1577 return EmitAtomicBinaryPartword(MI, BB, 1, 0, true); 1578 case Mips::ATOMIC_LOAD_NAND_I16: 1579 case Mips::ATOMIC_LOAD_NAND_I16_P8: 1580 return EmitAtomicBinaryPartword(MI, BB, 2, 0, true); 1581 case Mips::ATOMIC_LOAD_NAND_I32: 1582 case Mips::ATOMIC_LOAD_NAND_I32_P8: 1583 return EmitAtomicBinary(MI, BB, 4, 0, true); 1584 case Mips::ATOMIC_LOAD_NAND_I64: 1585 case Mips::ATOMIC_LOAD_NAND_I64_P8: 1586 return EmitAtomicBinary(MI, BB, 8, 0, true); 1587 1588 case Mips::ATOMIC_LOAD_SUB_I8: 1589 case Mips::ATOMIC_LOAD_SUB_I8_P8: 1590 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu); 1591 case Mips::ATOMIC_LOAD_SUB_I16: 1592 case Mips::ATOMIC_LOAD_SUB_I16_P8: 1593 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu); 1594 case Mips::ATOMIC_LOAD_SUB_I32: 1595 case Mips::ATOMIC_LOAD_SUB_I32_P8: 1596 return EmitAtomicBinary(MI, BB, 4, Mips::SUBu); 1597 case Mips::ATOMIC_LOAD_SUB_I64: 1598 case Mips::ATOMIC_LOAD_SUB_I64_P8: 1599 return EmitAtomicBinary(MI, BB, 8, Mips::DSUBu); 1600 1601 case Mips::ATOMIC_SWAP_I8: 1602 case Mips::ATOMIC_SWAP_I8_P8: 1603 return EmitAtomicBinaryPartword(MI, BB, 1, 0); 1604 case Mips::ATOMIC_SWAP_I16: 1605 case Mips::ATOMIC_SWAP_I16_P8: 1606 return EmitAtomicBinaryPartword(MI, BB, 2, 0); 1607 case Mips::ATOMIC_SWAP_I32: 1608 case Mips::ATOMIC_SWAP_I32_P8: 1609 return EmitAtomicBinary(MI, BB, 4, 0); 1610 case Mips::ATOMIC_SWAP_I64: 1611 case Mips::ATOMIC_SWAP_I64_P8: 1612 return EmitAtomicBinary(MI, BB, 8, 0); 1613 1614 case Mips::ATOMIC_CMP_SWAP_I8: 1615 case Mips::ATOMIC_CMP_SWAP_I8_P8: 1616 return EmitAtomicCmpSwapPartword(MI, BB, 1); 1617 case Mips::ATOMIC_CMP_SWAP_I16: 1618 case Mips::ATOMIC_CMP_SWAP_I16_P8: 1619 return EmitAtomicCmpSwapPartword(MI, BB, 2); 1620 case Mips::ATOMIC_CMP_SWAP_I32: 1621 case Mips::ATOMIC_CMP_SWAP_I32_P8: 1622 return EmitAtomicCmpSwap(MI, BB, 4); 1623 case Mips::ATOMIC_CMP_SWAP_I64: 1624 case Mips::ATOMIC_CMP_SWAP_I64_P8: 1625 return EmitAtomicCmpSwap(MI, BB, 8); 1626 case Mips::BPOSGE32_PSEUDO: 1627 return EmitBPOSGE32(MI, BB); 1628 case Mips::SelBeqZ: 1629 return EmitSel16(Mips::BeqzRxImm16, MI, BB); 1630 case Mips::SelBneZ: 1631 return EmitSel16(Mips::BnezRxImm16, MI, BB); 1632 case Mips::SelTBteqZCmpi: 1633 return EmitSeliT16(Mips::BteqzX16, Mips::CmpiRxImmX16, MI, BB); 1634 case Mips::SelTBteqZSlti: 1635 return EmitSeliT16(Mips::BteqzX16, Mips::SltiRxImmX16, MI, BB); 1636 case Mips::SelTBteqZSltiu: 1637 return EmitSeliT16(Mips::BteqzX16, Mips::SltiuRxImmX16, MI, BB); 1638 case Mips::SelTBtneZCmpi: 1639 return EmitSeliT16(Mips::BtnezX16, Mips::CmpiRxImmX16, MI, BB); 1640 case Mips::SelTBtneZSlti: 1641 return EmitSeliT16(Mips::BtnezX16, Mips::SltiRxImmX16, MI, BB); 1642 case Mips::SelTBtneZSltiu: 1643 return EmitSeliT16(Mips::BtnezX16, Mips::SltiuRxImmX16, MI, BB); 1644 case Mips::SelTBteqZCmp: 1645 return EmitSelT16(Mips::BteqzX16, Mips::CmpRxRy16, MI, BB); 1646 case Mips::SelTBteqZSlt: 1647 return EmitSelT16(Mips::BteqzX16, Mips::SltRxRy16, MI, BB); 1648 case Mips::SelTBteqZSltu: 1649 return EmitSelT16(Mips::BteqzX16, Mips::SltuRxRy16, MI, BB); 1650 case Mips::SelTBtneZCmp: 1651 return EmitSelT16(Mips::BtnezX16, Mips::CmpRxRy16, MI, BB); 1652 case Mips::SelTBtneZSlt: 1653 return EmitSelT16(Mips::BtnezX16, Mips::SltRxRy16, MI, BB); 1654 case Mips::SelTBtneZSltu: 1655 return EmitSelT16(Mips::BtnezX16, Mips::SltuRxRy16, MI, BB); 1656 case Mips::BteqzT8CmpX16: 1657 return EmitFEXT_T8I816_ins(Mips::BteqzX16, Mips::CmpRxRy16, MI, BB); 1658 case Mips::BteqzT8SltX16: 1659 return EmitFEXT_T8I816_ins(Mips::BteqzX16, Mips::SltRxRy16, MI, BB); 1660 case Mips::BteqzT8SltuX16: 1661 // TBD: figure out a way to get this or remove the instruction 1662 // altogether. 1663 return EmitFEXT_T8I816_ins(Mips::BteqzX16, Mips::SltuRxRy16, MI, BB); 1664 case Mips::BtnezT8CmpX16: 1665 return EmitFEXT_T8I816_ins(Mips::BtnezX16, Mips::CmpRxRy16, MI, BB); 1666 case Mips::BtnezT8SltX16: 1667 return EmitFEXT_T8I816_ins(Mips::BtnezX16, Mips::SltRxRy16, MI, BB); 1668 case Mips::BtnezT8SltuX16: 1669 // TBD: figure out a way to get this or remove the instruction 1670 // altogether. 1671 return EmitFEXT_T8I816_ins(Mips::BtnezX16, Mips::SltuRxRy16, MI, BB); 1672 case Mips::BteqzT8CmpiX16: return EmitFEXT_T8I8I16_ins( 1673 Mips::BteqzX16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, MI, BB); 1674 case Mips::BteqzT8SltiX16: return EmitFEXT_T8I8I16_ins( 1675 Mips::BteqzX16, Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB); 1676 case Mips::BteqzT8SltiuX16: return EmitFEXT_T8I8I16_ins( 1677 Mips::BteqzX16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, MI, BB); 1678 case Mips::BtnezT8CmpiX16: return EmitFEXT_T8I8I16_ins( 1679 Mips::BtnezX16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, MI, BB); 1680 case Mips::BtnezT8SltiX16: return EmitFEXT_T8I8I16_ins( 1681 Mips::BtnezX16, Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB); 1682 case Mips::BtnezT8SltiuX16: return EmitFEXT_T8I8I16_ins( 1683 Mips::BtnezX16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, MI, BB); 1684 break; 1685 case Mips::SltCCRxRy16: 1686 return EmitFEXT_CCRX16_ins(Mips::SltRxRy16, MI, BB); 1687 break; 1688 case Mips::SltiCCRxImmX16: 1689 return EmitFEXT_CCRXI16_ins 1690 (Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB); 1691 case Mips::SltiuCCRxImmX16: 1692 return EmitFEXT_CCRXI16_ins 1693 (Mips::SltiuRxImm16, Mips::SltiuRxImmX16, MI, BB); 1694 case Mips::SltuCCRxRy16: 1695 return EmitFEXT_CCRX16_ins 1696 (Mips::SltuRxRy16, MI, BB); 1697 } 1698} 1699 1700// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 1701// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 1702MachineBasicBlock * 1703MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 1704 unsigned Size, unsigned BinOpcode, 1705 bool Nand) const { 1706 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary."); 1707 1708 MachineFunction *MF = BB->getParent(); 1709 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1710 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1711 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1712 DebugLoc dl = MI->getDebugLoc(); 1713 unsigned LL, SC, AND, NOR, ZERO, BEQ; 1714 1715 if (Size == 4) { 1716 LL = IsN64 ? Mips::LL_P8 : Mips::LL; 1717 SC = IsN64 ? Mips::SC_P8 : Mips::SC; 1718 AND = Mips::AND; 1719 NOR = Mips::NOR; 1720 ZERO = Mips::ZERO; 1721 BEQ = Mips::BEQ; 1722 } 1723 else { 1724 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD; 1725 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD; 1726 AND = Mips::AND64; 1727 NOR = Mips::NOR64; 1728 ZERO = Mips::ZERO_64; 1729 BEQ = Mips::BEQ64; 1730 } 1731 1732 unsigned OldVal = MI->getOperand(0).getReg(); 1733 unsigned Ptr = MI->getOperand(1).getReg(); 1734 unsigned Incr = MI->getOperand(2).getReg(); 1735 1736 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1737 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1738 unsigned Success = RegInfo.createVirtualRegister(RC); 1739 1740 // insert new blocks after the current block 1741 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1742 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1743 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1744 MachineFunction::iterator It = BB; 1745 ++It; 1746 MF->insert(It, loopMBB); 1747 MF->insert(It, exitMBB); 1748 1749 // Transfer the remainder of BB and its successor edges to exitMBB. 1750 exitMBB->splice(exitMBB->begin(), BB, 1751 llvm::next(MachineBasicBlock::iterator(MI)), 1752 BB->end()); 1753 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1754 1755 // thisMBB: 1756 // ... 1757 // fallthrough --> loopMBB 1758 BB->addSuccessor(loopMBB); 1759 loopMBB->addSuccessor(loopMBB); 1760 loopMBB->addSuccessor(exitMBB); 1761 1762 // loopMBB: 1763 // ll oldval, 0(ptr) 1764 // <binop> storeval, oldval, incr 1765 // sc success, storeval, 0(ptr) 1766 // beq success, $0, loopMBB 1767 BB = loopMBB; 1768 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(Ptr).addImm(0); 1769 if (Nand) { 1770 // and andres, oldval, incr 1771 // nor storeval, $0, andres 1772 BuildMI(BB, dl, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr); 1773 BuildMI(BB, dl, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes); 1774 } else if (BinOpcode) { 1775 // <binop> storeval, oldval, incr 1776 BuildMI(BB, dl, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr); 1777 } else { 1778 StoreVal = Incr; 1779 } 1780 BuildMI(BB, dl, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0); 1781 BuildMI(BB, dl, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB); 1782 1783 MI->eraseFromParent(); // The instruction is gone now. 1784 1785 return exitMBB; 1786} 1787 1788MachineBasicBlock * 1789MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI, 1790 MachineBasicBlock *BB, 1791 unsigned Size, unsigned BinOpcode, 1792 bool Nand) const { 1793 assert((Size == 1 || Size == 2) && 1794 "Unsupported size for EmitAtomicBinaryPartial."); 1795 1796 MachineFunction *MF = BB->getParent(); 1797 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1798 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1799 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1800 DebugLoc dl = MI->getDebugLoc(); 1801 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL; 1802 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC; 1803 1804 unsigned Dest = MI->getOperand(0).getReg(); 1805 unsigned Ptr = MI->getOperand(1).getReg(); 1806 unsigned Incr = MI->getOperand(2).getReg(); 1807 1808 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 1809 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1810 unsigned Mask = RegInfo.createVirtualRegister(RC); 1811 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1812 unsigned NewVal = RegInfo.createVirtualRegister(RC); 1813 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1814 unsigned Incr2 = RegInfo.createVirtualRegister(RC); 1815 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 1816 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1817 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1818 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1819 unsigned BinOpRes = RegInfo.createVirtualRegister(RC); 1820 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1821 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1822 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1823 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1824 unsigned SllRes = RegInfo.createVirtualRegister(RC); 1825 unsigned Success = RegInfo.createVirtualRegister(RC); 1826 1827 // insert new blocks after the current block 1828 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1829 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1830 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1831 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1832 MachineFunction::iterator It = BB; 1833 ++It; 1834 MF->insert(It, loopMBB); 1835 MF->insert(It, sinkMBB); 1836 MF->insert(It, exitMBB); 1837 1838 // Transfer the remainder of BB and its successor edges to exitMBB. 1839 exitMBB->splice(exitMBB->begin(), BB, 1840 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1841 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1842 1843 BB->addSuccessor(loopMBB); 1844 loopMBB->addSuccessor(loopMBB); 1845 loopMBB->addSuccessor(sinkMBB); 1846 sinkMBB->addSuccessor(exitMBB); 1847 1848 // thisMBB: 1849 // addiu masklsb2,$0,-4 # 0xfffffffc 1850 // and alignedaddr,ptr,masklsb2 1851 // andi ptrlsb2,ptr,3 1852 // sll shiftamt,ptrlsb2,3 1853 // ori maskupper,$0,255 # 0xff 1854 // sll mask,maskupper,shiftamt 1855 // nor mask2,$0,mask 1856 // sll incr2,incr,shiftamt 1857 1858 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1859 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2) 1860 .addReg(Mips::ZERO).addImm(-4); 1861 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr) 1862 .addReg(Ptr).addReg(MaskLSB2); 1863 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1864 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1865 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper) 1866 .addReg(Mips::ZERO).addImm(MaskImm); 1867 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask) 1868 .addReg(ShiftAmt).addReg(MaskUpper); 1869 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1870 BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr); 1871 1872 // atomic.load.binop 1873 // loopMBB: 1874 // ll oldval,0(alignedaddr) 1875 // binop binopres,oldval,incr2 1876 // and newval,binopres,mask 1877 // and maskedoldval0,oldval,mask2 1878 // or storeval,maskedoldval0,newval 1879 // sc success,storeval,0(alignedaddr) 1880 // beq success,$0,loopMBB 1881 1882 // atomic.swap 1883 // loopMBB: 1884 // ll oldval,0(alignedaddr) 1885 // and newval,incr2,mask 1886 // and maskedoldval0,oldval,mask2 1887 // or storeval,maskedoldval0,newval 1888 // sc success,storeval,0(alignedaddr) 1889 // beq success,$0,loopMBB 1890 1891 BB = loopMBB; 1892 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1893 if (Nand) { 1894 // and andres, oldval, incr2 1895 // nor binopres, $0, andres 1896 // and newval, binopres, mask 1897 BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2); 1898 BuildMI(BB, dl, TII->get(Mips::NOR), BinOpRes) 1899 .addReg(Mips::ZERO).addReg(AndRes); 1900 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1901 } else if (BinOpcode) { 1902 // <binop> binopres, oldval, incr2 1903 // and newval, binopres, mask 1904 BuildMI(BB, dl, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2); 1905 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1906 } else {// atomic.swap 1907 // and newval, incr2, mask 1908 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask); 1909 } 1910 1911 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0) 1912 .addReg(OldVal).addReg(Mask2); 1913 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal) 1914 .addReg(MaskedOldVal0).addReg(NewVal); 1915 BuildMI(BB, dl, TII->get(SC), Success) 1916 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1917 BuildMI(BB, dl, TII->get(Mips::BEQ)) 1918 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB); 1919 1920 // sinkMBB: 1921 // and maskedoldval1,oldval,mask 1922 // srl srlres,maskedoldval1,shiftamt 1923 // sll sllres,srlres,24 1924 // sra dest,sllres,24 1925 BB = sinkMBB; 1926 int64_t ShiftImm = (Size == 1) ? 24 : 16; 1927 1928 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1) 1929 .addReg(OldVal).addReg(Mask); 1930 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes) 1931 .addReg(ShiftAmt).addReg(MaskedOldVal1); 1932 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes) 1933 .addReg(SrlRes).addImm(ShiftImm); 1934 BuildMI(BB, dl, TII->get(Mips::SRA), Dest) 1935 .addReg(SllRes).addImm(ShiftImm); 1936 1937 MI->eraseFromParent(); // The instruction is gone now. 1938 1939 return exitMBB; 1940} 1941 1942MachineBasicBlock * 1943MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI, 1944 MachineBasicBlock *BB, 1945 unsigned Size) const { 1946 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap."); 1947 1948 MachineFunction *MF = BB->getParent(); 1949 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1950 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1951 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1952 DebugLoc dl = MI->getDebugLoc(); 1953 unsigned LL, SC, ZERO, BNE, BEQ; 1954 1955 if (Size == 4) { 1956 LL = IsN64 ? Mips::LL_P8 : Mips::LL; 1957 SC = IsN64 ? Mips::SC_P8 : Mips::SC; 1958 ZERO = Mips::ZERO; 1959 BNE = Mips::BNE; 1960 BEQ = Mips::BEQ; 1961 } 1962 else { 1963 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD; 1964 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD; 1965 ZERO = Mips::ZERO_64; 1966 BNE = Mips::BNE64; 1967 BEQ = Mips::BEQ64; 1968 } 1969 1970 unsigned Dest = MI->getOperand(0).getReg(); 1971 unsigned Ptr = MI->getOperand(1).getReg(); 1972 unsigned OldVal = MI->getOperand(2).getReg(); 1973 unsigned NewVal = MI->getOperand(3).getReg(); 1974 1975 unsigned Success = RegInfo.createVirtualRegister(RC); 1976 1977 // insert new blocks after the current block 1978 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1979 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1980 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1981 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1982 MachineFunction::iterator It = BB; 1983 ++It; 1984 MF->insert(It, loop1MBB); 1985 MF->insert(It, loop2MBB); 1986 MF->insert(It, exitMBB); 1987 1988 // Transfer the remainder of BB and its successor edges to exitMBB. 1989 exitMBB->splice(exitMBB->begin(), BB, 1990 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1991 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1992 1993 // thisMBB: 1994 // ... 1995 // fallthrough --> loop1MBB 1996 BB->addSuccessor(loop1MBB); 1997 loop1MBB->addSuccessor(exitMBB); 1998 loop1MBB->addSuccessor(loop2MBB); 1999 loop2MBB->addSuccessor(loop1MBB); 2000 loop2MBB->addSuccessor(exitMBB); 2001 2002 // loop1MBB: 2003 // ll dest, 0(ptr) 2004 // bne dest, oldval, exitMBB 2005 BB = loop1MBB; 2006 BuildMI(BB, dl, TII->get(LL), Dest).addReg(Ptr).addImm(0); 2007 BuildMI(BB, dl, TII->get(BNE)) 2008 .addReg(Dest).addReg(OldVal).addMBB(exitMBB); 2009 2010 // loop2MBB: 2011 // sc success, newval, 0(ptr) 2012 // beq success, $0, loop1MBB 2013 BB = loop2MBB; 2014 BuildMI(BB, dl, TII->get(SC), Success) 2015 .addReg(NewVal).addReg(Ptr).addImm(0); 2016 BuildMI(BB, dl, TII->get(BEQ)) 2017 .addReg(Success).addReg(ZERO).addMBB(loop1MBB); 2018 2019 MI->eraseFromParent(); // The instruction is gone now. 2020 2021 return exitMBB; 2022} 2023 2024MachineBasicBlock * 2025MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI, 2026 MachineBasicBlock *BB, 2027 unsigned Size) const { 2028 assert((Size == 1 || Size == 2) && 2029 "Unsupported size for EmitAtomicCmpSwapPartial."); 2030 2031 MachineFunction *MF = BB->getParent(); 2032 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 2033 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 2034 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2035 DebugLoc dl = MI->getDebugLoc(); 2036 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL; 2037 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC; 2038 2039 unsigned Dest = MI->getOperand(0).getReg(); 2040 unsigned Ptr = MI->getOperand(1).getReg(); 2041 unsigned CmpVal = MI->getOperand(2).getReg(); 2042 unsigned NewVal = MI->getOperand(3).getReg(); 2043 2044 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 2045 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 2046 unsigned Mask = RegInfo.createVirtualRegister(RC); 2047 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 2048 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC); 2049 unsigned OldVal = RegInfo.createVirtualRegister(RC); 2050 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 2051 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC); 2052 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 2053 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 2054 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 2055 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC); 2056 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC); 2057 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 2058 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 2059 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 2060 unsigned SllRes = RegInfo.createVirtualRegister(RC); 2061 unsigned Success = RegInfo.createVirtualRegister(RC); 2062 2063 // insert new blocks after the current block 2064 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 2065 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 2066 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 2067 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 2068 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 2069 MachineFunction::iterator It = BB; 2070 ++It; 2071 MF->insert(It, loop1MBB); 2072 MF->insert(It, loop2MBB); 2073 MF->insert(It, sinkMBB); 2074 MF->insert(It, exitMBB); 2075 2076 // Transfer the remainder of BB and its successor edges to exitMBB. 2077 exitMBB->splice(exitMBB->begin(), BB, 2078 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 2079 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 2080 2081 BB->addSuccessor(loop1MBB); 2082 loop1MBB->addSuccessor(sinkMBB); 2083 loop1MBB->addSuccessor(loop2MBB); 2084 loop2MBB->addSuccessor(loop1MBB); 2085 loop2MBB->addSuccessor(sinkMBB); 2086 sinkMBB->addSuccessor(exitMBB); 2087 2088 // FIXME: computation of newval2 can be moved to loop2MBB. 2089 // thisMBB: 2090 // addiu masklsb2,$0,-4 # 0xfffffffc 2091 // and alignedaddr,ptr,masklsb2 2092 // andi ptrlsb2,ptr,3 2093 // sll shiftamt,ptrlsb2,3 2094 // ori maskupper,$0,255 # 0xff 2095 // sll mask,maskupper,shiftamt 2096 // nor mask2,$0,mask 2097 // andi maskedcmpval,cmpval,255 2098 // sll shiftedcmpval,maskedcmpval,shiftamt 2099 // andi maskednewval,newval,255 2100 // sll shiftednewval,maskednewval,shiftamt 2101 int64_t MaskImm = (Size == 1) ? 255 : 65535; 2102 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2) 2103 .addReg(Mips::ZERO).addImm(-4); 2104 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr) 2105 .addReg(Ptr).addReg(MaskLSB2); 2106 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 2107 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 2108 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper) 2109 .addReg(Mips::ZERO).addImm(MaskImm); 2110 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask) 2111 .addReg(ShiftAmt).addReg(MaskUpper); 2112 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 2113 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedCmpVal) 2114 .addReg(CmpVal).addImm(MaskImm); 2115 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedCmpVal) 2116 .addReg(ShiftAmt).addReg(MaskedCmpVal); 2117 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedNewVal) 2118 .addReg(NewVal).addImm(MaskImm); 2119 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedNewVal) 2120 .addReg(ShiftAmt).addReg(MaskedNewVal); 2121 2122 // loop1MBB: 2123 // ll oldval,0(alginedaddr) 2124 // and maskedoldval0,oldval,mask 2125 // bne maskedoldval0,shiftedcmpval,sinkMBB 2126 BB = loop1MBB; 2127 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 2128 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0) 2129 .addReg(OldVal).addReg(Mask); 2130 BuildMI(BB, dl, TII->get(Mips::BNE)) 2131 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB); 2132 2133 // loop2MBB: 2134 // and maskedoldval1,oldval,mask2 2135 // or storeval,maskedoldval1,shiftednewval 2136 // sc success,storeval,0(alignedaddr) 2137 // beq success,$0,loop1MBB 2138 BB = loop2MBB; 2139 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1) 2140 .addReg(OldVal).addReg(Mask2); 2141 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal) 2142 .addReg(MaskedOldVal1).addReg(ShiftedNewVal); 2143 BuildMI(BB, dl, TII->get(SC), Success) 2144 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 2145 BuildMI(BB, dl, TII->get(Mips::BEQ)) 2146 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB); 2147 2148 // sinkMBB: 2149 // srl srlres,maskedoldval0,shiftamt 2150 // sll sllres,srlres,24 2151 // sra dest,sllres,24 2152 BB = sinkMBB; 2153 int64_t ShiftImm = (Size == 1) ? 24 : 16; 2154 2155 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes) 2156 .addReg(ShiftAmt).addReg(MaskedOldVal0); 2157 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes) 2158 .addReg(SrlRes).addImm(ShiftImm); 2159 BuildMI(BB, dl, TII->get(Mips::SRA), Dest) 2160 .addReg(SllRes).addImm(ShiftImm); 2161 2162 MI->eraseFromParent(); // The instruction is gone now. 2163 2164 return exitMBB; 2165} 2166 2167//===----------------------------------------------------------------------===// 2168// Misc Lower Operation implementation 2169//===----------------------------------------------------------------------===// 2170SDValue MipsTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const { 2171 SDValue Chain = Op.getOperand(0); 2172 SDValue Table = Op.getOperand(1); 2173 SDValue Index = Op.getOperand(2); 2174 DebugLoc DL = Op.getDebugLoc(); 2175 EVT PTy = getPointerTy(); 2176 unsigned EntrySize = 2177 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(*getDataLayout()); 2178 2179 Index = DAG.getNode(ISD::MUL, DL, PTy, Index, 2180 DAG.getConstant(EntrySize, PTy)); 2181 SDValue Addr = DAG.getNode(ISD::ADD, DL, PTy, Index, Table); 2182 2183 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8); 2184 Addr = DAG.getExtLoad(ISD::SEXTLOAD, DL, PTy, Chain, Addr, 2185 MachinePointerInfo::getJumpTable(), MemVT, false, false, 2186 0); 2187 Chain = Addr.getValue(1); 2188 2189 if ((getTargetMachine().getRelocationModel() == Reloc::PIC_) || IsN64) { 2190 // For PIC, the sequence is: 2191 // BRIND(load(Jumptable + index) + RelocBase) 2192 // RelocBase can be JumpTable, GOT or some sort of global base. 2193 Addr = DAG.getNode(ISD::ADD, DL, PTy, Addr, 2194 getPICJumpTableRelocBase(Table, DAG)); 2195 } 2196 2197 return DAG.getNode(ISD::BRIND, DL, MVT::Other, Chain, Addr); 2198} 2199 2200SDValue MipsTargetLowering:: 2201LowerBRCOND(SDValue Op, SelectionDAG &DAG) const 2202{ 2203 // The first operand is the chain, the second is the condition, the third is 2204 // the block to branch to if the condition is true. 2205 SDValue Chain = Op.getOperand(0); 2206 SDValue Dest = Op.getOperand(2); 2207 DebugLoc dl = Op.getDebugLoc(); 2208 2209 SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1)); 2210 2211 // Return if flag is not set by a floating point comparison. 2212 if (CondRes.getOpcode() != MipsISD::FPCmp) 2213 return Op; 2214 2215 SDValue CCNode = CondRes.getOperand(2); 2216 Mips::CondCode CC = 2217 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 2218 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32); 2219 2220 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode, 2221 Dest, CondRes); 2222} 2223 2224SDValue MipsTargetLowering:: 2225LowerSELECT(SDValue Op, SelectionDAG &DAG) const 2226{ 2227 SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0)); 2228 2229 // Return if flag is not set by a floating point comparison. 2230 if (Cond.getOpcode() != MipsISD::FPCmp) 2231 return Op; 2232 2233 return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 2234 Op.getDebugLoc()); 2235} 2236 2237SDValue MipsTargetLowering:: 2238LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const 2239{ 2240 DebugLoc DL = Op.getDebugLoc(); 2241 EVT Ty = Op.getOperand(0).getValueType(); 2242 SDValue Cond = DAG.getNode(ISD::SETCC, DL, getSetCCResultType(Ty), 2243 Op.getOperand(0), Op.getOperand(1), 2244 Op.getOperand(4)); 2245 2246 return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2), 2247 Op.getOperand(3)); 2248} 2249 2250SDValue MipsTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 2251 SDValue Cond = CreateFPCmp(DAG, Op); 2252 2253 assert(Cond.getOpcode() == MipsISD::FPCmp && 2254 "Floating point operand expected."); 2255 2256 SDValue True = DAG.getConstant(1, MVT::i32); 2257 SDValue False = DAG.getConstant(0, MVT::i32); 2258 2259 return CreateCMovFP(DAG, Cond, True, False, Op.getDebugLoc()); 2260} 2261 2262SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op, 2263 SelectionDAG &DAG) const { 2264 // FIXME there isn't actually debug info here 2265 DebugLoc dl = Op.getDebugLoc(); 2266 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 2267 2268 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) { 2269 const MipsTargetObjectFile &TLOF = 2270 (const MipsTargetObjectFile&)getObjFileLowering(); 2271 2272 // %gp_rel relocation 2273 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) { 2274 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 2275 MipsII::MO_GPREL); 2276 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, 2277 DAG.getVTList(MVT::i32), &GA, 1); 2278 SDValue GPReg = DAG.getRegister(Mips::GP, MVT::i32); 2279 return DAG.getNode(ISD::ADD, dl, MVT::i32, GPReg, GPRelNode); 2280 } 2281 2282 // %hi/%lo relocation 2283 return getAddrNonPIC(Op, DAG); 2284 } 2285 2286 if (GV->hasInternalLinkage() || (GV->hasLocalLinkage() && !isa<Function>(GV))) 2287 return getAddrLocal(Op, DAG, HasMips64); 2288 2289 if (LargeGOT) 2290 return getAddrGlobalLargeGOT(Op, DAG, MipsII::MO_GOT_HI16, 2291 MipsII::MO_GOT_LO16); 2292 2293 return getAddrGlobal(Op, DAG, 2294 HasMips64 ? MipsII::MO_GOT_DISP : MipsII::MO_GOT16); 2295} 2296 2297SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op, 2298 SelectionDAG &DAG) const { 2299 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) 2300 return getAddrNonPIC(Op, DAG); 2301 2302 return getAddrLocal(Op, DAG, HasMips64); 2303} 2304 2305SDValue MipsTargetLowering:: 2306LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 2307{ 2308 // If the relocation model is PIC, use the General Dynamic TLS Model or 2309 // Local Dynamic TLS model, otherwise use the Initial Exec or 2310 // Local Exec TLS Model. 2311 2312 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 2313 DebugLoc dl = GA->getDebugLoc(); 2314 const GlobalValue *GV = GA->getGlobal(); 2315 EVT PtrVT = getPointerTy(); 2316 2317 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 2318 2319 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) { 2320 // General Dynamic and Local Dynamic TLS Model. 2321 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM 2322 : MipsII::MO_TLSGD; 2323 2324 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, Flag); 2325 SDValue Argument = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, 2326 GetGlobalReg(DAG, PtrVT), TGA); 2327 unsigned PtrSize = PtrVT.getSizeInBits(); 2328 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize); 2329 2330 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT); 2331 2332 ArgListTy Args; 2333 ArgListEntry Entry; 2334 Entry.Node = Argument; 2335 Entry.Ty = PtrTy; 2336 Args.push_back(Entry); 2337 2338 TargetLowering::CallLoweringInfo CLI(DAG.getEntryNode(), PtrTy, 2339 false, false, false, false, 0, CallingConv::C, 2340 /*isTailCall=*/false, /*doesNotRet=*/false, 2341 /*isReturnValueUsed=*/true, 2342 TlsGetAddr, Args, DAG, dl); 2343 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 2344 2345 SDValue Ret = CallResult.first; 2346 2347 if (model != TLSModel::LocalDynamic) 2348 return Ret; 2349 2350 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 2351 MipsII::MO_DTPREL_HI); 2352 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi); 2353 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 2354 MipsII::MO_DTPREL_LO); 2355 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo); 2356 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Ret); 2357 return DAG.getNode(ISD::ADD, dl, PtrVT, Add, Lo); 2358 } 2359 2360 SDValue Offset; 2361 if (model == TLSModel::InitialExec) { 2362 // Initial Exec TLS Model 2363 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 2364 MipsII::MO_GOTTPREL); 2365 TGA = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, GetGlobalReg(DAG, PtrVT), 2366 TGA); 2367 Offset = DAG.getLoad(PtrVT, dl, 2368 DAG.getEntryNode(), TGA, MachinePointerInfo(), 2369 false, false, false, 0); 2370 } else { 2371 // Local Exec TLS Model 2372 assert(model == TLSModel::LocalExec); 2373 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 2374 MipsII::MO_TPREL_HI); 2375 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 2376 MipsII::MO_TPREL_LO); 2377 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi); 2378 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo); 2379 Offset = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); 2380 } 2381 2382 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, dl, PtrVT); 2383 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 2384} 2385 2386SDValue MipsTargetLowering:: 2387LowerJumpTable(SDValue Op, SelectionDAG &DAG) const 2388{ 2389 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) 2390 return getAddrNonPIC(Op, DAG); 2391 2392 return getAddrLocal(Op, DAG, HasMips64); 2393} 2394 2395SDValue MipsTargetLowering:: 2396LowerConstantPool(SDValue Op, SelectionDAG &DAG) const 2397{ 2398 // gp_rel relocation 2399 // FIXME: we should reference the constant pool using small data sections, 2400 // but the asm printer currently doesn't support this feature without 2401 // hacking it. This feature should come soon so we can uncomment the 2402 // stuff below. 2403 //if (IsInSmallSection(C->getType())) { 2404 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP); 2405 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); 2406 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode); 2407 2408 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) 2409 return getAddrNonPIC(Op, DAG); 2410 2411 return getAddrLocal(Op, DAG, HasMips64); 2412} 2413 2414SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 2415 MachineFunction &MF = DAG.getMachineFunction(); 2416 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 2417 2418 DebugLoc dl = Op.getDebugLoc(); 2419 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 2420 getPointerTy()); 2421 2422 // vastart just stores the address of the VarArgsFrameIndex slot into the 2423 // memory location argument. 2424 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 2425 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1), 2426 MachinePointerInfo(SV), false, false, 0); 2427} 2428 2429static SDValue LowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasR2) { 2430 EVT TyX = Op.getOperand(0).getValueType(); 2431 EVT TyY = Op.getOperand(1).getValueType(); 2432 SDValue Const1 = DAG.getConstant(1, MVT::i32); 2433 SDValue Const31 = DAG.getConstant(31, MVT::i32); 2434 DebugLoc DL = Op.getDebugLoc(); 2435 SDValue Res; 2436 2437 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 2438 // to i32. 2439 SDValue X = (TyX == MVT::f32) ? 2440 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 2441 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 2442 Const1); 2443 SDValue Y = (TyY == MVT::f32) ? 2444 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) : 2445 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1), 2446 Const1); 2447 2448 if (HasR2) { 2449 // ext E, Y, 31, 1 ; extract bit31 of Y 2450 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X 2451 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1); 2452 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X); 2453 } else { 2454 // sll SllX, X, 1 2455 // srl SrlX, SllX, 1 2456 // srl SrlY, Y, 31 2457 // sll SllY, SrlX, 31 2458 // or Or, SrlX, SllY 2459 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 2460 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 2461 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); 2462 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31); 2463 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY); 2464 } 2465 2466 if (TyX == MVT::f32) 2467 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res); 2468 2469 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2470 Op.getOperand(0), DAG.getConstant(0, MVT::i32)); 2471 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 2472} 2473 2474static SDValue LowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasR2) { 2475 unsigned WidthX = Op.getOperand(0).getValueSizeInBits(); 2476 unsigned WidthY = Op.getOperand(1).getValueSizeInBits(); 2477 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY); 2478 SDValue Const1 = DAG.getConstant(1, MVT::i32); 2479 DebugLoc DL = Op.getDebugLoc(); 2480 2481 // Bitcast to integer nodes. 2482 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0)); 2483 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1)); 2484 2485 if (HasR2) { 2486 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y 2487 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X 2488 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y, 2489 DAG.getConstant(WidthY - 1, MVT::i32), Const1); 2490 2491 if (WidthX > WidthY) 2492 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E); 2493 else if (WidthY > WidthX) 2494 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E); 2495 2496 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E, 2497 DAG.getConstant(WidthX - 1, MVT::i32), Const1, X); 2498 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I); 2499 } 2500 2501 // (d)sll SllX, X, 1 2502 // (d)srl SrlX, SllX, 1 2503 // (d)srl SrlY, Y, width(Y)-1 2504 // (d)sll SllY, SrlX, width(Y)-1 2505 // or Or, SrlX, SllY 2506 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1); 2507 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); 2508 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, 2509 DAG.getConstant(WidthY - 1, MVT::i32)); 2510 2511 if (WidthX > WidthY) 2512 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY); 2513 else if (WidthY > WidthX) 2514 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY); 2515 2516 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY, 2517 DAG.getConstant(WidthX - 1, MVT::i32)); 2518 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY); 2519 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or); 2520} 2521 2522SDValue 2523MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 2524 if (Subtarget->hasMips64()) 2525 return LowerFCOPYSIGN64(Op, DAG, Subtarget->hasMips32r2()); 2526 2527 return LowerFCOPYSIGN32(Op, DAG, Subtarget->hasMips32r2()); 2528} 2529 2530static SDValue LowerFABS32(SDValue Op, SelectionDAG &DAG, bool HasR2) { 2531 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32); 2532 DebugLoc DL = Op.getDebugLoc(); 2533 2534 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 2535 // to i32. 2536 SDValue X = (Op.getValueType() == MVT::f32) ? 2537 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 2538 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 2539 Const1); 2540 2541 // Clear MSB. 2542 if (HasR2) 2543 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, 2544 DAG.getRegister(Mips::ZERO, MVT::i32), 2545 DAG.getConstant(31, MVT::i32), Const1, X); 2546 else { 2547 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 2548 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 2549 } 2550 2551 if (Op.getValueType() == MVT::f32) 2552 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res); 2553 2554 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2555 Op.getOperand(0), DAG.getConstant(0, MVT::i32)); 2556 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 2557} 2558 2559static SDValue LowerFABS64(SDValue Op, SelectionDAG &DAG, bool HasR2) { 2560 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32); 2561 DebugLoc DL = Op.getDebugLoc(); 2562 2563 // Bitcast to integer node. 2564 SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0)); 2565 2566 // Clear MSB. 2567 if (HasR2) 2568 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64, 2569 DAG.getRegister(Mips::ZERO_64, MVT::i64), 2570 DAG.getConstant(63, MVT::i32), Const1, X); 2571 else { 2572 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1); 2573 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1); 2574 } 2575 2576 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res); 2577} 2578 2579SDValue 2580MipsTargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const { 2581 if (Subtarget->hasMips64() && (Op.getValueType() == MVT::f64)) 2582 return LowerFABS64(Op, DAG, Subtarget->hasMips32r2()); 2583 2584 return LowerFABS32(Op, DAG, Subtarget->hasMips32r2()); 2585} 2586 2587SDValue MipsTargetLowering:: 2588LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 2589 // check the depth 2590 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 2591 "Frame address can only be determined for current frame."); 2592 2593 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2594 MFI->setFrameAddressIsTaken(true); 2595 EVT VT = Op.getValueType(); 2596 DebugLoc dl = Op.getDebugLoc(); 2597 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 2598 IsN64 ? Mips::FP_64 : Mips::FP, VT); 2599 return FrameAddr; 2600} 2601 2602SDValue MipsTargetLowering::LowerRETURNADDR(SDValue Op, 2603 SelectionDAG &DAG) const { 2604 // check the depth 2605 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 2606 "Return address can be determined only for current frame."); 2607 2608 MachineFunction &MF = DAG.getMachineFunction(); 2609 MachineFrameInfo *MFI = MF.getFrameInfo(); 2610 MVT VT = Op.getSimpleValueType(); 2611 unsigned RA = IsN64 ? Mips::RA_64 : Mips::RA; 2612 MFI->setReturnAddressIsTaken(true); 2613 2614 // Return RA, which contains the return address. Mark it an implicit live-in. 2615 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); 2616 return DAG.getCopyFromReg(DAG.getEntryNode(), Op.getDebugLoc(), Reg, VT); 2617} 2618 2619// An EH_RETURN is the result of lowering llvm.eh.return which in turn is 2620// generated from __builtin_eh_return (offset, handler) 2621// The effect of this is to adjust the stack pointer by "offset" 2622// and then branch to "handler". 2623SDValue MipsTargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) 2624 const { 2625 MachineFunction &MF = DAG.getMachineFunction(); 2626 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2627 2628 MipsFI->setCallsEhReturn(); 2629 SDValue Chain = Op.getOperand(0); 2630 SDValue Offset = Op.getOperand(1); 2631 SDValue Handler = Op.getOperand(2); 2632 DebugLoc DL = Op.getDebugLoc(); 2633 EVT Ty = IsN64 ? MVT::i64 : MVT::i32; 2634 2635 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and 2636 // EH_RETURN nodes, so that instructions are emitted back-to-back. 2637 unsigned OffsetReg = IsN64 ? Mips::V1_64 : Mips::V1; 2638 unsigned AddrReg = IsN64 ? Mips::V0_64 : Mips::V0; 2639 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue()); 2640 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1)); 2641 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain, 2642 DAG.getRegister(OffsetReg, Ty), 2643 DAG.getRegister(AddrReg, getPointerTy()), 2644 Chain.getValue(1)); 2645} 2646 2647// TODO: set SType according to the desired memory barrier behavior. 2648SDValue 2649MipsTargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const { 2650 unsigned SType = 0; 2651 DebugLoc dl = Op.getDebugLoc(); 2652 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0), 2653 DAG.getConstant(SType, MVT::i32)); 2654} 2655 2656SDValue MipsTargetLowering::LowerATOMIC_FENCE(SDValue Op, 2657 SelectionDAG &DAG) const { 2658 // FIXME: Need pseudo-fence for 'singlethread' fences 2659 // FIXME: Set SType for weaker fences where supported/appropriate. 2660 unsigned SType = 0; 2661 DebugLoc dl = Op.getDebugLoc(); 2662 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0), 2663 DAG.getConstant(SType, MVT::i32)); 2664} 2665 2666SDValue MipsTargetLowering::LowerShiftLeftParts(SDValue Op, 2667 SelectionDAG &DAG) const { 2668 DebugLoc DL = Op.getDebugLoc(); 2669 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2670 SDValue Shamt = Op.getOperand(2); 2671 2672 // if shamt < 32: 2673 // lo = (shl lo, shamt) 2674 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt)) 2675 // else: 2676 // lo = 0 2677 // hi = (shl lo, shamt[4:0]) 2678 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2679 DAG.getConstant(-1, MVT::i32)); 2680 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, 2681 DAG.getConstant(1, MVT::i32)); 2682 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo, 2683 Not); 2684 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt); 2685 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo); 2686 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt); 2687 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2688 DAG.getConstant(0x20, MVT::i32)); 2689 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, 2690 DAG.getConstant(0, MVT::i32), ShiftLeftLo); 2691 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or); 2692 2693 SDValue Ops[2] = {Lo, Hi}; 2694 return DAG.getMergeValues(Ops, 2, DL); 2695} 2696 2697SDValue MipsTargetLowering::LowerShiftRightParts(SDValue Op, SelectionDAG &DAG, 2698 bool IsSRA) const { 2699 DebugLoc DL = Op.getDebugLoc(); 2700 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2701 SDValue Shamt = Op.getOperand(2); 2702 2703 // if shamt < 32: 2704 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt)) 2705 // if isSRA: 2706 // hi = (sra hi, shamt) 2707 // else: 2708 // hi = (srl hi, shamt) 2709 // else: 2710 // if isSRA: 2711 // lo = (sra hi, shamt[4:0]) 2712 // hi = (sra hi, 31) 2713 // else: 2714 // lo = (srl hi, shamt[4:0]) 2715 // hi = 0 2716 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2717 DAG.getConstant(-1, MVT::i32)); 2718 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, 2719 DAG.getConstant(1, MVT::i32)); 2720 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not); 2721 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt); 2722 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo); 2723 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32, 2724 Hi, Shamt); 2725 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2726 DAG.getConstant(0x20, MVT::i32)); 2727 SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi, 2728 DAG.getConstant(31, MVT::i32)); 2729 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or); 2730 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, 2731 IsSRA ? Shift31 : DAG.getConstant(0, MVT::i32), 2732 ShiftRightHi); 2733 2734 SDValue Ops[2] = {Lo, Hi}; 2735 return DAG.getMergeValues(Ops, 2, DL); 2736} 2737 2738static SDValue CreateLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, 2739 SDValue Chain, SDValue Src, unsigned Offset) { 2740 SDValue Ptr = LD->getBasePtr(); 2741 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT(); 2742 EVT BasePtrVT = Ptr.getValueType(); 2743 DebugLoc DL = LD->getDebugLoc(); 2744 SDVTList VTList = DAG.getVTList(VT, MVT::Other); 2745 2746 if (Offset) 2747 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2748 DAG.getConstant(Offset, BasePtrVT)); 2749 2750 SDValue Ops[] = { Chain, Ptr, Src }; 2751 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT, 2752 LD->getMemOperand()); 2753} 2754 2755// Expand an unaligned 32 or 64-bit integer load node. 2756SDValue MipsTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const { 2757 LoadSDNode *LD = cast<LoadSDNode>(Op); 2758 EVT MemVT = LD->getMemoryVT(); 2759 2760 // Return if load is aligned or if MemVT is neither i32 nor i64. 2761 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) || 2762 ((MemVT != MVT::i32) && (MemVT != MVT::i64))) 2763 return SDValue(); 2764 2765 bool IsLittle = Subtarget->isLittle(); 2766 EVT VT = Op.getValueType(); 2767 ISD::LoadExtType ExtType = LD->getExtensionType(); 2768 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT); 2769 2770 assert((VT == MVT::i32) || (VT == MVT::i64)); 2771 2772 // Expand 2773 // (set dst, (i64 (load baseptr))) 2774 // to 2775 // (set tmp, (ldl (add baseptr, 7), undef)) 2776 // (set dst, (ldr baseptr, tmp)) 2777 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) { 2778 SDValue LDL = CreateLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef, 2779 IsLittle ? 7 : 0); 2780 return CreateLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL, 2781 IsLittle ? 0 : 7); 2782 } 2783 2784 SDValue LWL = CreateLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, 2785 IsLittle ? 3 : 0); 2786 SDValue LWR = CreateLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, 2787 IsLittle ? 0 : 3); 2788 2789 // Expand 2790 // (set dst, (i32 (load baseptr))) or 2791 // (set dst, (i64 (sextload baseptr))) or 2792 // (set dst, (i64 (extload baseptr))) 2793 // to 2794 // (set tmp, (lwl (add baseptr, 3), undef)) 2795 // (set dst, (lwr baseptr, tmp)) 2796 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) || 2797 (ExtType == ISD::EXTLOAD)) 2798 return LWR; 2799 2800 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)); 2801 2802 // Expand 2803 // (set dst, (i64 (zextload baseptr))) 2804 // to 2805 // (set tmp0, (lwl (add baseptr, 3), undef)) 2806 // (set tmp1, (lwr baseptr, tmp0)) 2807 // (set tmp2, (shl tmp1, 32)) 2808 // (set dst, (srl tmp2, 32)) 2809 DebugLoc DL = LD->getDebugLoc(); 2810 SDValue Const32 = DAG.getConstant(32, MVT::i32); 2811 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); 2812 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); 2813 SDValue Ops[] = { SRL, LWR.getValue(1) }; 2814 return DAG.getMergeValues(Ops, 2, DL); 2815} 2816 2817static SDValue CreateStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, 2818 SDValue Chain, unsigned Offset) { 2819 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue(); 2820 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType(); 2821 DebugLoc DL = SD->getDebugLoc(); 2822 SDVTList VTList = DAG.getVTList(MVT::Other); 2823 2824 if (Offset) 2825 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2826 DAG.getConstant(Offset, BasePtrVT)); 2827 2828 SDValue Ops[] = { Chain, Value, Ptr }; 2829 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT, 2830 SD->getMemOperand()); 2831} 2832 2833// Expand an unaligned 32 or 64-bit integer store node. 2834SDValue MipsTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const { 2835 StoreSDNode *SD = cast<StoreSDNode>(Op); 2836 EVT MemVT = SD->getMemoryVT(); 2837 2838 // Return if store is aligned or if MemVT is neither i32 nor i64. 2839 if ((SD->getAlignment() >= MemVT.getSizeInBits() / 8) || 2840 ((MemVT != MVT::i32) && (MemVT != MVT::i64))) 2841 return SDValue(); 2842 2843 bool IsLittle = Subtarget->isLittle(); 2844 SDValue Value = SD->getValue(), Chain = SD->getChain(); 2845 EVT VT = Value.getValueType(); 2846 2847 // Expand 2848 // (store val, baseptr) or 2849 // (truncstore val, baseptr) 2850 // to 2851 // (swl val, (add baseptr, 3)) 2852 // (swr val, baseptr) 2853 if ((VT == MVT::i32) || SD->isTruncatingStore()) { 2854 SDValue SWL = CreateStoreLR(MipsISD::SWL, DAG, SD, Chain, 2855 IsLittle ? 3 : 0); 2856 return CreateStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); 2857 } 2858 2859 assert(VT == MVT::i64); 2860 2861 // Expand 2862 // (store val, baseptr) 2863 // to 2864 // (sdl val, (add baseptr, 7)) 2865 // (sdr val, baseptr) 2866 SDValue SDL = CreateStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0); 2867 return CreateStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7); 2868} 2869 2870// This function expands mips intrinsic nodes which have 64-bit input operands 2871// or output values. 2872// 2873// out64 = intrinsic-node in64 2874// => 2875// lo = copy (extract-element (in64, 0)) 2876// hi = copy (extract-element (in64, 1)) 2877// mips-specific-node 2878// v0 = copy lo 2879// v1 = copy hi 2880// out64 = merge-values (v0, v1) 2881// 2882static SDValue LowerDSPIntr(SDValue Op, SelectionDAG &DAG, 2883 unsigned Opc, bool HasI64In, bool HasI64Out) { 2884 DebugLoc DL = Op.getDebugLoc(); 2885 bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other; 2886 SDValue Chain = HasChainIn ? Op->getOperand(0) : DAG.getEntryNode(); 2887 SmallVector<SDValue, 3> Ops; 2888 2889 if (HasI64In) { 2890 SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, 2891 Op->getOperand(1 + HasChainIn), 2892 DAG.getConstant(0, MVT::i32)); 2893 SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, 2894 Op->getOperand(1 + HasChainIn), 2895 DAG.getConstant(1, MVT::i32)); 2896 2897 Chain = DAG.getCopyToReg(Chain, DL, Mips::LO, InLo, SDValue()); 2898 Chain = DAG.getCopyToReg(Chain, DL, Mips::HI, InHi, Chain.getValue(1)); 2899 2900 Ops.push_back(Chain); 2901 Ops.append(Op->op_begin() + HasChainIn + 2, Op->op_end()); 2902 Ops.push_back(Chain.getValue(1)); 2903 } else { 2904 Ops.push_back(Chain); 2905 Ops.append(Op->op_begin() + HasChainIn + 1, Op->op_end()); 2906 } 2907 2908 if (!HasI64Out) 2909 return DAG.getNode(Opc, DL, Op->value_begin(), Op->getNumValues(), 2910 Ops.begin(), Ops.size()); 2911 2912 SDValue Intr = DAG.getNode(Opc, DL, DAG.getVTList(MVT::Other, MVT::Glue), 2913 Ops.begin(), Ops.size()); 2914 SDValue OutLo = DAG.getCopyFromReg(Intr.getValue(0), DL, Mips::LO, MVT::i32, 2915 Intr.getValue(1)); 2916 SDValue OutHi = DAG.getCopyFromReg(OutLo.getValue(1), DL, Mips::HI, MVT::i32, 2917 OutLo.getValue(2)); 2918 SDValue Out = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, OutLo, OutHi); 2919 2920 if (!HasChainIn) 2921 return Out; 2922 2923 SDValue Vals[] = { Out, OutHi.getValue(1) }; 2924 return DAG.getMergeValues(Vals, 2, DL); 2925} 2926 2927SDValue MipsTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, 2928 SelectionDAG &DAG) const { 2929 switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) { 2930 default: 2931 return SDValue(); 2932 case Intrinsic::mips_shilo: 2933 return LowerDSPIntr(Op, DAG, MipsISD::SHILO, true, true); 2934 case Intrinsic::mips_dpau_h_qbl: 2935 return LowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL, true, true); 2936 case Intrinsic::mips_dpau_h_qbr: 2937 return LowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR, true, true); 2938 case Intrinsic::mips_dpsu_h_qbl: 2939 return LowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL, true, true); 2940 case Intrinsic::mips_dpsu_h_qbr: 2941 return LowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR, true, true); 2942 case Intrinsic::mips_dpa_w_ph: 2943 return LowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH, true, true); 2944 case Intrinsic::mips_dps_w_ph: 2945 return LowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH, true, true); 2946 case Intrinsic::mips_dpax_w_ph: 2947 return LowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH, true, true); 2948 case Intrinsic::mips_dpsx_w_ph: 2949 return LowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH, true, true); 2950 case Intrinsic::mips_mulsa_w_ph: 2951 return LowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH, true, true); 2952 case Intrinsic::mips_mult: 2953 return LowerDSPIntr(Op, DAG, MipsISD::MULT, false, true); 2954 case Intrinsic::mips_multu: 2955 return LowerDSPIntr(Op, DAG, MipsISD::MULTU, false, true); 2956 case Intrinsic::mips_madd: 2957 return LowerDSPIntr(Op, DAG, MipsISD::MADD_DSP, true, true); 2958 case Intrinsic::mips_maddu: 2959 return LowerDSPIntr(Op, DAG, MipsISD::MADDU_DSP, true, true); 2960 case Intrinsic::mips_msub: 2961 return LowerDSPIntr(Op, DAG, MipsISD::MSUB_DSP, true, true); 2962 case Intrinsic::mips_msubu: 2963 return LowerDSPIntr(Op, DAG, MipsISD::MSUBU_DSP, true, true); 2964 } 2965} 2966 2967SDValue MipsTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, 2968 SelectionDAG &DAG) const { 2969 switch (cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue()) { 2970 default: 2971 return SDValue(); 2972 case Intrinsic::mips_extp: 2973 return LowerDSPIntr(Op, DAG, MipsISD::EXTP, true, false); 2974 case Intrinsic::mips_extpdp: 2975 return LowerDSPIntr(Op, DAG, MipsISD::EXTPDP, true, false); 2976 case Intrinsic::mips_extr_w: 2977 return LowerDSPIntr(Op, DAG, MipsISD::EXTR_W, true, false); 2978 case Intrinsic::mips_extr_r_w: 2979 return LowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W, true, false); 2980 case Intrinsic::mips_extr_rs_w: 2981 return LowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W, true, false); 2982 case Intrinsic::mips_extr_s_h: 2983 return LowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H, true, false); 2984 case Intrinsic::mips_mthlip: 2985 return LowerDSPIntr(Op, DAG, MipsISD::MTHLIP, true, true); 2986 case Intrinsic::mips_mulsaq_s_w_ph: 2987 return LowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH, true, true); 2988 case Intrinsic::mips_maq_s_w_phl: 2989 return LowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL, true, true); 2990 case Intrinsic::mips_maq_s_w_phr: 2991 return LowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR, true, true); 2992 case Intrinsic::mips_maq_sa_w_phl: 2993 return LowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL, true, true); 2994 case Intrinsic::mips_maq_sa_w_phr: 2995 return LowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR, true, true); 2996 case Intrinsic::mips_dpaq_s_w_ph: 2997 return LowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH, true, true); 2998 case Intrinsic::mips_dpsq_s_w_ph: 2999 return LowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH, true, true); 3000 case Intrinsic::mips_dpaq_sa_l_w: 3001 return LowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W, true, true); 3002 case Intrinsic::mips_dpsq_sa_l_w: 3003 return LowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W, true, true); 3004 case Intrinsic::mips_dpaqx_s_w_ph: 3005 return LowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH, true, true); 3006 case Intrinsic::mips_dpaqx_sa_w_ph: 3007 return LowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH, true, true); 3008 case Intrinsic::mips_dpsqx_s_w_ph: 3009 return LowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH, true, true); 3010 case Intrinsic::mips_dpsqx_sa_w_ph: 3011 return LowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH, true, true); 3012 } 3013} 3014 3015SDValue MipsTargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const { 3016 if (Op->getOperand(0).getOpcode() != ISD::FRAMEADDR 3017 || cast<ConstantSDNode> 3018 (Op->getOperand(0).getOperand(0))->getZExtValue() != 0 3019 || Op->getOperand(1).getOpcode() != ISD::FRAME_TO_ARGS_OFFSET) 3020 return SDValue(); 3021 3022 // The pattern 3023 // (add (frameaddr 0), (frame_to_args_offset)) 3024 // results from lowering llvm.eh.dwarf.cfa intrinsic. Transform it to 3025 // (add FrameObject, 0) 3026 // where FrameObject is a fixed StackObject with offset 0 which points to 3027 // the old stack pointer. 3028 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3029 EVT ValTy = Op->getValueType(0); 3030 int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false); 3031 SDValue InArgsAddr = DAG.getFrameIndex(FI, ValTy); 3032 return DAG.getNode(ISD::ADD, Op->getDebugLoc(), ValTy, InArgsAddr, 3033 DAG.getConstant(0, ValTy)); 3034} 3035 3036//===----------------------------------------------------------------------===// 3037// Calling Convention Implementation 3038//===----------------------------------------------------------------------===// 3039 3040//===----------------------------------------------------------------------===// 3041// TODO: Implement a generic logic using tblgen that can support this. 3042// Mips O32 ABI rules: 3043// --- 3044// i32 - Passed in A0, A1, A2, A3 and stack 3045// f32 - Only passed in f32 registers if no int reg has been used yet to hold 3046// an argument. Otherwise, passed in A1, A2, A3 and stack. 3047// f64 - Only passed in two aliased f32 registers if no int reg has been used 3048// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 3049// not used, it must be shadowed. If only A3 is avaiable, shadow it and 3050// go to stack. 3051// 3052// For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 3053//===----------------------------------------------------------------------===// 3054 3055static bool CC_MipsO32(unsigned ValNo, MVT ValVT, 3056 MVT LocVT, CCValAssign::LocInfo LocInfo, 3057 ISD::ArgFlagsTy ArgFlags, CCState &State) { 3058 3059 static const unsigned IntRegsSize=4, FloatRegsSize=2; 3060 3061 static const uint16_t IntRegs[] = { 3062 Mips::A0, Mips::A1, Mips::A2, Mips::A3 3063 }; 3064 static const uint16_t F32Regs[] = { 3065 Mips::F12, Mips::F14 3066 }; 3067 static const uint16_t F64Regs[] = { 3068 Mips::D6, Mips::D7 3069 }; 3070 3071 // Do not process byval args here. 3072 if (ArgFlags.isByVal()) 3073 return true; 3074 3075 // Promote i8 and i16 3076 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 3077 LocVT = MVT::i32; 3078 if (ArgFlags.isSExt()) 3079 LocInfo = CCValAssign::SExt; 3080 else if (ArgFlags.isZExt()) 3081 LocInfo = CCValAssign::ZExt; 3082 else 3083 LocInfo = CCValAssign::AExt; 3084 } 3085 3086 unsigned Reg; 3087 3088 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 3089 // is true: function is vararg, argument is 3rd or higher, there is previous 3090 // argument which is not f32 or f64. 3091 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 3092 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo; 3093 unsigned OrigAlign = ArgFlags.getOrigAlign(); 3094 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8); 3095 3096 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 3097 Reg = State.AllocateReg(IntRegs, IntRegsSize); 3098 // If this is the first part of an i64 arg, 3099 // the allocated register must be either A0 or A2. 3100 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 3101 Reg = State.AllocateReg(IntRegs, IntRegsSize); 3102 LocVT = MVT::i32; 3103 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 3104 // Allocate int register and shadow next int register. If first 3105 // available register is Mips::A1 or Mips::A3, shadow it too. 3106 Reg = State.AllocateReg(IntRegs, IntRegsSize); 3107 if (Reg == Mips::A1 || Reg == Mips::A3) 3108 Reg = State.AllocateReg(IntRegs, IntRegsSize); 3109 State.AllocateReg(IntRegs, IntRegsSize); 3110 LocVT = MVT::i32; 3111 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 3112 // we are guaranteed to find an available float register 3113 if (ValVT == MVT::f32) { 3114 Reg = State.AllocateReg(F32Regs, FloatRegsSize); 3115 // Shadow int register 3116 State.AllocateReg(IntRegs, IntRegsSize); 3117 } else { 3118 Reg = State.AllocateReg(F64Regs, FloatRegsSize); 3119 // Shadow int registers 3120 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize); 3121 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 3122 State.AllocateReg(IntRegs, IntRegsSize); 3123 State.AllocateReg(IntRegs, IntRegsSize); 3124 } 3125 } else 3126 llvm_unreachable("Cannot handle this ValVT."); 3127 3128 if (!Reg) { 3129 unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3, 3130 OrigAlign); 3131 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 3132 } else 3133 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3134 3135 return false; 3136} 3137 3138#include "MipsGenCallingConv.inc" 3139 3140//===----------------------------------------------------------------------===// 3141// Call Calling Convention Implementation 3142//===----------------------------------------------------------------------===// 3143 3144static const unsigned O32IntRegsSize = 4; 3145 3146// Return next O32 integer argument register. 3147static unsigned getNextIntArgReg(unsigned Reg) { 3148 assert((Reg == Mips::A0) || (Reg == Mips::A2)); 3149 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3; 3150} 3151 3152/// IsEligibleForTailCallOptimization - Check whether the call is eligible 3153/// for tail call optimization. 3154bool MipsTargetLowering:: 3155IsEligibleForTailCallOptimization(const MipsCC &MipsCCInfo, 3156 unsigned NextStackOffset, 3157 const MipsFunctionInfo& FI) const { 3158 if (!EnableMipsTailCalls) 3159 return false; 3160 3161 // No tail call optimization for mips16. 3162 if (Subtarget->inMips16Mode()) 3163 return false; 3164 3165 // Return false if either the callee or caller has a byval argument. 3166 if (MipsCCInfo.hasByValArg() || FI.hasByvalArg()) 3167 return false; 3168 3169 // Return true if the callee's argument area is no larger than the 3170 // caller's. 3171 return NextStackOffset <= FI.getIncomingArgSize(); 3172} 3173 3174SDValue 3175MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset, 3176 SDValue Chain, SDValue Arg, DebugLoc DL, 3177 bool IsTailCall, SelectionDAG &DAG) const { 3178 if (!IsTailCall) { 3179 SDValue PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, 3180 DAG.getIntPtrConstant(Offset)); 3181 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), false, 3182 false, 0); 3183 } 3184 3185 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3186 int FI = MFI->CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false); 3187 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 3188 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(), 3189 /*isVolatile=*/ true, false, 0); 3190} 3191 3192// 3193// The Mips16 hard float is a crazy quilt inherited from gcc. I have a much 3194// cleaner way to do all of this but it will have to wait until the traditional 3195// gcc mechanism is completed. 3196// 3197// For Pic, in order for Mips16 code to call Mips32 code which according the abi 3198// have either arguments or returned values placed in floating point registers, 3199// we use a set of helper functions. (This includes functions which return type 3200// complex which on Mips are returned in a pair of floating point registers). 3201// 3202// This is an encoding that we inherited from gcc. 3203// In Mips traditional O32, N32 ABI, floating point numbers are passed in 3204// floating point argument registers 1,2 only when the first and optionally 3205// the second arguments are float (sf) or double (df). 3206// For Mips16 we are only concerned with the situations where floating point 3207// arguments are being passed in floating point registers by the ABI, because 3208// Mips16 mode code cannot execute floating point instructions to load those 3209// values and hence helper functions are needed. 3210// The possibilities are (), (sf), (sf, sf), (sf, df), (df), (df, sf), (df, df) 3211// the helper function suffixs for these are: 3212// 0, 1, 5, 9, 2, 6, 10 3213// this suffix can then be calculated as follows: 3214// for a given argument Arg: 3215// Arg1x, Arg2x = 1 : Arg is sf 3216// 2 : Arg is df 3217// 0: Arg is neither sf or df 3218// So this stub is the string for number Arg1x + Arg2x*4. 3219// However not all numbers between 0 and 10 are possible, we check anyway and 3220// assert if the impossible exists. 3221// 3222 3223unsigned int MipsTargetLowering::getMips16HelperFunctionStubNumber 3224 (ArgListTy &Args) const { 3225 unsigned int resultNum = 0; 3226 if (Args.size() >= 1) { 3227 Type *t = Args[0].Ty; 3228 if (t->isFloatTy()) { 3229 resultNum = 1; 3230 } 3231 else if (t->isDoubleTy()) { 3232 resultNum = 2; 3233 } 3234 } 3235 if (resultNum) { 3236 if (Args.size() >=2) { 3237 Type *t = Args[1].Ty; 3238 if (t->isFloatTy()) { 3239 resultNum += 4; 3240 } 3241 else if (t->isDoubleTy()) { 3242 resultNum += 8; 3243 } 3244 } 3245 } 3246 return resultNum; 3247} 3248 3249// 3250// prefixs are attached to stub numbers depending on the return type . 3251// return type: float sf_ 3252// double df_ 3253// single complex sc_ 3254// double complext dc_ 3255// others NO PREFIX 3256// 3257// 3258// The full name of a helper function is__mips16_call_stub + 3259// return type dependent prefix + stub number 3260// 3261// 3262// This is something that probably should be in a different source file and 3263// perhaps done differently but my main purpose is to not waste runtime 3264// on something that we can enumerate in the source. Another possibility is 3265// to have a python script to generate these mapping tables. This will do 3266// for now. There are a whole series of helper function mapping arrays, one 3267// for each return type class as outlined above. There there are 11 possible 3268// entries. Ones with 0 are ones which should never be selected 3269// 3270// All the arrays are similar except for ones which return neither 3271// sf, df, sc, dc, in which only care about ones which have sf or df as a 3272// first parameter. 3273// 3274#define P_ "__mips16_call_stub_" 3275#define MAX_STUB_NUMBER 10 3276#define T1 P "1", P "2", 0, 0, P "5", P "6", 0, 0, P "9", P "10" 3277#define T P "0" , T1 3278#define P P_ 3279static char const * vMips16Helper[MAX_STUB_NUMBER+1] = 3280 {0, T1 }; 3281#undef P 3282#define P P_ "sf_" 3283static char const * sfMips16Helper[MAX_STUB_NUMBER+1] = 3284 { T }; 3285#undef P 3286#define P P_ "df_" 3287static char const * dfMips16Helper[MAX_STUB_NUMBER+1] = 3288 { T }; 3289#undef P 3290#define P P_ "sc_" 3291static char const * scMips16Helper[MAX_STUB_NUMBER+1] = 3292 { T }; 3293#undef P 3294#define P P_ "dc_" 3295static char const * dcMips16Helper[MAX_STUB_NUMBER+1] = 3296 { T }; 3297#undef P 3298#undef P_ 3299 3300 3301const char* MipsTargetLowering:: 3302 getMips16HelperFunction 3303 (Type* RetTy, ArgListTy &Args, bool &needHelper) const { 3304 const unsigned int stubNum = getMips16HelperFunctionStubNumber(Args); 3305#ifndef NDEBUG 3306 const unsigned int maxStubNum = 10; 3307 assert(stubNum <= maxStubNum); 3308 const bool validStubNum[maxStubNum+1] = 3309 {true, true, true, false, false, true, true, false, false, true, true}; 3310 assert(validStubNum[stubNum]); 3311#endif 3312 const char *result; 3313 if (RetTy->isFloatTy()) { 3314 result = sfMips16Helper[stubNum]; 3315 } 3316 else if (RetTy ->isDoubleTy()) { 3317 result = dfMips16Helper[stubNum]; 3318 } 3319 else if (RetTy->isStructTy()) { 3320 // check if it's complex 3321 if (RetTy->getNumContainedTypes() == 2) { 3322 if ((RetTy->getContainedType(0)->isFloatTy()) && 3323 (RetTy->getContainedType(1)->isFloatTy())) { 3324 result = scMips16Helper[stubNum]; 3325 } 3326 else if ((RetTy->getContainedType(0)->isDoubleTy()) && 3327 (RetTy->getContainedType(1)->isDoubleTy())) { 3328 result = dcMips16Helper[stubNum]; 3329 } 3330 else { 3331 llvm_unreachable("Uncovered condition"); 3332 } 3333 } 3334 else { 3335 llvm_unreachable("Uncovered condition"); 3336 } 3337 } 3338 else { 3339 if (stubNum == 0) { 3340 needHelper = false; 3341 return ""; 3342 } 3343 result = vMips16Helper[stubNum]; 3344 } 3345 needHelper = true; 3346 return result; 3347} 3348 3349/// LowerCall - functions arguments are copied from virtual regs to 3350/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 3351SDValue 3352MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 3353 SmallVectorImpl<SDValue> &InVals) const { 3354 SelectionDAG &DAG = CLI.DAG; 3355 DebugLoc &dl = CLI.DL; 3356 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; 3357 SmallVector<SDValue, 32> &OutVals = CLI.OutVals; 3358 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; 3359 SDValue Chain = CLI.Chain; 3360 SDValue Callee = CLI.Callee; 3361 bool &isTailCall = CLI.IsTailCall; 3362 CallingConv::ID CallConv = CLI.CallConv; 3363 bool isVarArg = CLI.IsVarArg; 3364 3365 const char* mips16HelperFunction = 0; 3366 bool needMips16Helper = false; 3367 3368 if (Subtarget->inMips16Mode() && getTargetMachine().Options.UseSoftFloat && 3369 Mips16HardFloat) { 3370 // 3371 // currently we don't have symbols tagged with the mips16 or mips32 3372 // qualifier so we will assume that we don't know what kind it is. 3373 // and generate the helper 3374 // 3375 bool lookupHelper = true; 3376 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 3377 if (noHelperNeeded.find(S->getSymbol()) != noHelperNeeded.end()) { 3378 lookupHelper = false; 3379 } 3380 } 3381 if (lookupHelper) mips16HelperFunction = 3382 getMips16HelperFunction(CLI.RetTy, CLI.Args, needMips16Helper); 3383 3384 } 3385 MachineFunction &MF = DAG.getMachineFunction(); 3386 MachineFrameInfo *MFI = MF.getFrameInfo(); 3387 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering(); 3388 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 3389 3390 // Analyze operands of the call, assigning locations to each operand. 3391 SmallVector<CCValAssign, 16> ArgLocs; 3392 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 3393 getTargetMachine(), ArgLocs, *DAG.getContext()); 3394 MipsCC MipsCCInfo(CallConv, IsO32, CCInfo); 3395 3396 MipsCCInfo.analyzeCallOperands(Outs, isVarArg, 3397 getTargetMachine().Options.UseSoftFloat, 3398 Callee.getNode(), CLI.Args); 3399 3400 // Get a count of how many bytes are to be pushed on the stack. 3401 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 3402 3403 // Check if it's really possible to do a tail call. 3404 if (isTailCall) 3405 isTailCall = 3406 IsEligibleForTailCallOptimization(MipsCCInfo, NextStackOffset, 3407 *MF.getInfo<MipsFunctionInfo>()); 3408 3409 if (isTailCall) 3410 ++NumTailCalls; 3411 3412 // Chain is the output chain of the last Load/Store or CopyToReg node. 3413 // ByValChain is the output chain of the last Memcpy node created for copying 3414 // byval arguments to the stack. 3415 unsigned StackAlignment = TFL->getStackAlignment(); 3416 NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment); 3417 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true); 3418 3419 if (!isTailCall) 3420 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal); 3421 3422 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, 3423 IsN64 ? Mips::SP_64 : Mips::SP, 3424 getPointerTy()); 3425 3426 // With EABI is it possible to have 16 args on registers. 3427 std::deque< std::pair<unsigned, SDValue> > RegsToPass; 3428 SmallVector<SDValue, 8> MemOpChains; 3429 MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin(); 3430 3431 // Walk the register/memloc assignments, inserting copies/loads. 3432 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 3433 SDValue Arg = OutVals[i]; 3434 CCValAssign &VA = ArgLocs[i]; 3435 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); 3436 ISD::ArgFlagsTy Flags = Outs[i].Flags; 3437 3438 // ByVal Arg. 3439 if (Flags.isByVal()) { 3440 assert(Flags.getByValSize() && 3441 "ByVal args of size 0 should have been ignored by front-end."); 3442 assert(ByValArg != MipsCCInfo.byval_end()); 3443 assert(!isTailCall && 3444 "Do not tail-call optimize if there is a byval argument."); 3445 passByValArg(Chain, dl, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg, 3446 MipsCCInfo, *ByValArg, Flags, Subtarget->isLittle()); 3447 ++ByValArg; 3448 continue; 3449 } 3450 3451 // Promote the value if needed. 3452 switch (VA.getLocInfo()) { 3453 default: llvm_unreachable("Unknown loc info!"); 3454 case CCValAssign::Full: 3455 if (VA.isRegLoc()) { 3456 if ((ValVT == MVT::f32 && LocVT == MVT::i32) || 3457 (ValVT == MVT::f64 && LocVT == MVT::i64) || 3458 (ValVT == MVT::i64 && LocVT == MVT::f64)) 3459 Arg = DAG.getNode(ISD::BITCAST, dl, LocVT, Arg); 3460 else if (ValVT == MVT::f64 && LocVT == MVT::i32) { 3461 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 3462 Arg, DAG.getConstant(0, MVT::i32)); 3463 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 3464 Arg, DAG.getConstant(1, MVT::i32)); 3465 if (!Subtarget->isLittle()) 3466 std::swap(Lo, Hi); 3467 unsigned LocRegLo = VA.getLocReg(); 3468 unsigned LocRegHigh = getNextIntArgReg(LocRegLo); 3469 RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); 3470 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); 3471 continue; 3472 } 3473 } 3474 break; 3475 case CCValAssign::SExt: 3476 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, LocVT, Arg); 3477 break; 3478 case CCValAssign::ZExt: 3479 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, LocVT, Arg); 3480 break; 3481 case CCValAssign::AExt: 3482 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, LocVT, Arg); 3483 break; 3484 } 3485 3486 // Arguments that can be passed on register must be kept at 3487 // RegsToPass vector 3488 if (VA.isRegLoc()) { 3489 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 3490 continue; 3491 } 3492 3493 // Register can't get to this point... 3494 assert(VA.isMemLoc()); 3495 3496 // emit ISD::STORE whichs stores the 3497 // parameter value to a stack Location 3498 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(), 3499 Chain, Arg, dl, isTailCall, DAG)); 3500 } 3501 3502 // Transform all store nodes into one single node because all store 3503 // nodes are independent of each other. 3504 if (!MemOpChains.empty()) 3505 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3506 &MemOpChains[0], MemOpChains.size()); 3507 3508 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 3509 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 3510 // node so that legalize doesn't hack it. 3511 bool IsPICCall = (IsN64 || IsPIC); // true if calls are translated to jalr $25 3512 bool GlobalOrExternal = false, InternalLinkage = false; 3513 SDValue CalleeLo; 3514 3515 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 3516 if (IsPICCall) { 3517 InternalLinkage = G->getGlobal()->hasInternalLinkage(); 3518 3519 if (InternalLinkage) 3520 Callee = getAddrLocal(Callee, DAG, HasMips64); 3521 else if (LargeGOT) 3522 Callee = getAddrGlobalLargeGOT(Callee, DAG, MipsII::MO_CALL_HI16, 3523 MipsII::MO_CALL_LO16); 3524 else 3525 Callee = getAddrGlobal(Callee, DAG, MipsII::MO_GOT_CALL); 3526 } else 3527 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 0, 3528 MipsII::MO_NO_FLAG); 3529 GlobalOrExternal = true; 3530 } 3531 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 3532 if (!IsN64 && !IsPIC) // !N64 && static 3533 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 3534 MipsII::MO_NO_FLAG); 3535 else if (LargeGOT) 3536 Callee = getAddrGlobalLargeGOT(Callee, DAG, MipsII::MO_CALL_HI16, 3537 MipsII::MO_CALL_LO16); 3538 else // N64 || PIC 3539 Callee = getAddrGlobal(Callee, DAG, MipsII::MO_GOT_CALL); 3540 3541 GlobalOrExternal = true; 3542 } 3543 3544 SDValue JumpTarget = Callee; 3545 3546 // T9 should contain the address of the callee function if 3547 // -reloction-model=pic or it is an indirect call. 3548 if (IsPICCall || !GlobalOrExternal) { 3549 unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9; 3550 unsigned V0Reg = Mips::V0; 3551 if (needMips16Helper) { 3552 RegsToPass.push_front(std::make_pair(V0Reg, Callee)); 3553 JumpTarget = DAG.getExternalSymbol( 3554 mips16HelperFunction, getPointerTy()); 3555 JumpTarget = getAddrGlobal(JumpTarget, DAG, MipsII::MO_GOT); 3556 } 3557 else { 3558 RegsToPass.push_front(std::make_pair(T9Reg, Callee)); 3559 3560 if (!Subtarget->inMips16Mode()) 3561 JumpTarget = SDValue(); 3562 } 3563 } 3564 3565 // Insert node "GP copy globalreg" before call to function. 3566 // 3567 // R_MIPS_CALL* operators (emitted when non-internal functions are called 3568 // in PIC mode) allow symbols to be resolved via lazy binding. 3569 // The lazy binding stub requires GP to point to the GOT. 3570 if (IsPICCall && !InternalLinkage) { 3571 unsigned GPReg = IsN64 ? Mips::GP_64 : Mips::GP; 3572 EVT Ty = IsN64 ? MVT::i64 : MVT::i32; 3573 RegsToPass.push_back(std::make_pair(GPReg, GetGlobalReg(DAG, Ty))); 3574 } 3575 3576 // Build a sequence of copy-to-reg nodes chained together with token 3577 // chain and flag operands which copy the outgoing args into registers. 3578 // The InFlag in necessary since all emitted instructions must be 3579 // stuck together. 3580 SDValue InFlag; 3581 3582 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 3583 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 3584 RegsToPass[i].second, InFlag); 3585 InFlag = Chain.getValue(1); 3586 } 3587 3588 // MipsJmpLink = #chain, #target_address, #opt_in_flags... 3589 // = Chain, Callee, Reg#1, Reg#2, ... 3590 // 3591 // Returns a chain & a flag for retval copy to use. 3592 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 3593 SmallVector<SDValue, 8> Ops(1, Chain); 3594 3595 if (JumpTarget.getNode()) 3596 Ops.push_back(JumpTarget); 3597 3598 // Add argument registers to the end of the list so that they are 3599 // known live into the call. 3600 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 3601 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 3602 RegsToPass[i].second.getValueType())); 3603 3604 // Add a register mask operand representing the call-preserved registers. 3605 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 3606 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv); 3607 assert(Mask && "Missing call preserved mask for calling convention"); 3608 Ops.push_back(DAG.getRegisterMask(Mask)); 3609 3610 if (InFlag.getNode()) 3611 Ops.push_back(InFlag); 3612 3613 if (isTailCall) 3614 return DAG.getNode(MipsISD::TailCall, dl, MVT::Other, &Ops[0], Ops.size()); 3615 3616 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size()); 3617 InFlag = Chain.getValue(1); 3618 3619 // Create the CALLSEQ_END node. 3620 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal, 3621 DAG.getIntPtrConstant(0, true), InFlag); 3622 InFlag = Chain.getValue(1); 3623 3624 // Handle result values, copying them out of physregs into vregs that we 3625 // return. 3626 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 3627 Ins, dl, DAG, InVals, CLI.Callee.getNode(), CLI.RetTy); 3628} 3629 3630/// LowerCallResult - Lower the result values of a call into the 3631/// appropriate copies out of appropriate physical registers. 3632SDValue 3633MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 3634 CallingConv::ID CallConv, bool isVarArg, 3635 const SmallVectorImpl<ISD::InputArg> &Ins, 3636 DebugLoc dl, SelectionDAG &DAG, 3637 SmallVectorImpl<SDValue> &InVals, 3638 const SDNode *CallNode, 3639 const Type *RetTy) const { 3640 // Assign locations to each value returned by this call. 3641 SmallVector<CCValAssign, 16> RVLocs; 3642 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 3643 getTargetMachine(), RVLocs, *DAG.getContext()); 3644 MipsCC MipsCCInfo(CallConv, IsO32, CCInfo); 3645 3646 MipsCCInfo.analyzeCallResult(Ins, getTargetMachine().Options.UseSoftFloat, 3647 CallNode, RetTy); 3648 3649 // Copy all of the result registers out of their specified physreg. 3650 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3651 SDValue Val = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), 3652 RVLocs[i].getLocVT(), InFlag); 3653 Chain = Val.getValue(1); 3654 InFlag = Val.getValue(2); 3655 3656 if (RVLocs[i].getValVT() != RVLocs[i].getLocVT()) 3657 Val = DAG.getNode(ISD::BITCAST, dl, RVLocs[i].getValVT(), Val); 3658 3659 InVals.push_back(Val); 3660 } 3661 3662 return Chain; 3663} 3664 3665//===----------------------------------------------------------------------===// 3666// Formal Arguments Calling Convention Implementation 3667//===----------------------------------------------------------------------===// 3668/// LowerFormalArguments - transform physical registers into virtual registers 3669/// and generate load operations for arguments places on the stack. 3670SDValue 3671MipsTargetLowering::LowerFormalArguments(SDValue Chain, 3672 CallingConv::ID CallConv, 3673 bool isVarArg, 3674 const SmallVectorImpl<ISD::InputArg> &Ins, 3675 DebugLoc dl, SelectionDAG &DAG, 3676 SmallVectorImpl<SDValue> &InVals) 3677 const { 3678 MachineFunction &MF = DAG.getMachineFunction(); 3679 MachineFrameInfo *MFI = MF.getFrameInfo(); 3680 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3681 3682 MipsFI->setVarArgsFrameIndex(0); 3683 3684 // Used with vargs to acumulate store chains. 3685 std::vector<SDValue> OutChains; 3686 3687 // Assign locations to all of the incoming arguments. 3688 SmallVector<CCValAssign, 16> ArgLocs; 3689 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 3690 getTargetMachine(), ArgLocs, *DAG.getContext()); 3691 MipsCC MipsCCInfo(CallConv, IsO32, CCInfo); 3692 Function::const_arg_iterator FuncArg = 3693 DAG.getMachineFunction().getFunction()->arg_begin(); 3694 bool UseSoftFloat = getTargetMachine().Options.UseSoftFloat; 3695 3696 MipsCCInfo.analyzeFormalArguments(Ins, UseSoftFloat, FuncArg); 3697 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(), 3698 MipsCCInfo.hasByValArg()); 3699 3700 unsigned CurArgIdx = 0; 3701 MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin(); 3702 3703 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 3704 CCValAssign &VA = ArgLocs[i]; 3705 std::advance(FuncArg, Ins[i].OrigArgIndex - CurArgIdx); 3706 CurArgIdx = Ins[i].OrigArgIndex; 3707 EVT ValVT = VA.getValVT(); 3708 ISD::ArgFlagsTy Flags = Ins[i].Flags; 3709 bool IsRegLoc = VA.isRegLoc(); 3710 3711 if (Flags.isByVal()) { 3712 assert(Flags.getByValSize() && 3713 "ByVal args of size 0 should have been ignored by front-end."); 3714 assert(ByValArg != MipsCCInfo.byval_end()); 3715 copyByValRegs(Chain, dl, OutChains, DAG, Flags, InVals, &*FuncArg, 3716 MipsCCInfo, *ByValArg); 3717 ++ByValArg; 3718 continue; 3719 } 3720 3721 // Arguments stored on registers 3722 if (IsRegLoc) { 3723 EVT RegVT = VA.getLocVT(); 3724 unsigned ArgReg = VA.getLocReg(); 3725 const TargetRegisterClass *RC; 3726 3727 if (RegVT == MVT::i32) 3728 RC = Subtarget->inMips16Mode()? &Mips::CPU16RegsRegClass : 3729 &Mips::CPURegsRegClass; 3730 else if (RegVT == MVT::i64) 3731 RC = &Mips::CPU64RegsRegClass; 3732 else if (RegVT == MVT::f32) 3733 RC = &Mips::FGR32RegClass; 3734 else if (RegVT == MVT::f64) 3735 RC = HasMips64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; 3736 else 3737 llvm_unreachable("RegVT not supported by FormalArguments Lowering"); 3738 3739 // Transform the arguments stored on 3740 // physical registers into virtual ones 3741 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgReg, RC); 3742 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 3743 3744 // If this is an 8 or 16-bit value, it has been passed promoted 3745 // to 32 bits. Insert an assert[sz]ext to capture this, then 3746 // truncate to the right size. 3747 if (VA.getLocInfo() != CCValAssign::Full) { 3748 unsigned Opcode = 0; 3749 if (VA.getLocInfo() == CCValAssign::SExt) 3750 Opcode = ISD::AssertSext; 3751 else if (VA.getLocInfo() == CCValAssign::ZExt) 3752 Opcode = ISD::AssertZext; 3753 if (Opcode) 3754 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue, 3755 DAG.getValueType(ValVT)); 3756 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, ValVT, ArgValue); 3757 } 3758 3759 // Handle floating point arguments passed in integer registers and 3760 // long double arguments passed in floating point registers. 3761 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || 3762 (RegVT == MVT::i64 && ValVT == MVT::f64) || 3763 (RegVT == MVT::f64 && ValVT == MVT::i64)) 3764 ArgValue = DAG.getNode(ISD::BITCAST, dl, ValVT, ArgValue); 3765 else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) { 3766 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(), 3767 getNextIntArgReg(ArgReg), RC); 3768 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT); 3769 if (!Subtarget->isLittle()) 3770 std::swap(ArgValue, ArgValue2); 3771 ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64, 3772 ArgValue, ArgValue2); 3773 } 3774 3775 InVals.push_back(ArgValue); 3776 } else { // VA.isRegLoc() 3777 3778 // sanity check 3779 assert(VA.isMemLoc()); 3780 3781 // The stack pointer offset is relative to the caller stack frame. 3782 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 3783 VA.getLocMemOffset(), true); 3784 3785 // Create load nodes to retrieve arguments from the stack 3786 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 3787 InVals.push_back(DAG.getLoad(ValVT, dl, Chain, FIN, 3788 MachinePointerInfo::getFixedStack(FI), 3789 false, false, false, 0)); 3790 } 3791 } 3792 3793 // The mips ABIs for returning structs by value requires that we copy 3794 // the sret argument into $v0 for the return. Save the argument into 3795 // a virtual register so that we can access it from the return points. 3796 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 3797 unsigned Reg = MipsFI->getSRetReturnReg(); 3798 if (!Reg) { 3799 Reg = MF.getRegInfo(). 3800 createVirtualRegister(getRegClassFor(IsN64 ? MVT::i64 : MVT::i32)); 3801 MipsFI->setSRetReturnReg(Reg); 3802 } 3803 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 3804 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 3805 } 3806 3807 if (isVarArg) 3808 writeVarArgRegs(OutChains, MipsCCInfo, Chain, dl, DAG); 3809 3810 // All stores are grouped in one node to allow the matching between 3811 // the size of Ins and InVals. This only happens when on varg functions 3812 if (!OutChains.empty()) { 3813 OutChains.push_back(Chain); 3814 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3815 &OutChains[0], OutChains.size()); 3816 } 3817 3818 return Chain; 3819} 3820 3821//===----------------------------------------------------------------------===// 3822// Return Value Calling Convention Implementation 3823//===----------------------------------------------------------------------===// 3824 3825bool 3826MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv, 3827 MachineFunction &MF, bool isVarArg, 3828 const SmallVectorImpl<ISD::OutputArg> &Outs, 3829 LLVMContext &Context) const { 3830 SmallVector<CCValAssign, 16> RVLocs; 3831 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 3832 RVLocs, Context); 3833 return CCInfo.CheckReturn(Outs, RetCC_Mips); 3834} 3835 3836SDValue 3837MipsTargetLowering::LowerReturn(SDValue Chain, 3838 CallingConv::ID CallConv, bool isVarArg, 3839 const SmallVectorImpl<ISD::OutputArg> &Outs, 3840 const SmallVectorImpl<SDValue> &OutVals, 3841 DebugLoc dl, SelectionDAG &DAG) const { 3842 // CCValAssign - represent the assignment of 3843 // the return value to a location 3844 SmallVector<CCValAssign, 16> RVLocs; 3845 MachineFunction &MF = DAG.getMachineFunction(); 3846 3847 // CCState - Info about the registers and stack slot. 3848 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, 3849 *DAG.getContext()); 3850 MipsCC MipsCCInfo(CallConv, IsO32, CCInfo); 3851 3852 // Analize return values. 3853 MipsCCInfo.analyzeReturn(Outs, getTargetMachine().Options.UseSoftFloat, 3854 MF.getFunction()->getReturnType()); 3855 3856 SDValue Flag; 3857 SmallVector<SDValue, 4> RetOps(1, Chain); 3858 3859 // Copy the result values into the output registers. 3860 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3861 SDValue Val = OutVals[i]; 3862 CCValAssign &VA = RVLocs[i]; 3863 assert(VA.isRegLoc() && "Can only return in registers!"); 3864 3865 if (RVLocs[i].getValVT() != RVLocs[i].getLocVT()) 3866 Val = DAG.getNode(ISD::BITCAST, dl, RVLocs[i].getLocVT(), Val); 3867 3868 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Val, Flag); 3869 3870 // Guarantee that all emitted copies are stuck together with flags. 3871 Flag = Chain.getValue(1); 3872 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 3873 } 3874 3875 // The mips ABIs for returning structs by value requires that we copy 3876 // the sret argument into $v0 for the return. We saved the argument into 3877 // a virtual register in the entry block, so now we copy the value out 3878 // and into $v0. 3879 if (MF.getFunction()->hasStructRetAttr()) { 3880 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3881 unsigned Reg = MipsFI->getSRetReturnReg(); 3882 3883 if (!Reg) 3884 llvm_unreachable("sret virtual register not created in the entry block"); 3885 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 3886 unsigned V0 = IsN64 ? Mips::V0_64 : Mips::V0; 3887 3888 Chain = DAG.getCopyToReg(Chain, dl, V0, Val, Flag); 3889 Flag = Chain.getValue(1); 3890 RetOps.push_back(DAG.getRegister(V0, getPointerTy())); 3891 } 3892 3893 RetOps[0] = Chain; // Update chain. 3894 3895 // Add the flag if we have it. 3896 if (Flag.getNode()) 3897 RetOps.push_back(Flag); 3898 3899 // Return on Mips is always a "jr $ra" 3900 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, &RetOps[0], RetOps.size()); 3901} 3902 3903//===----------------------------------------------------------------------===// 3904// Mips Inline Assembly Support 3905//===----------------------------------------------------------------------===// 3906 3907/// getConstraintType - Given a constraint letter, return the type of 3908/// constraint it is for this target. 3909MipsTargetLowering::ConstraintType MipsTargetLowering:: 3910getConstraintType(const std::string &Constraint) const 3911{ 3912 // Mips specific constrainy 3913 // GCC config/mips/constraints.md 3914 // 3915 // 'd' : An address register. Equivalent to r 3916 // unless generating MIPS16 code. 3917 // 'y' : Equivalent to r; retained for 3918 // backwards compatibility. 3919 // 'c' : A register suitable for use in an indirect 3920 // jump. This will always be $25 for -mabicalls. 3921 // 'l' : The lo register. 1 word storage. 3922 // 'x' : The hilo register pair. Double word storage. 3923 if (Constraint.size() == 1) { 3924 switch (Constraint[0]) { 3925 default : break; 3926 case 'd': 3927 case 'y': 3928 case 'f': 3929 case 'c': 3930 case 'l': 3931 case 'x': 3932 return C_RegisterClass; 3933 case 'R': 3934 return C_Memory; 3935 } 3936 } 3937 return TargetLowering::getConstraintType(Constraint); 3938} 3939 3940/// Examine constraint type and operand type and determine a weight value. 3941/// This object must already have been set up with the operand type 3942/// and the current alternative constraint selected. 3943TargetLowering::ConstraintWeight 3944MipsTargetLowering::getSingleConstraintMatchWeight( 3945 AsmOperandInfo &info, const char *constraint) const { 3946 ConstraintWeight weight = CW_Invalid; 3947 Value *CallOperandVal = info.CallOperandVal; 3948 // If we don't have a value, we can't do a match, 3949 // but allow it at the lowest weight. 3950 if (CallOperandVal == NULL) 3951 return CW_Default; 3952 Type *type = CallOperandVal->getType(); 3953 // Look at the constraint type. 3954 switch (*constraint) { 3955 default: 3956 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 3957 break; 3958 case 'd': 3959 case 'y': 3960 if (type->isIntegerTy()) 3961 weight = CW_Register; 3962 break; 3963 case 'f': 3964 if (type->isFloatTy()) 3965 weight = CW_Register; 3966 break; 3967 case 'c': // $25 for indirect jumps 3968 case 'l': // lo register 3969 case 'x': // hilo register pair 3970 if (type->isIntegerTy()) 3971 weight = CW_SpecificReg; 3972 break; 3973 case 'I': // signed 16 bit immediate 3974 case 'J': // integer zero 3975 case 'K': // unsigned 16 bit immediate 3976 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3977 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3978 case 'O': // signed 15 bit immediate (+- 16383) 3979 case 'P': // immediate in the range of 65535 to 1 (inclusive) 3980 if (isa<ConstantInt>(CallOperandVal)) 3981 weight = CW_Constant; 3982 break; 3983 case 'R': 3984 weight = CW_Memory; 3985 break; 3986 } 3987 return weight; 3988} 3989 3990/// Given a register class constraint, like 'r', if this corresponds directly 3991/// to an LLVM register class, return a register of 0 and the register class 3992/// pointer. 3993std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering:: 3994getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const 3995{ 3996 if (Constraint.size() == 1) { 3997 switch (Constraint[0]) { 3998 case 'd': // Address register. Same as 'r' unless generating MIPS16 code. 3999 case 'y': // Same as 'r'. Exists for compatibility. 4000 case 'r': 4001 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { 4002 if (Subtarget->inMips16Mode()) 4003 return std::make_pair(0U, &Mips::CPU16RegsRegClass); 4004 return std::make_pair(0U, &Mips::CPURegsRegClass); 4005 } 4006 if (VT == MVT::i64 && !HasMips64) 4007 return std::make_pair(0U, &Mips::CPURegsRegClass); 4008 if (VT == MVT::i64 && HasMips64) 4009 return std::make_pair(0U, &Mips::CPU64RegsRegClass); 4010 // This will generate an error message 4011 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 4012 case 'f': 4013 if (VT == MVT::f32) 4014 return std::make_pair(0U, &Mips::FGR32RegClass); 4015 if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) { 4016 if (Subtarget->isFP64bit()) 4017 return std::make_pair(0U, &Mips::FGR64RegClass); 4018 return std::make_pair(0U, &Mips::AFGR64RegClass); 4019 } 4020 break; 4021 case 'c': // register suitable for indirect jump 4022 if (VT == MVT::i32) 4023 return std::make_pair((unsigned)Mips::T9, &Mips::CPURegsRegClass); 4024 assert(VT == MVT::i64 && "Unexpected type."); 4025 return std::make_pair((unsigned)Mips::T9_64, &Mips::CPU64RegsRegClass); 4026 case 'l': // register suitable for indirect jump 4027 if (VT == MVT::i32) 4028 return std::make_pair((unsigned)Mips::LO, &Mips::HILORegClass); 4029 return std::make_pair((unsigned)Mips::LO64, &Mips::HILO64RegClass); 4030 case 'x': // register suitable for indirect jump 4031 // Fixme: Not triggering the use of both hi and low 4032 // This will generate an error message 4033 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 4034 } 4035 } 4036 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 4037} 4038 4039/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 4040/// vector. If it is invalid, don't add anything to Ops. 4041void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 4042 std::string &Constraint, 4043 std::vector<SDValue>&Ops, 4044 SelectionDAG &DAG) const { 4045 SDValue Result(0, 0); 4046 4047 // Only support length 1 constraints for now. 4048 if (Constraint.length() > 1) return; 4049 4050 char ConstraintLetter = Constraint[0]; 4051 switch (ConstraintLetter) { 4052 default: break; // This will fall through to the generic implementation 4053 case 'I': // Signed 16 bit constant 4054 // If this fails, the parent routine will give an error 4055 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 4056 EVT Type = Op.getValueType(); 4057 int64_t Val = C->getSExtValue(); 4058 if (isInt<16>(Val)) { 4059 Result = DAG.getTargetConstant(Val, Type); 4060 break; 4061 } 4062 } 4063 return; 4064 case 'J': // integer zero 4065 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 4066 EVT Type = Op.getValueType(); 4067 int64_t Val = C->getZExtValue(); 4068 if (Val == 0) { 4069 Result = DAG.getTargetConstant(0, Type); 4070 break; 4071 } 4072 } 4073 return; 4074 case 'K': // unsigned 16 bit immediate 4075 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 4076 EVT Type = Op.getValueType(); 4077 uint64_t Val = (uint64_t)C->getZExtValue(); 4078 if (isUInt<16>(Val)) { 4079 Result = DAG.getTargetConstant(Val, Type); 4080 break; 4081 } 4082 } 4083 return; 4084 case 'L': // signed 32 bit immediate where lower 16 bits are 0 4085 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 4086 EVT Type = Op.getValueType(); 4087 int64_t Val = C->getSExtValue(); 4088 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){ 4089 Result = DAG.getTargetConstant(Val, Type); 4090 break; 4091 } 4092 } 4093 return; 4094 case 'N': // immediate in the range of -65535 to -1 (inclusive) 4095 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 4096 EVT Type = Op.getValueType(); 4097 int64_t Val = C->getSExtValue(); 4098 if ((Val >= -65535) && (Val <= -1)) { 4099 Result = DAG.getTargetConstant(Val, Type); 4100 break; 4101 } 4102 } 4103 return; 4104 case 'O': // signed 15 bit immediate 4105 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 4106 EVT Type = Op.getValueType(); 4107 int64_t Val = C->getSExtValue(); 4108 if ((isInt<15>(Val))) { 4109 Result = DAG.getTargetConstant(Val, Type); 4110 break; 4111 } 4112 } 4113 return; 4114 case 'P': // immediate in the range of 1 to 65535 (inclusive) 4115 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 4116 EVT Type = Op.getValueType(); 4117 int64_t Val = C->getSExtValue(); 4118 if ((Val <= 65535) && (Val >= 1)) { 4119 Result = DAG.getTargetConstant(Val, Type); 4120 break; 4121 } 4122 } 4123 return; 4124 } 4125 4126 if (Result.getNode()) { 4127 Ops.push_back(Result); 4128 return; 4129 } 4130 4131 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 4132} 4133 4134bool 4135MipsTargetLowering::isLegalAddressingMode(const AddrMode &AM, Type *Ty) const { 4136 // No global is ever allowed as a base. 4137 if (AM.BaseGV) 4138 return false; 4139 4140 switch (AM.Scale) { 4141 case 0: // "r+i" or just "i", depending on HasBaseReg. 4142 break; 4143 case 1: 4144 if (!AM.HasBaseReg) // allow "r+i". 4145 break; 4146 return false; // disallow "r+r" or "r+r+i". 4147 default: 4148 return false; 4149 } 4150 4151 return true; 4152} 4153 4154bool 4155MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 4156 // The Mips target isn't yet aware of offsets. 4157 return false; 4158} 4159 4160EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 4161 unsigned SrcAlign, 4162 bool IsMemset, bool ZeroMemset, 4163 bool MemcpyStrSrc, 4164 MachineFunction &MF) const { 4165 if (Subtarget->hasMips64()) 4166 return MVT::i64; 4167 4168 return MVT::i32; 4169} 4170 4171bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 4172 if (VT != MVT::f32 && VT != MVT::f64) 4173 return false; 4174 if (Imm.isNegZero()) 4175 return false; 4176 return Imm.isZero(); 4177} 4178 4179unsigned MipsTargetLowering::getJumpTableEncoding() const { 4180 if (IsN64) 4181 return MachineJumpTableInfo::EK_GPRel64BlockAddress; 4182 4183 return TargetLowering::getJumpTableEncoding(); 4184} 4185 4186/// This function returns true if CallSym is a long double emulation routine. 4187static bool isF128SoftLibCall(const char *CallSym) { 4188 const char *const LibCalls[] = 4189 {"__addtf3", "__divtf3", "__eqtf2", "__extenddftf2", "__extendsftf2", 4190 "__fixtfdi", "__fixtfsi", "__fixtfti", "__fixunstfdi", "__fixunstfsi", 4191 "__fixunstfti", "__floatditf", "__floatsitf", "__floattitf", 4192 "__floatunditf", "__floatunsitf", "__floatuntitf", "__getf2", "__gttf2", 4193 "__letf2", "__lttf2", "__multf3", "__netf2", "__powitf2", "__subtf3", 4194 "__trunctfdf2", "__trunctfsf2", "__unordtf2", 4195 "ceill", "copysignl", "cosl", "exp2l", "expl", "floorl", "fmal", "fmodl", 4196 "log10l", "log2l", "logl", "nearbyintl", "powl", "rintl", "sinl", "sqrtl", 4197 "truncl"}; 4198 4199 const char * const *End = LibCalls + array_lengthof(LibCalls); 4200 4201 // Check that LibCalls is sorted alphabetically. 4202#ifndef NDEBUG 4203 ltstr Comp; 4204 4205 for (const char * const *I = LibCalls; I < End - 1; ++I) 4206 assert(Comp(*I, *(I + 1))); 4207#endif 4208 4209 return std::binary_search(LibCalls, End, CallSym, ltstr()); 4210} 4211 4212/// This function returns true if Ty is fp128 or i128 which was originally a 4213/// fp128. 4214static bool originalTypeIsF128(const Type *Ty, const SDNode *CallNode) { 4215 if (Ty->isFP128Ty()) 4216 return true; 4217 4218 const ExternalSymbolSDNode *ES = 4219 dyn_cast_or_null<const ExternalSymbolSDNode>(CallNode); 4220 4221 // If the Ty is i128 and the function being called is a long double emulation 4222 // routine, then the original type is f128. 4223 return (ES && Ty->isIntegerTy(128) && isF128SoftLibCall(ES->getSymbol())); 4224} 4225 4226MipsTargetLowering::MipsCC::MipsCC(CallingConv::ID CC, bool IsO32_, 4227 CCState &Info) 4228 : CCInfo(Info), CallConv(CC), IsO32(IsO32_) { 4229 // Pre-allocate reserved argument area. 4230 CCInfo.AllocateStack(reservedArgArea(), 1); 4231} 4232 4233void MipsTargetLowering::MipsCC:: 4234analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Args, 4235 bool IsVarArg, bool IsSoftFloat, const SDNode *CallNode, 4236 std::vector<ArgListEntry> &FuncArgs) { 4237 assert((CallConv != CallingConv::Fast || !IsVarArg) && 4238 "CallingConv::Fast shouldn't be used for vararg functions."); 4239 4240 unsigned NumOpnds = Args.size(); 4241 llvm::CCAssignFn *FixedFn = fixedArgFn(), *VarFn = varArgFn(); 4242 4243 for (unsigned I = 0; I != NumOpnds; ++I) { 4244 MVT ArgVT = Args[I].VT; 4245 ISD::ArgFlagsTy ArgFlags = Args[I].Flags; 4246 bool R; 4247 4248 if (ArgFlags.isByVal()) { 4249 handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags); 4250 continue; 4251 } 4252 4253 if (IsVarArg && !Args[I].IsFixed) 4254 R = VarFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo); 4255 else { 4256 MVT RegVT = getRegVT(ArgVT, FuncArgs[Args[I].OrigArgIndex].Ty, CallNode, 4257 IsSoftFloat); 4258 R = FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, CCInfo); 4259 } 4260 4261 if (R) { 4262#ifndef NDEBUG 4263 dbgs() << "Call operand #" << I << " has unhandled type " 4264 << EVT(ArgVT).getEVTString(); 4265#endif 4266 llvm_unreachable(0); 4267 } 4268 } 4269} 4270 4271void MipsTargetLowering::MipsCC:: 4272analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Args, 4273 bool IsSoftFloat, Function::const_arg_iterator FuncArg) { 4274 unsigned NumArgs = Args.size(); 4275 llvm::CCAssignFn *FixedFn = fixedArgFn(); 4276 unsigned CurArgIdx = 0; 4277 4278 for (unsigned I = 0; I != NumArgs; ++I) { 4279 MVT ArgVT = Args[I].VT; 4280 ISD::ArgFlagsTy ArgFlags = Args[I].Flags; 4281 std::advance(FuncArg, Args[I].OrigArgIndex - CurArgIdx); 4282 CurArgIdx = Args[I].OrigArgIndex; 4283 4284 if (ArgFlags.isByVal()) { 4285 handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags); 4286 continue; 4287 } 4288 4289 MVT RegVT = getRegVT(ArgVT, FuncArg->getType(), 0, IsSoftFloat); 4290 4291 if (!FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, CCInfo)) 4292 continue; 4293 4294#ifndef NDEBUG 4295 dbgs() << "Formal Arg #" << I << " has unhandled type " 4296 << EVT(ArgVT).getEVTString(); 4297#endif 4298 llvm_unreachable(0); 4299 } 4300} 4301 4302template<typename Ty> 4303void MipsTargetLowering::MipsCC:: 4304analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat, 4305 const SDNode *CallNode, const Type *RetTy) const { 4306 CCAssignFn *Fn; 4307 4308 if (IsSoftFloat && originalTypeIsF128(RetTy, CallNode)) 4309 Fn = RetCC_F128Soft; 4310 else 4311 Fn = RetCC_Mips; 4312 4313 for (unsigned I = 0, E = RetVals.size(); I < E; ++I) { 4314 MVT VT = RetVals[I].VT; 4315 ISD::ArgFlagsTy Flags = RetVals[I].Flags; 4316 MVT RegVT = this->getRegVT(VT, RetTy, CallNode, IsSoftFloat); 4317 4318 if (Fn(I, VT, RegVT, CCValAssign::Full, Flags, this->CCInfo)) { 4319#ifndef NDEBUG 4320 dbgs() << "Call result #" << I << " has unhandled type " 4321 << EVT(VT).getEVTString() << '\n'; 4322#endif 4323 llvm_unreachable(0); 4324 } 4325 } 4326} 4327 4328void MipsTargetLowering::MipsCC:: 4329analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, bool IsSoftFloat, 4330 const SDNode *CallNode, const Type *RetTy) const { 4331 analyzeReturn(Ins, IsSoftFloat, CallNode, RetTy); 4332} 4333 4334void MipsTargetLowering::MipsCC:: 4335analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsSoftFloat, 4336 const Type *RetTy) const { 4337 analyzeReturn(Outs, IsSoftFloat, 0, RetTy); 4338} 4339 4340void 4341MipsTargetLowering::MipsCC::handleByValArg(unsigned ValNo, MVT ValVT, 4342 MVT LocVT, 4343 CCValAssign::LocInfo LocInfo, 4344 ISD::ArgFlagsTy ArgFlags) { 4345 assert(ArgFlags.getByValSize() && "Byval argument's size shouldn't be 0."); 4346 4347 struct ByValArgInfo ByVal; 4348 unsigned RegSize = regSize(); 4349 unsigned ByValSize = RoundUpToAlignment(ArgFlags.getByValSize(), RegSize); 4350 unsigned Align = std::min(std::max(ArgFlags.getByValAlign(), RegSize), 4351 RegSize * 2); 4352 4353 if (useRegsForByval()) 4354 allocateRegs(ByVal, ByValSize, Align); 4355 4356 // Allocate space on caller's stack. 4357 ByVal.Address = CCInfo.AllocateStack(ByValSize - RegSize * ByVal.NumRegs, 4358 Align); 4359 CCInfo.addLoc(CCValAssign::getMem(ValNo, ValVT, ByVal.Address, LocVT, 4360 LocInfo)); 4361 ByValArgs.push_back(ByVal); 4362} 4363 4364unsigned MipsTargetLowering::MipsCC::numIntArgRegs() const { 4365 return IsO32 ? array_lengthof(O32IntRegs) : array_lengthof(Mips64IntRegs); 4366} 4367 4368unsigned MipsTargetLowering::MipsCC::reservedArgArea() const { 4369 return (IsO32 && (CallConv != CallingConv::Fast)) ? 16 : 0; 4370} 4371 4372const uint16_t *MipsTargetLowering::MipsCC::intArgRegs() const { 4373 return IsO32 ? O32IntRegs : Mips64IntRegs; 4374} 4375 4376llvm::CCAssignFn *MipsTargetLowering::MipsCC::fixedArgFn() const { 4377 if (CallConv == CallingConv::Fast) 4378 return CC_Mips_FastCC; 4379 4380 return IsO32 ? CC_MipsO32 : CC_MipsN; 4381} 4382 4383llvm::CCAssignFn *MipsTargetLowering::MipsCC::varArgFn() const { 4384 return IsO32 ? CC_MipsO32 : CC_MipsN_VarArg; 4385} 4386 4387const uint16_t *MipsTargetLowering::MipsCC::shadowRegs() const { 4388 return IsO32 ? O32IntRegs : Mips64DPRegs; 4389} 4390 4391void MipsTargetLowering::MipsCC::allocateRegs(ByValArgInfo &ByVal, 4392 unsigned ByValSize, 4393 unsigned Align) { 4394 unsigned RegSize = regSize(), NumIntArgRegs = numIntArgRegs(); 4395 const uint16_t *IntArgRegs = intArgRegs(), *ShadowRegs = shadowRegs(); 4396 assert(!(ByValSize % RegSize) && !(Align % RegSize) && 4397 "Byval argument's size and alignment should be a multiple of" 4398 "RegSize."); 4399 4400 ByVal.FirstIdx = CCInfo.getFirstUnallocated(IntArgRegs, NumIntArgRegs); 4401 4402 // If Align > RegSize, the first arg register must be even. 4403 if ((Align > RegSize) && (ByVal.FirstIdx % 2)) { 4404 CCInfo.AllocateReg(IntArgRegs[ByVal.FirstIdx], ShadowRegs[ByVal.FirstIdx]); 4405 ++ByVal.FirstIdx; 4406 } 4407 4408 // Mark the registers allocated. 4409 for (unsigned I = ByVal.FirstIdx; ByValSize && (I < NumIntArgRegs); 4410 ByValSize -= RegSize, ++I, ++ByVal.NumRegs) 4411 CCInfo.AllocateReg(IntArgRegs[I], ShadowRegs[I]); 4412} 4413 4414MVT MipsTargetLowering::MipsCC::getRegVT(MVT VT, const Type *OrigTy, 4415 const SDNode *CallNode, 4416 bool IsSoftFloat) const { 4417 if (IsSoftFloat || IsO32) 4418 return VT; 4419 4420 // Check if the original type was fp128. 4421 if (originalTypeIsF128(OrigTy, CallNode)) { 4422 assert(VT == MVT::i64); 4423 return MVT::f64; 4424 } 4425 4426 return VT; 4427} 4428 4429void MipsTargetLowering:: 4430copyByValRegs(SDValue Chain, DebugLoc DL, std::vector<SDValue> &OutChains, 4431 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags, 4432 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg, 4433 const MipsCC &CC, const ByValArgInfo &ByVal) const { 4434 MachineFunction &MF = DAG.getMachineFunction(); 4435 MachineFrameInfo *MFI = MF.getFrameInfo(); 4436 unsigned RegAreaSize = ByVal.NumRegs * CC.regSize(); 4437 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize); 4438 int FrameObjOffset; 4439 4440 if (RegAreaSize) 4441 FrameObjOffset = (int)CC.reservedArgArea() - 4442 (int)((CC.numIntArgRegs() - ByVal.FirstIdx) * CC.regSize()); 4443 else 4444 FrameObjOffset = ByVal.Address; 4445 4446 // Create frame object. 4447 EVT PtrTy = getPointerTy(); 4448 int FI = MFI->CreateFixedObject(FrameObjSize, FrameObjOffset, true); 4449 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 4450 InVals.push_back(FIN); 4451 4452 if (!ByVal.NumRegs) 4453 return; 4454 4455 // Copy arg registers. 4456 MVT RegTy = MVT::getIntegerVT(CC.regSize() * 8); 4457 const TargetRegisterClass *RC = getRegClassFor(RegTy); 4458 4459 for (unsigned I = 0; I < ByVal.NumRegs; ++I) { 4460 unsigned ArgReg = CC.intArgRegs()[ByVal.FirstIdx + I]; 4461 unsigned VReg = AddLiveIn(MF, ArgReg, RC); 4462 unsigned Offset = I * CC.regSize(); 4463 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN, 4464 DAG.getConstant(Offset, PtrTy)); 4465 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy), 4466 StorePtr, MachinePointerInfo(FuncArg, Offset), 4467 false, false, 0); 4468 OutChains.push_back(Store); 4469 } 4470} 4471 4472// Copy byVal arg to registers and stack. 4473void MipsTargetLowering:: 4474passByValArg(SDValue Chain, DebugLoc DL, 4475 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 4476 SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr, 4477 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, 4478 const MipsCC &CC, const ByValArgInfo &ByVal, 4479 const ISD::ArgFlagsTy &Flags, bool isLittle) const { 4480 unsigned ByValSize = Flags.getByValSize(); 4481 unsigned Offset = 0; // Offset in # of bytes from the beginning of struct. 4482 unsigned RegSize = CC.regSize(); 4483 unsigned Alignment = std::min(Flags.getByValAlign(), RegSize); 4484 EVT PtrTy = getPointerTy(), RegTy = MVT::getIntegerVT(RegSize * 8); 4485 4486 if (ByVal.NumRegs) { 4487 const uint16_t *ArgRegs = CC.intArgRegs(); 4488 bool LeftoverBytes = (ByVal.NumRegs * RegSize > ByValSize); 4489 unsigned I = 0; 4490 4491 // Copy words to registers. 4492 for (; I < ByVal.NumRegs - LeftoverBytes; ++I, Offset += RegSize) { 4493 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 4494 DAG.getConstant(Offset, PtrTy)); 4495 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr, 4496 MachinePointerInfo(), false, false, false, 4497 Alignment); 4498 MemOpChains.push_back(LoadVal.getValue(1)); 4499 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I]; 4500 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal)); 4501 } 4502 4503 // Return if the struct has been fully copied. 4504 if (ByValSize == Offset) 4505 return; 4506 4507 // Copy the remainder of the byval argument with sub-word loads and shifts. 4508 if (LeftoverBytes) { 4509 assert((ByValSize > Offset) && (ByValSize < Offset + RegSize) && 4510 "Size of the remainder should be smaller than RegSize."); 4511 SDValue Val; 4512 4513 for (unsigned LoadSize = RegSize / 2, TotalSizeLoaded = 0; 4514 Offset < ByValSize; LoadSize /= 2) { 4515 unsigned RemSize = ByValSize - Offset; 4516 4517 if (RemSize < LoadSize) 4518 continue; 4519 4520 // Load subword. 4521 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 4522 DAG.getConstant(Offset, PtrTy)); 4523 SDValue LoadVal = 4524 DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, 4525 MachinePointerInfo(), MVT::getIntegerVT(LoadSize * 8), 4526 false, false, Alignment); 4527 MemOpChains.push_back(LoadVal.getValue(1)); 4528 4529 // Shift the loaded value. 4530 unsigned Shamt; 4531 4532 if (isLittle) 4533 Shamt = TotalSizeLoaded; 4534 else 4535 Shamt = (RegSize - (TotalSizeLoaded + LoadSize)) * 8; 4536 4537 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal, 4538 DAG.getConstant(Shamt, MVT::i32)); 4539 4540 if (Val.getNode()) 4541 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift); 4542 else 4543 Val = Shift; 4544 4545 Offset += LoadSize; 4546 TotalSizeLoaded += LoadSize; 4547 Alignment = std::min(Alignment, LoadSize); 4548 } 4549 4550 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I]; 4551 RegsToPass.push_back(std::make_pair(ArgReg, Val)); 4552 return; 4553 } 4554 } 4555 4556 // Copy remainder of byval arg to it with memcpy. 4557 unsigned MemCpySize = ByValSize - Offset; 4558 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 4559 DAG.getConstant(Offset, PtrTy)); 4560 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr, 4561 DAG.getIntPtrConstant(ByVal.Address)); 4562 Chain = DAG.getMemcpy(Chain, DL, Dst, Src, 4563 DAG.getConstant(MemCpySize, PtrTy), Alignment, 4564 /*isVolatile=*/false, /*AlwaysInline=*/false, 4565 MachinePointerInfo(0), MachinePointerInfo(0)); 4566 MemOpChains.push_back(Chain); 4567} 4568 4569void 4570MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains, 4571 const MipsCC &CC, SDValue Chain, 4572 DebugLoc DL, SelectionDAG &DAG) const { 4573 unsigned NumRegs = CC.numIntArgRegs(); 4574 const uint16_t *ArgRegs = CC.intArgRegs(); 4575 const CCState &CCInfo = CC.getCCInfo(); 4576 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumRegs); 4577 unsigned RegSize = CC.regSize(); 4578 MVT RegTy = MVT::getIntegerVT(RegSize * 8); 4579 const TargetRegisterClass *RC = getRegClassFor(RegTy); 4580 MachineFunction &MF = DAG.getMachineFunction(); 4581 MachineFrameInfo *MFI = MF.getFrameInfo(); 4582 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 4583 4584 // Offset of the first variable argument from stack pointer. 4585 int VaArgOffset; 4586 4587 if (NumRegs == Idx) 4588 VaArgOffset = RoundUpToAlignment(CCInfo.getNextStackOffset(), RegSize); 4589 else 4590 VaArgOffset = 4591 (int)CC.reservedArgArea() - (int)(RegSize * (NumRegs - Idx)); 4592 4593 // Record the frame index of the first variable argument 4594 // which is a value necessary to VASTART. 4595 int FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true); 4596 MipsFI->setVarArgsFrameIndex(FI); 4597 4598 // Copy the integer registers that have not been used for argument passing 4599 // to the argument register save area. For O32, the save area is allocated 4600 // in the caller's stack frame, while for N32/64, it is allocated in the 4601 // callee's stack frame. 4602 for (unsigned I = Idx; I < NumRegs; ++I, VaArgOffset += RegSize) { 4603 unsigned Reg = AddLiveIn(MF, ArgRegs[I], RC); 4604 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy); 4605 FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true); 4606 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy()); 4607 SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff, 4608 MachinePointerInfo(), false, false, 0); 4609 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(0); 4610 OutChains.push_back(Store); 4611 } 4612} 4613