MipsISelLowering.cpp revision f934d159ae6b57f05d8163265b9deaa29315d2e7
1//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that Mips uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "mips-lower" 16#include "MipsISelLowering.h" 17#include "MipsMachineFunction.h" 18#include "MipsTargetMachine.h" 19#include "MipsTargetObjectFile.h" 20#include "MipsSubtarget.h" 21#include "InstPrinter/MipsInstPrinter.h" 22#include "MCTargetDesc/MipsBaseInfo.h" 23#include "llvm/DerivedTypes.h" 24#include "llvm/Function.h" 25#include "llvm/GlobalVariable.h" 26#include "llvm/Intrinsics.h" 27#include "llvm/CallingConv.h" 28#include "llvm/CodeGen/CallingConvLower.h" 29#include "llvm/CodeGen/MachineFrameInfo.h" 30#include "llvm/CodeGen/MachineFunction.h" 31#include "llvm/CodeGen/MachineInstrBuilder.h" 32#include "llvm/CodeGen/MachineRegisterInfo.h" 33#include "llvm/CodeGen/SelectionDAGISel.h" 34#include "llvm/CodeGen/ValueTypes.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/Support/raw_ostream.h" 38 39using namespace llvm; 40 41// If I is a shifted mask, set the size (Size) and the first bit of the 42// mask (Pos), and return true. 43// For example, if I is 0x003ff800, (Pos, Size) = (11, 11). 44static bool IsShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { 45 if (!isShiftedMask_64(I)) 46 return false; 47 48 Size = CountPopulation_64(I); 49 Pos = CountTrailingZeros_64(I); 50 return true; 51} 52 53static SDValue GetGlobalReg(SelectionDAG &DAG, EVT Ty) { 54 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>(); 55 return DAG.getRegister(FI->getGlobalBaseReg(), Ty); 56} 57 58const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 59 switch (Opcode) { 60 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 61 case MipsISD::Hi: return "MipsISD::Hi"; 62 case MipsISD::Lo: return "MipsISD::Lo"; 63 case MipsISD::GPRel: return "MipsISD::GPRel"; 64 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; 65 case MipsISD::Ret: return "MipsISD::Ret"; 66 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 67 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 68 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 69 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 70 case MipsISD::FPRound: return "MipsISD::FPRound"; 71 case MipsISD::MAdd: return "MipsISD::MAdd"; 72 case MipsISD::MAddu: return "MipsISD::MAddu"; 73 case MipsISD::MSub: return "MipsISD::MSub"; 74 case MipsISD::MSubu: return "MipsISD::MSubu"; 75 case MipsISD::DivRem: return "MipsISD::DivRem"; 76 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 77 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 78 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 79 case MipsISD::Wrapper: return "MipsISD::Wrapper"; 80 case MipsISD::DynAlloc: return "MipsISD::DynAlloc"; 81 case MipsISD::Sync: return "MipsISD::Sync"; 82 case MipsISD::Ext: return "MipsISD::Ext"; 83 case MipsISD::Ins: return "MipsISD::Ins"; 84 case MipsISD::LWL: return "MipsISD::LWL"; 85 case MipsISD::LWR: return "MipsISD::LWR"; 86 case MipsISD::SWL: return "MipsISD::SWL"; 87 case MipsISD::SWR: return "MipsISD::SWR"; 88 case MipsISD::LDL: return "MipsISD::LDL"; 89 case MipsISD::LDR: return "MipsISD::LDR"; 90 case MipsISD::SDL: return "MipsISD::SDL"; 91 case MipsISD::SDR: return "MipsISD::SDR"; 92 default: return NULL; 93 } 94} 95 96MipsTargetLowering:: 97MipsTargetLowering(MipsTargetMachine &TM) 98 : TargetLowering(TM, new MipsTargetObjectFile()), 99 Subtarget(&TM.getSubtarget<MipsSubtarget>()), 100 HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()), 101 IsO32(Subtarget->isABI_O32()) { 102 103 // Mips does not have i1 type, so use i32 for 104 // setcc operations results (slt, sgt, ...). 105 setBooleanContents(ZeroOrOneBooleanContent); 106 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct? 107 108 // Set up the register classes 109 addRegisterClass(MVT::i32, &Mips::CPURegsRegClass); 110 111 if (HasMips64) 112 addRegisterClass(MVT::i64, &Mips::CPU64RegsRegClass); 113 114 if (Subtarget->inMips16Mode()) { 115 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass); 116 } 117 118 if (!TM.Options.UseSoftFloat) { 119 addRegisterClass(MVT::f32, &Mips::FGR32RegClass); 120 121 // When dealing with single precision only, use libcalls 122 if (!Subtarget->isSingleFloat()) { 123 if (HasMips64) 124 addRegisterClass(MVT::f64, &Mips::FGR64RegClass); 125 else 126 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass); 127 } 128 } 129 130 // Load extented operations for i1 types must be promoted 131 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 132 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 133 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 134 135 // MIPS doesn't have extending float->double load/store 136 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 137 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 138 139 // Used by legalize types to correctly generate the setcc result. 140 // Without this, every float setcc comes with a AND/OR with the result, 141 // we don't want this, since the fpcmp result goes to a flag register, 142 // which is used implicitly by brcond and select operations. 143 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 144 145 // Mips Custom Operations 146 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 147 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 148 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 149 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 150 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 151 setOperationAction(ISD::SELECT, MVT::f32, Custom); 152 setOperationAction(ISD::SELECT, MVT::f64, Custom); 153 setOperationAction(ISD::SELECT, MVT::i32, Custom); 154 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 155 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 156 setOperationAction(ISD::SETCC, MVT::f32, Custom); 157 setOperationAction(ISD::SETCC, MVT::f64, Custom); 158 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 159 setOperationAction(ISD::VASTART, MVT::Other, Custom); 160 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 161 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 162 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom); 163 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); 164 if (!Subtarget->inMips16Mode()) { 165 setOperationAction(ISD::LOAD, MVT::i32, Custom); 166 setOperationAction(ISD::STORE, MVT::i32, Custom); 167 } 168 169 if (!TM.Options.NoNaNsFPMath) { 170 setOperationAction(ISD::FABS, MVT::f32, Custom); 171 setOperationAction(ISD::FABS, MVT::f64, Custom); 172 } 173 174 if (HasMips64) { 175 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 176 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 177 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 178 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 179 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 180 setOperationAction(ISD::SELECT, MVT::i64, Custom); 181 setOperationAction(ISD::LOAD, MVT::i64, Custom); 182 setOperationAction(ISD::STORE, MVT::i64, Custom); 183 } 184 185 if (!HasMips64) { 186 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 187 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 188 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 189 } 190 191 setOperationAction(ISD::SDIV, MVT::i32, Expand); 192 setOperationAction(ISD::SREM, MVT::i32, Expand); 193 setOperationAction(ISD::UDIV, MVT::i32, Expand); 194 setOperationAction(ISD::UREM, MVT::i32, Expand); 195 setOperationAction(ISD::SDIV, MVT::i64, Expand); 196 setOperationAction(ISD::SREM, MVT::i64, Expand); 197 setOperationAction(ISD::UDIV, MVT::i64, Expand); 198 setOperationAction(ISD::UREM, MVT::i64, Expand); 199 200 // Operations not directly supported by Mips. 201 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 202 setOperationAction(ISD::BR_CC, MVT::Other, Expand); 203 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 204 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 205 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 206 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 207 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 208 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 209 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 210 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 211 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 212 setOperationAction(ISD::CTTZ, MVT::i64, Expand); 213 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 214 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 215 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 216 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 217 setOperationAction(ISD::ROTL, MVT::i32, Expand); 218 setOperationAction(ISD::ROTL, MVT::i64, Expand); 219 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 220 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 221 222 if (!Subtarget->hasMips32r2()) 223 setOperationAction(ISD::ROTR, MVT::i32, Expand); 224 225 if (!Subtarget->hasMips64r2()) 226 setOperationAction(ISD::ROTR, MVT::i64, Expand); 227 228 setOperationAction(ISD::FSIN, MVT::f32, Expand); 229 setOperationAction(ISD::FSIN, MVT::f64, Expand); 230 setOperationAction(ISD::FCOS, MVT::f32, Expand); 231 setOperationAction(ISD::FCOS, MVT::f64, Expand); 232 setOperationAction(ISD::FPOWI, MVT::f32, Expand); 233 setOperationAction(ISD::FPOW, MVT::f32, Expand); 234 setOperationAction(ISD::FPOW, MVT::f64, Expand); 235 setOperationAction(ISD::FLOG, MVT::f32, Expand); 236 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 237 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 238 setOperationAction(ISD::FEXP, MVT::f32, Expand); 239 setOperationAction(ISD::FMA, MVT::f32, Expand); 240 setOperationAction(ISD::FMA, MVT::f64, Expand); 241 setOperationAction(ISD::FREM, MVT::f32, Expand); 242 setOperationAction(ISD::FREM, MVT::f64, Expand); 243 244 if (!TM.Options.NoNaNsFPMath) { 245 setOperationAction(ISD::FNEG, MVT::f32, Expand); 246 setOperationAction(ISD::FNEG, MVT::f64, Expand); 247 } 248 249 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 250 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 251 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 252 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 253 254 setOperationAction(ISD::VAARG, MVT::Other, Expand); 255 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 256 setOperationAction(ISD::VAEND, MVT::Other, Expand); 257 258 // Use the default for now 259 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 260 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 261 262 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); 263 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); 264 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); 265 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); 266 267 setInsertFencesForAtomic(true); 268 269 if (!Subtarget->hasSEInReg()) { 270 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 271 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 272 } 273 274 if (!Subtarget->hasBitCount()) { 275 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 276 setOperationAction(ISD::CTLZ, MVT::i64, Expand); 277 } 278 279 if (!Subtarget->hasSwap()) { 280 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 281 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 282 } 283 284 if (HasMips64) { 285 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom); 286 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom); 287 setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom); 288 setTruncStoreAction(MVT::i64, MVT::i32, Custom); 289 } 290 291 setTargetDAGCombine(ISD::ADDE); 292 setTargetDAGCombine(ISD::SUBE); 293 setTargetDAGCombine(ISD::SDIVREM); 294 setTargetDAGCombine(ISD::UDIVREM); 295 setTargetDAGCombine(ISD::SELECT); 296 setTargetDAGCombine(ISD::AND); 297 setTargetDAGCombine(ISD::OR); 298 setTargetDAGCombine(ISD::ADD); 299 300 setMinFunctionAlignment(HasMips64 ? 3 : 2); 301 302 setStackPointerRegisterToSaveRestore(IsN64 ? Mips::SP_64 : Mips::SP); 303 computeRegisterProperties(); 304 305 setExceptionPointerRegister(IsN64 ? Mips::A0_64 : Mips::A0); 306 setExceptionSelectorRegister(IsN64 ? Mips::A1_64 : Mips::A1); 307 308 maxStoresPerMemcpy = 16; 309} 310 311bool MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const { 312 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy; 313 314 if (Subtarget->inMips16Mode()) 315 return false; 316 317 switch (SVT) { 318 case MVT::i64: 319 case MVT::i32: 320 return true; 321 default: 322 return false; 323 } 324} 325 326EVT MipsTargetLowering::getSetCCResultType(EVT VT) const { 327 return MVT::i32; 328} 329 330// SelectMadd - 331// Transforms a subgraph in CurDAG if the following pattern is found: 332// (addc multLo, Lo0), (adde multHi, Hi0), 333// where, 334// multHi/Lo: product of multiplication 335// Lo0: initial value of Lo register 336// Hi0: initial value of Hi register 337// Return true if pattern matching was successful. 338static bool SelectMadd(SDNode *ADDENode, SelectionDAG *CurDAG) { 339 // ADDENode's second operand must be a flag output of an ADDC node in order 340 // for the matching to be successful. 341 SDNode *ADDCNode = ADDENode->getOperand(2).getNode(); 342 343 if (ADDCNode->getOpcode() != ISD::ADDC) 344 return false; 345 346 SDValue MultHi = ADDENode->getOperand(0); 347 SDValue MultLo = ADDCNode->getOperand(0); 348 SDNode *MultNode = MultHi.getNode(); 349 unsigned MultOpc = MultHi.getOpcode(); 350 351 // MultHi and MultLo must be generated by the same node, 352 if (MultLo.getNode() != MultNode) 353 return false; 354 355 // and it must be a multiplication. 356 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 357 return false; 358 359 // MultLo amd MultHi must be the first and second output of MultNode 360 // respectively. 361 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 362 return false; 363 364 // Transform this to a MADD only if ADDENode and ADDCNode are the only users 365 // of the values of MultNode, in which case MultNode will be removed in later 366 // phases. 367 // If there exist users other than ADDENode or ADDCNode, this function returns 368 // here, which will result in MultNode being mapped to a single MULT 369 // instruction node rather than a pair of MULT and MADD instructions being 370 // produced. 371 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 372 return false; 373 374 SDValue Chain = CurDAG->getEntryNode(); 375 DebugLoc dl = ADDENode->getDebugLoc(); 376 377 // create MipsMAdd(u) node 378 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd; 379 380 SDValue MAdd = CurDAG->getNode(MultOpc, dl, MVT::Glue, 381 MultNode->getOperand(0),// Factor 0 382 MultNode->getOperand(1),// Factor 1 383 ADDCNode->getOperand(1),// Lo0 384 ADDENode->getOperand(1));// Hi0 385 386 // create CopyFromReg nodes 387 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32, 388 MAdd); 389 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl, 390 Mips::HI, MVT::i32, 391 CopyFromLo.getValue(2)); 392 393 // replace uses of adde and addc here 394 if (!SDValue(ADDCNode, 0).use_empty()) 395 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo); 396 397 if (!SDValue(ADDENode, 0).use_empty()) 398 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi); 399 400 return true; 401} 402 403// SelectMsub - 404// Transforms a subgraph in CurDAG if the following pattern is found: 405// (addc Lo0, multLo), (sube Hi0, multHi), 406// where, 407// multHi/Lo: product of multiplication 408// Lo0: initial value of Lo register 409// Hi0: initial value of Hi register 410// Return true if pattern matching was successful. 411static bool SelectMsub(SDNode *SUBENode, SelectionDAG *CurDAG) { 412 // SUBENode's second operand must be a flag output of an SUBC node in order 413 // for the matching to be successful. 414 SDNode *SUBCNode = SUBENode->getOperand(2).getNode(); 415 416 if (SUBCNode->getOpcode() != ISD::SUBC) 417 return false; 418 419 SDValue MultHi = SUBENode->getOperand(1); 420 SDValue MultLo = SUBCNode->getOperand(1); 421 SDNode *MultNode = MultHi.getNode(); 422 unsigned MultOpc = MultHi.getOpcode(); 423 424 // MultHi and MultLo must be generated by the same node, 425 if (MultLo.getNode() != MultNode) 426 return false; 427 428 // and it must be a multiplication. 429 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 430 return false; 431 432 // MultLo amd MultHi must be the first and second output of MultNode 433 // respectively. 434 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 435 return false; 436 437 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users 438 // of the values of MultNode, in which case MultNode will be removed in later 439 // phases. 440 // If there exist users other than SUBENode or SUBCNode, this function returns 441 // here, which will result in MultNode being mapped to a single MULT 442 // instruction node rather than a pair of MULT and MSUB instructions being 443 // produced. 444 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 445 return false; 446 447 SDValue Chain = CurDAG->getEntryNode(); 448 DebugLoc dl = SUBENode->getDebugLoc(); 449 450 // create MipsSub(u) node 451 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub; 452 453 SDValue MSub = CurDAG->getNode(MultOpc, dl, MVT::Glue, 454 MultNode->getOperand(0),// Factor 0 455 MultNode->getOperand(1),// Factor 1 456 SUBCNode->getOperand(0),// Lo0 457 SUBENode->getOperand(0));// Hi0 458 459 // create CopyFromReg nodes 460 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32, 461 MSub); 462 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl, 463 Mips::HI, MVT::i32, 464 CopyFromLo.getValue(2)); 465 466 // replace uses of sube and subc here 467 if (!SDValue(SUBCNode, 0).use_empty()) 468 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo); 469 470 if (!SDValue(SUBENode, 0).use_empty()) 471 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi); 472 473 return true; 474} 475 476static SDValue PerformADDECombine(SDNode *N, SelectionDAG &DAG, 477 TargetLowering::DAGCombinerInfo &DCI, 478 const MipsSubtarget *Subtarget) { 479 if (DCI.isBeforeLegalize()) 480 return SDValue(); 481 482 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 && 483 SelectMadd(N, &DAG)) 484 return SDValue(N, 0); 485 486 return SDValue(); 487} 488 489static SDValue PerformSUBECombine(SDNode *N, SelectionDAG &DAG, 490 TargetLowering::DAGCombinerInfo &DCI, 491 const MipsSubtarget *Subtarget) { 492 if (DCI.isBeforeLegalize()) 493 return SDValue(); 494 495 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 && 496 SelectMsub(N, &DAG)) 497 return SDValue(N, 0); 498 499 return SDValue(); 500} 501 502static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG &DAG, 503 TargetLowering::DAGCombinerInfo &DCI, 504 const MipsSubtarget *Subtarget) { 505 if (DCI.isBeforeLegalizeOps()) 506 return SDValue(); 507 508 EVT Ty = N->getValueType(0); 509 unsigned LO = (Ty == MVT::i32) ? Mips::LO : Mips::LO64; 510 unsigned HI = (Ty == MVT::i32) ? Mips::HI : Mips::HI64; 511 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem : 512 MipsISD::DivRemU; 513 DebugLoc dl = N->getDebugLoc(); 514 515 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue, 516 N->getOperand(0), N->getOperand(1)); 517 SDValue InChain = DAG.getEntryNode(); 518 SDValue InGlue = DivRem; 519 520 // insert MFLO 521 if (N->hasAnyUseOfValue(0)) { 522 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, LO, Ty, 523 InGlue); 524 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 525 InChain = CopyFromLo.getValue(1); 526 InGlue = CopyFromLo.getValue(2); 527 } 528 529 // insert MFHI 530 if (N->hasAnyUseOfValue(1)) { 531 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl, 532 HI, Ty, InGlue); 533 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 534 } 535 536 return SDValue(); 537} 538 539static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) { 540 switch (CC) { 541 default: llvm_unreachable("Unknown fp condition code!"); 542 case ISD::SETEQ: 543 case ISD::SETOEQ: return Mips::FCOND_OEQ; 544 case ISD::SETUNE: return Mips::FCOND_UNE; 545 case ISD::SETLT: 546 case ISD::SETOLT: return Mips::FCOND_OLT; 547 case ISD::SETGT: 548 case ISD::SETOGT: return Mips::FCOND_OGT; 549 case ISD::SETLE: 550 case ISD::SETOLE: return Mips::FCOND_OLE; 551 case ISD::SETGE: 552 case ISD::SETOGE: return Mips::FCOND_OGE; 553 case ISD::SETULT: return Mips::FCOND_ULT; 554 case ISD::SETULE: return Mips::FCOND_ULE; 555 case ISD::SETUGT: return Mips::FCOND_UGT; 556 case ISD::SETUGE: return Mips::FCOND_UGE; 557 case ISD::SETUO: return Mips::FCOND_UN; 558 case ISD::SETO: return Mips::FCOND_OR; 559 case ISD::SETNE: 560 case ISD::SETONE: return Mips::FCOND_ONE; 561 case ISD::SETUEQ: return Mips::FCOND_UEQ; 562 } 563} 564 565 566// Returns true if condition code has to be inverted. 567static bool InvertFPCondCode(Mips::CondCode CC) { 568 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 569 return false; 570 571 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 572 "Illegal Condition Code"); 573 574 return true; 575} 576 577// Creates and returns an FPCmp node from a setcc node. 578// Returns Op if setcc is not a floating point comparison. 579static SDValue CreateFPCmp(SelectionDAG &DAG, const SDValue &Op) { 580 // must be a SETCC node 581 if (Op.getOpcode() != ISD::SETCC) 582 return Op; 583 584 SDValue LHS = Op.getOperand(0); 585 586 if (!LHS.getValueType().isFloatingPoint()) 587 return Op; 588 589 SDValue RHS = Op.getOperand(1); 590 DebugLoc dl = Op.getDebugLoc(); 591 592 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 593 // node if necessary. 594 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 595 596 return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS, 597 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32)); 598} 599 600// Creates and returns a CMovFPT/F node. 601static SDValue CreateCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, 602 SDValue False, DebugLoc DL) { 603 bool invert = InvertFPCondCode((Mips::CondCode) 604 cast<ConstantSDNode>(Cond.getOperand(2)) 605 ->getSExtValue()); 606 607 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 608 True.getValueType(), True, False, Cond); 609} 610 611static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 612 TargetLowering::DAGCombinerInfo &DCI, 613 const MipsSubtarget *Subtarget) { 614 if (DCI.isBeforeLegalizeOps()) 615 return SDValue(); 616 617 SDValue SetCC = N->getOperand(0); 618 619 if ((SetCC.getOpcode() != ISD::SETCC) || 620 !SetCC.getOperand(0).getValueType().isInteger()) 621 return SDValue(); 622 623 SDValue False = N->getOperand(2); 624 EVT FalseTy = False.getValueType(); 625 626 if (!FalseTy.isInteger()) 627 return SDValue(); 628 629 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(False); 630 631 if (!CN || CN->getZExtValue()) 632 return SDValue(); 633 634 const DebugLoc DL = N->getDebugLoc(); 635 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 636 SDValue True = N->getOperand(1); 637 638 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 639 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 640 641 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); 642} 643 644static SDValue PerformANDCombine(SDNode *N, SelectionDAG &DAG, 645 TargetLowering::DAGCombinerInfo &DCI, 646 const MipsSubtarget *Subtarget) { 647 // Pattern match EXT. 648 // $dst = and ((sra or srl) $src , pos), (2**size - 1) 649 // => ext $dst, $src, size, pos 650 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2()) 651 return SDValue(); 652 653 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1); 654 unsigned ShiftRightOpc = ShiftRight.getOpcode(); 655 656 // Op's first operand must be a shift right. 657 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL) 658 return SDValue(); 659 660 // The second operand of the shift must be an immediate. 661 ConstantSDNode *CN; 662 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1)))) 663 return SDValue(); 664 665 uint64_t Pos = CN->getZExtValue(); 666 uint64_t SMPos, SMSize; 667 668 // Op's second operand must be a shifted mask. 669 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) || 670 !IsShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 671 return SDValue(); 672 673 // Return if the shifted mask does not start at bit 0 or the sum of its size 674 // and Pos exceeds the word's size. 675 EVT ValTy = N->getValueType(0); 676 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits()) 677 return SDValue(); 678 679 return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), ValTy, 680 ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32), 681 DAG.getConstant(SMSize, MVT::i32)); 682} 683 684static SDValue PerformORCombine(SDNode *N, SelectionDAG &DAG, 685 TargetLowering::DAGCombinerInfo &DCI, 686 const MipsSubtarget *Subtarget) { 687 // Pattern match INS. 688 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), 689 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 690 // => ins $dst, $src, size, pos, $src1 691 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2()) 692 return SDValue(); 693 694 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); 695 uint64_t SMPos0, SMSize0, SMPos1, SMSize1; 696 ConstantSDNode *CN; 697 698 // See if Op's first operand matches (and $src1 , mask0). 699 if (And0.getOpcode() != ISD::AND) 700 return SDValue(); 701 702 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) || 703 !IsShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0)) 704 return SDValue(); 705 706 // See if Op's second operand matches (and (shl $src, pos), mask1). 707 if (And1.getOpcode() != ISD::AND) 708 return SDValue(); 709 710 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || 711 !IsShiftedMask(CN->getZExtValue(), SMPos1, SMSize1)) 712 return SDValue(); 713 714 // The shift masks must have the same position and size. 715 if (SMPos0 != SMPos1 || SMSize0 != SMSize1) 716 return SDValue(); 717 718 SDValue Shl = And1.getOperand(0); 719 if (Shl.getOpcode() != ISD::SHL) 720 return SDValue(); 721 722 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1)))) 723 return SDValue(); 724 725 unsigned Shamt = CN->getZExtValue(); 726 727 // Return if the shift amount and the first bit position of mask are not the 728 // same. 729 EVT ValTy = N->getValueType(0); 730 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits())) 731 return SDValue(); 732 733 return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), ValTy, Shl.getOperand(0), 734 DAG.getConstant(SMPos0, MVT::i32), 735 DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0)); 736} 737 738static SDValue PerformADDCombine(SDNode *N, SelectionDAG &DAG, 739 TargetLowering::DAGCombinerInfo &DCI, 740 const MipsSubtarget *Subtarget) { 741 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) 742 743 if (DCI.isBeforeLegalizeOps()) 744 return SDValue(); 745 746 SDValue Add = N->getOperand(1); 747 748 if (Add.getOpcode() != ISD::ADD) 749 return SDValue(); 750 751 SDValue Lo = Add.getOperand(1); 752 753 if ((Lo.getOpcode() != MipsISD::Lo) || 754 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable)) 755 return SDValue(); 756 757 EVT ValTy = N->getValueType(0); 758 DebugLoc DL = N->getDebugLoc(); 759 760 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0), 761 Add.getOperand(0)); 762 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo); 763} 764 765SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 766 const { 767 SelectionDAG &DAG = DCI.DAG; 768 unsigned opc = N->getOpcode(); 769 770 switch (opc) { 771 default: break; 772 case ISD::ADDE: 773 return PerformADDECombine(N, DAG, DCI, Subtarget); 774 case ISD::SUBE: 775 return PerformSUBECombine(N, DAG, DCI, Subtarget); 776 case ISD::SDIVREM: 777 case ISD::UDIVREM: 778 return PerformDivRemCombine(N, DAG, DCI, Subtarget); 779 case ISD::SELECT: 780 return PerformSELECTCombine(N, DAG, DCI, Subtarget); 781 case ISD::AND: 782 return PerformANDCombine(N, DAG, DCI, Subtarget); 783 case ISD::OR: 784 return PerformORCombine(N, DAG, DCI, Subtarget); 785 case ISD::ADD: 786 return PerformADDCombine(N, DAG, DCI, Subtarget); 787 } 788 789 return SDValue(); 790} 791 792SDValue MipsTargetLowering:: 793LowerOperation(SDValue Op, SelectionDAG &DAG) const 794{ 795 switch (Op.getOpcode()) 796 { 797 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 798 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 799 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 800 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 801 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 802 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 803 case ISD::SELECT: return LowerSELECT(Op, DAG); 804 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 805 case ISD::SETCC: return LowerSETCC(Op, DAG); 806 case ISD::VASTART: return LowerVASTART(Op, DAG); 807 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 808 case ISD::FABS: return LowerFABS(Op, DAG); 809 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 810 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 811 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG); 812 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG); 813 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG); 814 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG, true); 815 case ISD::SRL_PARTS: return LowerShiftRightParts(Op, DAG, false); 816 case ISD::LOAD: return LowerLOAD(Op, DAG); 817 case ISD::STORE: return LowerSTORE(Op, DAG); 818 } 819 return SDValue(); 820} 821 822//===----------------------------------------------------------------------===// 823// Lower helper functions 824//===----------------------------------------------------------------------===// 825 826// AddLiveIn - This helper function adds the specified physical register to the 827// MachineFunction as a live in value. It also creates a corresponding 828// virtual register for it. 829static unsigned 830AddLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) 831{ 832 assert(RC->contains(PReg) && "Not the correct regclass!"); 833 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 834 MF.getRegInfo().addLiveIn(PReg, VReg); 835 return VReg; 836} 837 838// Get fp branch code (not opcode) from condition code. 839static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) { 840 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 841 return Mips::BRANCH_T; 842 843 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 844 "Invalid CondCode."); 845 846 return Mips::BRANCH_F; 847} 848 849/* 850static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB, 851 DebugLoc dl, 852 const MipsSubtarget *Subtarget, 853 const TargetInstrInfo *TII, 854 bool isFPCmp, unsigned Opc) { 855 // There is no need to expand CMov instructions if target has 856 // conditional moves. 857 if (Subtarget->hasCondMov()) 858 return BB; 859 860 // To "insert" a SELECT_CC instruction, we actually have to insert the 861 // diamond control-flow pattern. The incoming instruction knows the 862 // destination vreg to set, the condition code register to branch on, the 863 // true/false values to select between, and a branch opcode to use. 864 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 865 MachineFunction::iterator It = BB; 866 ++It; 867 868 // thisMBB: 869 // ... 870 // TrueVal = ... 871 // setcc r1, r2, r3 872 // bNE r1, r0, copy1MBB 873 // fallthrough --> copy0MBB 874 MachineBasicBlock *thisMBB = BB; 875 MachineFunction *F = BB->getParent(); 876 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 877 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 878 F->insert(It, copy0MBB); 879 F->insert(It, sinkMBB); 880 881 // Transfer the remainder of BB and its successor edges to sinkMBB. 882 sinkMBB->splice(sinkMBB->begin(), BB, 883 llvm::next(MachineBasicBlock::iterator(MI)), 884 BB->end()); 885 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 886 887 // Next, add the true and fallthrough blocks as its successors. 888 BB->addSuccessor(copy0MBB); 889 BB->addSuccessor(sinkMBB); 890 891 // Emit the right instruction according to the type of the operands compared 892 if (isFPCmp) 893 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB); 894 else 895 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg()) 896 .addReg(Mips::ZERO).addMBB(sinkMBB); 897 898 // copy0MBB: 899 // %FalseValue = ... 900 // # fallthrough to sinkMBB 901 BB = copy0MBB; 902 903 // Update machine-CFG edges 904 BB->addSuccessor(sinkMBB); 905 906 // sinkMBB: 907 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 908 // ... 909 BB = sinkMBB; 910 911 if (isFPCmp) 912 BuildMI(*BB, BB->begin(), dl, 913 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 914 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB) 915 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB); 916 else 917 BuildMI(*BB, BB->begin(), dl, 918 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 919 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB) 920 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB); 921 922 MI->eraseFromParent(); // The pseudo instruction is gone now. 923 return BB; 924} 925*/ 926MachineBasicBlock * 927MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 928 MachineBasicBlock *BB) const { 929 switch (MI->getOpcode()) { 930 default: llvm_unreachable("Unexpected instr type to insert"); 931 case Mips::ATOMIC_LOAD_ADD_I8: 932 case Mips::ATOMIC_LOAD_ADD_I8_P8: 933 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu); 934 case Mips::ATOMIC_LOAD_ADD_I16: 935 case Mips::ATOMIC_LOAD_ADD_I16_P8: 936 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu); 937 case Mips::ATOMIC_LOAD_ADD_I32: 938 case Mips::ATOMIC_LOAD_ADD_I32_P8: 939 return EmitAtomicBinary(MI, BB, 4, Mips::ADDu); 940 case Mips::ATOMIC_LOAD_ADD_I64: 941 case Mips::ATOMIC_LOAD_ADD_I64_P8: 942 return EmitAtomicBinary(MI, BB, 8, Mips::DADDu); 943 944 case Mips::ATOMIC_LOAD_AND_I8: 945 case Mips::ATOMIC_LOAD_AND_I8_P8: 946 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::AND); 947 case Mips::ATOMIC_LOAD_AND_I16: 948 case Mips::ATOMIC_LOAD_AND_I16_P8: 949 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::AND); 950 case Mips::ATOMIC_LOAD_AND_I32: 951 case Mips::ATOMIC_LOAD_AND_I32_P8: 952 return EmitAtomicBinary(MI, BB, 4, Mips::AND); 953 case Mips::ATOMIC_LOAD_AND_I64: 954 case Mips::ATOMIC_LOAD_AND_I64_P8: 955 return EmitAtomicBinary(MI, BB, 8, Mips::AND64); 956 957 case Mips::ATOMIC_LOAD_OR_I8: 958 case Mips::ATOMIC_LOAD_OR_I8_P8: 959 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::OR); 960 case Mips::ATOMIC_LOAD_OR_I16: 961 case Mips::ATOMIC_LOAD_OR_I16_P8: 962 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::OR); 963 case Mips::ATOMIC_LOAD_OR_I32: 964 case Mips::ATOMIC_LOAD_OR_I32_P8: 965 return EmitAtomicBinary(MI, BB, 4, Mips::OR); 966 case Mips::ATOMIC_LOAD_OR_I64: 967 case Mips::ATOMIC_LOAD_OR_I64_P8: 968 return EmitAtomicBinary(MI, BB, 8, Mips::OR64); 969 970 case Mips::ATOMIC_LOAD_XOR_I8: 971 case Mips::ATOMIC_LOAD_XOR_I8_P8: 972 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::XOR); 973 case Mips::ATOMIC_LOAD_XOR_I16: 974 case Mips::ATOMIC_LOAD_XOR_I16_P8: 975 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::XOR); 976 case Mips::ATOMIC_LOAD_XOR_I32: 977 case Mips::ATOMIC_LOAD_XOR_I32_P8: 978 return EmitAtomicBinary(MI, BB, 4, Mips::XOR); 979 case Mips::ATOMIC_LOAD_XOR_I64: 980 case Mips::ATOMIC_LOAD_XOR_I64_P8: 981 return EmitAtomicBinary(MI, BB, 8, Mips::XOR64); 982 983 case Mips::ATOMIC_LOAD_NAND_I8: 984 case Mips::ATOMIC_LOAD_NAND_I8_P8: 985 return EmitAtomicBinaryPartword(MI, BB, 1, 0, true); 986 case Mips::ATOMIC_LOAD_NAND_I16: 987 case Mips::ATOMIC_LOAD_NAND_I16_P8: 988 return EmitAtomicBinaryPartword(MI, BB, 2, 0, true); 989 case Mips::ATOMIC_LOAD_NAND_I32: 990 case Mips::ATOMIC_LOAD_NAND_I32_P8: 991 return EmitAtomicBinary(MI, BB, 4, 0, true); 992 case Mips::ATOMIC_LOAD_NAND_I64: 993 case Mips::ATOMIC_LOAD_NAND_I64_P8: 994 return EmitAtomicBinary(MI, BB, 8, 0, true); 995 996 case Mips::ATOMIC_LOAD_SUB_I8: 997 case Mips::ATOMIC_LOAD_SUB_I8_P8: 998 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu); 999 case Mips::ATOMIC_LOAD_SUB_I16: 1000 case Mips::ATOMIC_LOAD_SUB_I16_P8: 1001 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu); 1002 case Mips::ATOMIC_LOAD_SUB_I32: 1003 case Mips::ATOMIC_LOAD_SUB_I32_P8: 1004 return EmitAtomicBinary(MI, BB, 4, Mips::SUBu); 1005 case Mips::ATOMIC_LOAD_SUB_I64: 1006 case Mips::ATOMIC_LOAD_SUB_I64_P8: 1007 return EmitAtomicBinary(MI, BB, 8, Mips::DSUBu); 1008 1009 case Mips::ATOMIC_SWAP_I8: 1010 case Mips::ATOMIC_SWAP_I8_P8: 1011 return EmitAtomicBinaryPartword(MI, BB, 1, 0); 1012 case Mips::ATOMIC_SWAP_I16: 1013 case Mips::ATOMIC_SWAP_I16_P8: 1014 return EmitAtomicBinaryPartword(MI, BB, 2, 0); 1015 case Mips::ATOMIC_SWAP_I32: 1016 case Mips::ATOMIC_SWAP_I32_P8: 1017 return EmitAtomicBinary(MI, BB, 4, 0); 1018 case Mips::ATOMIC_SWAP_I64: 1019 case Mips::ATOMIC_SWAP_I64_P8: 1020 return EmitAtomicBinary(MI, BB, 8, 0); 1021 1022 case Mips::ATOMIC_CMP_SWAP_I8: 1023 case Mips::ATOMIC_CMP_SWAP_I8_P8: 1024 return EmitAtomicCmpSwapPartword(MI, BB, 1); 1025 case Mips::ATOMIC_CMP_SWAP_I16: 1026 case Mips::ATOMIC_CMP_SWAP_I16_P8: 1027 return EmitAtomicCmpSwapPartword(MI, BB, 2); 1028 case Mips::ATOMIC_CMP_SWAP_I32: 1029 case Mips::ATOMIC_CMP_SWAP_I32_P8: 1030 return EmitAtomicCmpSwap(MI, BB, 4); 1031 case Mips::ATOMIC_CMP_SWAP_I64: 1032 case Mips::ATOMIC_CMP_SWAP_I64_P8: 1033 return EmitAtomicCmpSwap(MI, BB, 8); 1034 } 1035} 1036 1037// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 1038// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 1039MachineBasicBlock * 1040MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 1041 unsigned Size, unsigned BinOpcode, 1042 bool Nand) const { 1043 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary."); 1044 1045 MachineFunction *MF = BB->getParent(); 1046 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1047 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1048 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1049 DebugLoc dl = MI->getDebugLoc(); 1050 unsigned LL, SC, AND, NOR, ZERO, BEQ; 1051 1052 if (Size == 4) { 1053 LL = IsN64 ? Mips::LL_P8 : Mips::LL; 1054 SC = IsN64 ? Mips::SC_P8 : Mips::SC; 1055 AND = Mips::AND; 1056 NOR = Mips::NOR; 1057 ZERO = Mips::ZERO; 1058 BEQ = Mips::BEQ; 1059 } 1060 else { 1061 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD; 1062 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD; 1063 AND = Mips::AND64; 1064 NOR = Mips::NOR64; 1065 ZERO = Mips::ZERO_64; 1066 BEQ = Mips::BEQ64; 1067 } 1068 1069 unsigned OldVal = MI->getOperand(0).getReg(); 1070 unsigned Ptr = MI->getOperand(1).getReg(); 1071 unsigned Incr = MI->getOperand(2).getReg(); 1072 1073 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1074 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1075 unsigned Success = RegInfo.createVirtualRegister(RC); 1076 1077 // insert new blocks after the current block 1078 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1079 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1080 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1081 MachineFunction::iterator It = BB; 1082 ++It; 1083 MF->insert(It, loopMBB); 1084 MF->insert(It, exitMBB); 1085 1086 // Transfer the remainder of BB and its successor edges to exitMBB. 1087 exitMBB->splice(exitMBB->begin(), BB, 1088 llvm::next(MachineBasicBlock::iterator(MI)), 1089 BB->end()); 1090 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1091 1092 // thisMBB: 1093 // ... 1094 // fallthrough --> loopMBB 1095 BB->addSuccessor(loopMBB); 1096 loopMBB->addSuccessor(loopMBB); 1097 loopMBB->addSuccessor(exitMBB); 1098 1099 // loopMBB: 1100 // ll oldval, 0(ptr) 1101 // <binop> storeval, oldval, incr 1102 // sc success, storeval, 0(ptr) 1103 // beq success, $0, loopMBB 1104 BB = loopMBB; 1105 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(Ptr).addImm(0); 1106 if (Nand) { 1107 // and andres, oldval, incr 1108 // nor storeval, $0, andres 1109 BuildMI(BB, dl, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr); 1110 BuildMI(BB, dl, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes); 1111 } else if (BinOpcode) { 1112 // <binop> storeval, oldval, incr 1113 BuildMI(BB, dl, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr); 1114 } else { 1115 StoreVal = Incr; 1116 } 1117 BuildMI(BB, dl, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0); 1118 BuildMI(BB, dl, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB); 1119 1120 MI->eraseFromParent(); // The instruction is gone now. 1121 1122 return exitMBB; 1123} 1124 1125MachineBasicBlock * 1126MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI, 1127 MachineBasicBlock *BB, 1128 unsigned Size, unsigned BinOpcode, 1129 bool Nand) const { 1130 assert((Size == 1 || Size == 2) && 1131 "Unsupported size for EmitAtomicBinaryPartial."); 1132 1133 MachineFunction *MF = BB->getParent(); 1134 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1135 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1136 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1137 DebugLoc dl = MI->getDebugLoc(); 1138 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL; 1139 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC; 1140 1141 unsigned Dest = MI->getOperand(0).getReg(); 1142 unsigned Ptr = MI->getOperand(1).getReg(); 1143 unsigned Incr = MI->getOperand(2).getReg(); 1144 1145 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 1146 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1147 unsigned Mask = RegInfo.createVirtualRegister(RC); 1148 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1149 unsigned NewVal = RegInfo.createVirtualRegister(RC); 1150 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1151 unsigned Incr2 = RegInfo.createVirtualRegister(RC); 1152 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 1153 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1154 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1155 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1156 unsigned BinOpRes = RegInfo.createVirtualRegister(RC); 1157 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1158 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1159 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1160 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1161 unsigned SllRes = RegInfo.createVirtualRegister(RC); 1162 unsigned Success = RegInfo.createVirtualRegister(RC); 1163 1164 // insert new blocks after the current block 1165 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1166 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1167 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1168 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1169 MachineFunction::iterator It = BB; 1170 ++It; 1171 MF->insert(It, loopMBB); 1172 MF->insert(It, sinkMBB); 1173 MF->insert(It, exitMBB); 1174 1175 // Transfer the remainder of BB and its successor edges to exitMBB. 1176 exitMBB->splice(exitMBB->begin(), BB, 1177 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1178 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1179 1180 BB->addSuccessor(loopMBB); 1181 loopMBB->addSuccessor(loopMBB); 1182 loopMBB->addSuccessor(sinkMBB); 1183 sinkMBB->addSuccessor(exitMBB); 1184 1185 // thisMBB: 1186 // addiu masklsb2,$0,-4 # 0xfffffffc 1187 // and alignedaddr,ptr,masklsb2 1188 // andi ptrlsb2,ptr,3 1189 // sll shiftamt,ptrlsb2,3 1190 // ori maskupper,$0,255 # 0xff 1191 // sll mask,maskupper,shiftamt 1192 // nor mask2,$0,mask 1193 // sll incr2,incr,shiftamt 1194 1195 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1196 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2) 1197 .addReg(Mips::ZERO).addImm(-4); 1198 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr) 1199 .addReg(Ptr).addReg(MaskLSB2); 1200 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1201 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1202 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper) 1203 .addReg(Mips::ZERO).addImm(MaskImm); 1204 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask) 1205 .addReg(ShiftAmt).addReg(MaskUpper); 1206 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1207 BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr); 1208 1209 // atomic.load.binop 1210 // loopMBB: 1211 // ll oldval,0(alignedaddr) 1212 // binop binopres,oldval,incr2 1213 // and newval,binopres,mask 1214 // and maskedoldval0,oldval,mask2 1215 // or storeval,maskedoldval0,newval 1216 // sc success,storeval,0(alignedaddr) 1217 // beq success,$0,loopMBB 1218 1219 // atomic.swap 1220 // loopMBB: 1221 // ll oldval,0(alignedaddr) 1222 // and newval,incr2,mask 1223 // and maskedoldval0,oldval,mask2 1224 // or storeval,maskedoldval0,newval 1225 // sc success,storeval,0(alignedaddr) 1226 // beq success,$0,loopMBB 1227 1228 BB = loopMBB; 1229 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1230 if (Nand) { 1231 // and andres, oldval, incr2 1232 // nor binopres, $0, andres 1233 // and newval, binopres, mask 1234 BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2); 1235 BuildMI(BB, dl, TII->get(Mips::NOR), BinOpRes) 1236 .addReg(Mips::ZERO).addReg(AndRes); 1237 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1238 } else if (BinOpcode) { 1239 // <binop> binopres, oldval, incr2 1240 // and newval, binopres, mask 1241 BuildMI(BB, dl, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2); 1242 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1243 } else {// atomic.swap 1244 // and newval, incr2, mask 1245 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask); 1246 } 1247 1248 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0) 1249 .addReg(OldVal).addReg(Mask2); 1250 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal) 1251 .addReg(MaskedOldVal0).addReg(NewVal); 1252 BuildMI(BB, dl, TII->get(SC), Success) 1253 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1254 BuildMI(BB, dl, TII->get(Mips::BEQ)) 1255 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB); 1256 1257 // sinkMBB: 1258 // and maskedoldval1,oldval,mask 1259 // srl srlres,maskedoldval1,shiftamt 1260 // sll sllres,srlres,24 1261 // sra dest,sllres,24 1262 BB = sinkMBB; 1263 int64_t ShiftImm = (Size == 1) ? 24 : 16; 1264 1265 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1) 1266 .addReg(OldVal).addReg(Mask); 1267 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes) 1268 .addReg(ShiftAmt).addReg(MaskedOldVal1); 1269 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes) 1270 .addReg(SrlRes).addImm(ShiftImm); 1271 BuildMI(BB, dl, TII->get(Mips::SRA), Dest) 1272 .addReg(SllRes).addImm(ShiftImm); 1273 1274 MI->eraseFromParent(); // The instruction is gone now. 1275 1276 return exitMBB; 1277} 1278 1279MachineBasicBlock * 1280MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI, 1281 MachineBasicBlock *BB, 1282 unsigned Size) const { 1283 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap."); 1284 1285 MachineFunction *MF = BB->getParent(); 1286 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1287 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1288 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1289 DebugLoc dl = MI->getDebugLoc(); 1290 unsigned LL, SC, ZERO, BNE, BEQ; 1291 1292 if (Size == 4) { 1293 LL = IsN64 ? Mips::LL_P8 : Mips::LL; 1294 SC = IsN64 ? Mips::SC_P8 : Mips::SC; 1295 ZERO = Mips::ZERO; 1296 BNE = Mips::BNE; 1297 BEQ = Mips::BEQ; 1298 } 1299 else { 1300 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD; 1301 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD; 1302 ZERO = Mips::ZERO_64; 1303 BNE = Mips::BNE64; 1304 BEQ = Mips::BEQ64; 1305 } 1306 1307 unsigned Dest = MI->getOperand(0).getReg(); 1308 unsigned Ptr = MI->getOperand(1).getReg(); 1309 unsigned OldVal = MI->getOperand(2).getReg(); 1310 unsigned NewVal = MI->getOperand(3).getReg(); 1311 1312 unsigned Success = RegInfo.createVirtualRegister(RC); 1313 1314 // insert new blocks after the current block 1315 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1316 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1317 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1318 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1319 MachineFunction::iterator It = BB; 1320 ++It; 1321 MF->insert(It, loop1MBB); 1322 MF->insert(It, loop2MBB); 1323 MF->insert(It, exitMBB); 1324 1325 // Transfer the remainder of BB and its successor edges to exitMBB. 1326 exitMBB->splice(exitMBB->begin(), BB, 1327 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1328 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1329 1330 // thisMBB: 1331 // ... 1332 // fallthrough --> loop1MBB 1333 BB->addSuccessor(loop1MBB); 1334 loop1MBB->addSuccessor(exitMBB); 1335 loop1MBB->addSuccessor(loop2MBB); 1336 loop2MBB->addSuccessor(loop1MBB); 1337 loop2MBB->addSuccessor(exitMBB); 1338 1339 // loop1MBB: 1340 // ll dest, 0(ptr) 1341 // bne dest, oldval, exitMBB 1342 BB = loop1MBB; 1343 BuildMI(BB, dl, TII->get(LL), Dest).addReg(Ptr).addImm(0); 1344 BuildMI(BB, dl, TII->get(BNE)) 1345 .addReg(Dest).addReg(OldVal).addMBB(exitMBB); 1346 1347 // loop2MBB: 1348 // sc success, newval, 0(ptr) 1349 // beq success, $0, loop1MBB 1350 BB = loop2MBB; 1351 BuildMI(BB, dl, TII->get(SC), Success) 1352 .addReg(NewVal).addReg(Ptr).addImm(0); 1353 BuildMI(BB, dl, TII->get(BEQ)) 1354 .addReg(Success).addReg(ZERO).addMBB(loop1MBB); 1355 1356 MI->eraseFromParent(); // The instruction is gone now. 1357 1358 return exitMBB; 1359} 1360 1361MachineBasicBlock * 1362MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI, 1363 MachineBasicBlock *BB, 1364 unsigned Size) const { 1365 assert((Size == 1 || Size == 2) && 1366 "Unsupported size for EmitAtomicCmpSwapPartial."); 1367 1368 MachineFunction *MF = BB->getParent(); 1369 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1370 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1371 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1372 DebugLoc dl = MI->getDebugLoc(); 1373 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL; 1374 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC; 1375 1376 unsigned Dest = MI->getOperand(0).getReg(); 1377 unsigned Ptr = MI->getOperand(1).getReg(); 1378 unsigned CmpVal = MI->getOperand(2).getReg(); 1379 unsigned NewVal = MI->getOperand(3).getReg(); 1380 1381 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 1382 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1383 unsigned Mask = RegInfo.createVirtualRegister(RC); 1384 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1385 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC); 1386 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1387 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1388 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC); 1389 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 1390 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1391 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1392 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC); 1393 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC); 1394 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1395 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1396 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1397 unsigned SllRes = RegInfo.createVirtualRegister(RC); 1398 unsigned Success = RegInfo.createVirtualRegister(RC); 1399 1400 // insert new blocks after the current block 1401 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1402 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1403 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1404 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1405 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1406 MachineFunction::iterator It = BB; 1407 ++It; 1408 MF->insert(It, loop1MBB); 1409 MF->insert(It, loop2MBB); 1410 MF->insert(It, sinkMBB); 1411 MF->insert(It, exitMBB); 1412 1413 // Transfer the remainder of BB and its successor edges to exitMBB. 1414 exitMBB->splice(exitMBB->begin(), BB, 1415 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1416 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1417 1418 BB->addSuccessor(loop1MBB); 1419 loop1MBB->addSuccessor(sinkMBB); 1420 loop1MBB->addSuccessor(loop2MBB); 1421 loop2MBB->addSuccessor(loop1MBB); 1422 loop2MBB->addSuccessor(sinkMBB); 1423 sinkMBB->addSuccessor(exitMBB); 1424 1425 // FIXME: computation of newval2 can be moved to loop2MBB. 1426 // thisMBB: 1427 // addiu masklsb2,$0,-4 # 0xfffffffc 1428 // and alignedaddr,ptr,masklsb2 1429 // andi ptrlsb2,ptr,3 1430 // sll shiftamt,ptrlsb2,3 1431 // ori maskupper,$0,255 # 0xff 1432 // sll mask,maskupper,shiftamt 1433 // nor mask2,$0,mask 1434 // andi maskedcmpval,cmpval,255 1435 // sll shiftedcmpval,maskedcmpval,shiftamt 1436 // andi maskednewval,newval,255 1437 // sll shiftednewval,maskednewval,shiftamt 1438 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1439 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2) 1440 .addReg(Mips::ZERO).addImm(-4); 1441 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr) 1442 .addReg(Ptr).addReg(MaskLSB2); 1443 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1444 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1445 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper) 1446 .addReg(Mips::ZERO).addImm(MaskImm); 1447 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask) 1448 .addReg(ShiftAmt).addReg(MaskUpper); 1449 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1450 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedCmpVal) 1451 .addReg(CmpVal).addImm(MaskImm); 1452 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedCmpVal) 1453 .addReg(ShiftAmt).addReg(MaskedCmpVal); 1454 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedNewVal) 1455 .addReg(NewVal).addImm(MaskImm); 1456 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedNewVal) 1457 .addReg(ShiftAmt).addReg(MaskedNewVal); 1458 1459 // loop1MBB: 1460 // ll oldval,0(alginedaddr) 1461 // and maskedoldval0,oldval,mask 1462 // bne maskedoldval0,shiftedcmpval,sinkMBB 1463 BB = loop1MBB; 1464 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1465 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0) 1466 .addReg(OldVal).addReg(Mask); 1467 BuildMI(BB, dl, TII->get(Mips::BNE)) 1468 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB); 1469 1470 // loop2MBB: 1471 // and maskedoldval1,oldval,mask2 1472 // or storeval,maskedoldval1,shiftednewval 1473 // sc success,storeval,0(alignedaddr) 1474 // beq success,$0,loop1MBB 1475 BB = loop2MBB; 1476 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1) 1477 .addReg(OldVal).addReg(Mask2); 1478 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal) 1479 .addReg(MaskedOldVal1).addReg(ShiftedNewVal); 1480 BuildMI(BB, dl, TII->get(SC), Success) 1481 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1482 BuildMI(BB, dl, TII->get(Mips::BEQ)) 1483 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB); 1484 1485 // sinkMBB: 1486 // srl srlres,maskedoldval0,shiftamt 1487 // sll sllres,srlres,24 1488 // sra dest,sllres,24 1489 BB = sinkMBB; 1490 int64_t ShiftImm = (Size == 1) ? 24 : 16; 1491 1492 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes) 1493 .addReg(ShiftAmt).addReg(MaskedOldVal0); 1494 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes) 1495 .addReg(SrlRes).addImm(ShiftImm); 1496 BuildMI(BB, dl, TII->get(Mips::SRA), Dest) 1497 .addReg(SllRes).addImm(ShiftImm); 1498 1499 MI->eraseFromParent(); // The instruction is gone now. 1500 1501 return exitMBB; 1502} 1503 1504//===----------------------------------------------------------------------===// 1505// Misc Lower Operation implementation 1506//===----------------------------------------------------------------------===// 1507SDValue MipsTargetLowering:: 1508LowerBRCOND(SDValue Op, SelectionDAG &DAG) const 1509{ 1510 // The first operand is the chain, the second is the condition, the third is 1511 // the block to branch to if the condition is true. 1512 SDValue Chain = Op.getOperand(0); 1513 SDValue Dest = Op.getOperand(2); 1514 DebugLoc dl = Op.getDebugLoc(); 1515 1516 SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1)); 1517 1518 // Return if flag is not set by a floating point comparison. 1519 if (CondRes.getOpcode() != MipsISD::FPCmp) 1520 return Op; 1521 1522 SDValue CCNode = CondRes.getOperand(2); 1523 Mips::CondCode CC = 1524 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 1525 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32); 1526 1527 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode, 1528 Dest, CondRes); 1529} 1530 1531SDValue MipsTargetLowering:: 1532LowerSELECT(SDValue Op, SelectionDAG &DAG) const 1533{ 1534 SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0)); 1535 1536 // Return if flag is not set by a floating point comparison. 1537 if (Cond.getOpcode() != MipsISD::FPCmp) 1538 return Op; 1539 1540 return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 1541 Op.getDebugLoc()); 1542} 1543 1544SDValue MipsTargetLowering:: 1545LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const 1546{ 1547 DebugLoc DL = Op.getDebugLoc(); 1548 EVT Ty = Op.getOperand(0).getValueType(); 1549 SDValue Cond = DAG.getNode(ISD::SETCC, DL, getSetCCResultType(Ty), 1550 Op.getOperand(0), Op.getOperand(1), 1551 Op.getOperand(4)); 1552 1553 return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2), 1554 Op.getOperand(3)); 1555} 1556 1557SDValue MipsTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 1558 SDValue Cond = CreateFPCmp(DAG, Op); 1559 1560 assert(Cond.getOpcode() == MipsISD::FPCmp && 1561 "Floating point operand expected."); 1562 1563 SDValue True = DAG.getConstant(1, MVT::i32); 1564 SDValue False = DAG.getConstant(0, MVT::i32); 1565 1566 return CreateCMovFP(DAG, Cond, True, False, Op.getDebugLoc()); 1567} 1568 1569SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op, 1570 SelectionDAG &DAG) const { 1571 // FIXME there isn't actually debug info here 1572 DebugLoc dl = Op.getDebugLoc(); 1573 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 1574 1575 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) { 1576 SDVTList VTs = DAG.getVTList(MVT::i32); 1577 1578 const MipsTargetObjectFile &TLOF = 1579 (const MipsTargetObjectFile&)getObjFileLowering(); 1580 1581 // %gp_rel relocation 1582 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) { 1583 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1584 MipsII::MO_GPREL); 1585 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1); 1586 SDValue GPReg = DAG.getRegister(Mips::GP, MVT::i32); 1587 return DAG.getNode(ISD::ADD, dl, MVT::i32, GPReg, GPRelNode); 1588 } 1589 // %hi/%lo relocation 1590 SDValue GAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1591 MipsII::MO_ABS_HI); 1592 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1593 MipsII::MO_ABS_LO); 1594 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GAHi, 1); 1595 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo); 1596 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 1597 } 1598 1599 EVT ValTy = Op.getValueType(); 1600 bool HasGotOfst = (GV->hasInternalLinkage() || 1601 (GV->hasLocalLinkage() && !isa<Function>(GV))); 1602 unsigned GotFlag = HasMips64 ? 1603 (HasGotOfst ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT_DISP) : 1604 (HasGotOfst ? MipsII::MO_GOT : MipsII::MO_GOT16); 1605 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0, GotFlag); 1606 GA = DAG.getNode(MipsISD::Wrapper, dl, ValTy, GetGlobalReg(DAG, ValTy), GA); 1607 SDValue ResNode = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), GA, 1608 MachinePointerInfo(), false, false, false, 0); 1609 // On functions and global targets not internal linked only 1610 // a load from got/GP is necessary for PIC to work. 1611 if (!HasGotOfst) 1612 return ResNode; 1613 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0, 1614 HasMips64 ? MipsII::MO_GOT_OFST : 1615 MipsII::MO_ABS_LO); 1616 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, GALo); 1617 return DAG.getNode(ISD::ADD, dl, ValTy, ResNode, Lo); 1618} 1619 1620SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op, 1621 SelectionDAG &DAG) const { 1622 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 1623 // FIXME there isn't actually debug info here 1624 DebugLoc dl = Op.getDebugLoc(); 1625 1626 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) { 1627 // %hi/%lo relocation 1628 SDValue BAHi = DAG.getTargetBlockAddress(BA, MVT::i32, 0, MipsII::MO_ABS_HI); 1629 SDValue BALo = DAG.getTargetBlockAddress(BA, MVT::i32, 0, MipsII::MO_ABS_LO); 1630 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, MVT::i32, BAHi); 1631 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALo); 1632 return DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo); 1633 } 1634 1635 EVT ValTy = Op.getValueType(); 1636 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT; 1637 unsigned OFSTFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO; 1638 SDValue BAGOTOffset = DAG.getTargetBlockAddress(BA, ValTy, 0, GOTFlag); 1639 BAGOTOffset = DAG.getNode(MipsISD::Wrapper, dl, ValTy, 1640 GetGlobalReg(DAG, ValTy), BAGOTOffset); 1641 SDValue BALOOffset = DAG.getTargetBlockAddress(BA, ValTy, 0, OFSTFlag); 1642 SDValue Load = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), BAGOTOffset, 1643 MachinePointerInfo(), false, false, false, 0); 1644 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, BALOOffset); 1645 return DAG.getNode(ISD::ADD, dl, ValTy, Load, Lo); 1646} 1647 1648SDValue MipsTargetLowering:: 1649LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 1650{ 1651 // If the relocation model is PIC, use the General Dynamic TLS Model or 1652 // Local Dynamic TLS model, otherwise use the Initial Exec or 1653 // Local Exec TLS Model. 1654 1655 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1656 DebugLoc dl = GA->getDebugLoc(); 1657 const GlobalValue *GV = GA->getGlobal(); 1658 EVT PtrVT = getPointerTy(); 1659 1660 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 1661 1662 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) { 1663 // General Dynamic and Local Dynamic TLS Model. 1664 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM 1665 : MipsII::MO_TLSGD; 1666 1667 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, Flag); 1668 SDValue Argument = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, 1669 GetGlobalReg(DAG, PtrVT), TGA); 1670 unsigned PtrSize = PtrVT.getSizeInBits(); 1671 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize); 1672 1673 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT); 1674 1675 ArgListTy Args; 1676 ArgListEntry Entry; 1677 Entry.Node = Argument; 1678 Entry.Ty = PtrTy; 1679 Args.push_back(Entry); 1680 1681 TargetLowering::CallLoweringInfo CLI(DAG.getEntryNode(), PtrTy, 1682 false, false, false, false, 0, CallingConv::C, 1683 /*isTailCall=*/false, /*doesNotRet=*/false, 1684 /*isReturnValueUsed=*/true, 1685 TlsGetAddr, Args, DAG, dl); 1686 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 1687 1688 SDValue Ret = CallResult.first; 1689 1690 if (model != TLSModel::LocalDynamic) 1691 return Ret; 1692 1693 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1694 MipsII::MO_DTPREL_HI); 1695 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi); 1696 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1697 MipsII::MO_DTPREL_LO); 1698 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo); 1699 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Ret); 1700 return DAG.getNode(ISD::ADD, dl, PtrVT, Add, Lo); 1701 } 1702 1703 SDValue Offset; 1704 if (model == TLSModel::InitialExec) { 1705 // Initial Exec TLS Model 1706 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1707 MipsII::MO_GOTTPREL); 1708 TGA = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, GetGlobalReg(DAG, PtrVT), 1709 TGA); 1710 Offset = DAG.getLoad(PtrVT, dl, 1711 DAG.getEntryNode(), TGA, MachinePointerInfo(), 1712 false, false, false, 0); 1713 } else { 1714 // Local Exec TLS Model 1715 assert(model == TLSModel::LocalExec); 1716 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1717 MipsII::MO_TPREL_HI); 1718 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1719 MipsII::MO_TPREL_LO); 1720 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi); 1721 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo); 1722 Offset = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); 1723 } 1724 1725 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, dl, PtrVT); 1726 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 1727} 1728 1729SDValue MipsTargetLowering:: 1730LowerJumpTable(SDValue Op, SelectionDAG &DAG) const 1731{ 1732 SDValue HiPart, JTI, JTILo; 1733 // FIXME there isn't actually debug info here 1734 DebugLoc dl = Op.getDebugLoc(); 1735 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 1736 EVT PtrVT = Op.getValueType(); 1737 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 1738 1739 if (!IsPIC && !IsN64) { 1740 JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MipsII::MO_ABS_HI); 1741 HiPart = DAG.getNode(MipsISD::Hi, dl, PtrVT, JTI); 1742 JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MipsII::MO_ABS_LO); 1743 } else {// Emit Load from Global Pointer 1744 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT; 1745 unsigned OfstFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO; 1746 JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, GOTFlag); 1747 JTI = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, GetGlobalReg(DAG, PtrVT), 1748 JTI); 1749 HiPart = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), JTI, 1750 MachinePointerInfo(), false, false, false, 0); 1751 JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OfstFlag); 1752 } 1753 1754 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, JTILo); 1755 return DAG.getNode(ISD::ADD, dl, PtrVT, HiPart, Lo); 1756} 1757 1758SDValue MipsTargetLowering:: 1759LowerConstantPool(SDValue Op, SelectionDAG &DAG) const 1760{ 1761 SDValue ResNode; 1762 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 1763 const Constant *C = N->getConstVal(); 1764 // FIXME there isn't actually debug info here 1765 DebugLoc dl = Op.getDebugLoc(); 1766 1767 // gp_rel relocation 1768 // FIXME: we should reference the constant pool using small data sections, 1769 // but the asm printer currently doesn't support this feature without 1770 // hacking it. This feature should come soon so we can uncomment the 1771 // stuff below. 1772 //if (IsInSmallSection(C->getType())) { 1773 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP); 1774 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); 1775 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode); 1776 1777 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) { 1778 SDValue CPHi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 1779 N->getOffset(), MipsII::MO_ABS_HI); 1780 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 1781 N->getOffset(), MipsII::MO_ABS_LO); 1782 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CPHi); 1783 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo); 1784 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 1785 } else { 1786 EVT ValTy = Op.getValueType(); 1787 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT; 1788 unsigned OFSTFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO; 1789 SDValue CP = DAG.getTargetConstantPool(C, ValTy, N->getAlignment(), 1790 N->getOffset(), GOTFlag); 1791 CP = DAG.getNode(MipsISD::Wrapper, dl, ValTy, GetGlobalReg(DAG, ValTy), CP); 1792 SDValue Load = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), CP, 1793 MachinePointerInfo::getConstantPool(), false, 1794 false, false, 0); 1795 SDValue CPLo = DAG.getTargetConstantPool(C, ValTy, N->getAlignment(), 1796 N->getOffset(), OFSTFlag); 1797 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, CPLo); 1798 ResNode = DAG.getNode(ISD::ADD, dl, ValTy, Load, Lo); 1799 } 1800 1801 return ResNode; 1802} 1803 1804SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 1805 MachineFunction &MF = DAG.getMachineFunction(); 1806 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 1807 1808 DebugLoc dl = Op.getDebugLoc(); 1809 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1810 getPointerTy()); 1811 1812 // vastart just stores the address of the VarArgsFrameIndex slot into the 1813 // memory location argument. 1814 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1815 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1), 1816 MachinePointerInfo(SV), false, false, 0); 1817} 1818 1819static SDValue LowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasR2) { 1820 EVT TyX = Op.getOperand(0).getValueType(); 1821 EVT TyY = Op.getOperand(1).getValueType(); 1822 SDValue Const1 = DAG.getConstant(1, MVT::i32); 1823 SDValue Const31 = DAG.getConstant(31, MVT::i32); 1824 DebugLoc DL = Op.getDebugLoc(); 1825 SDValue Res; 1826 1827 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 1828 // to i32. 1829 SDValue X = (TyX == MVT::f32) ? 1830 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 1831 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 1832 Const1); 1833 SDValue Y = (TyY == MVT::f32) ? 1834 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) : 1835 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1), 1836 Const1); 1837 1838 if (HasR2) { 1839 // ext E, Y, 31, 1 ; extract bit31 of Y 1840 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X 1841 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1); 1842 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X); 1843 } else { 1844 // sll SllX, X, 1 1845 // srl SrlX, SllX, 1 1846 // srl SrlY, Y, 31 1847 // sll SllY, SrlX, 31 1848 // or Or, SrlX, SllY 1849 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 1850 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 1851 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); 1852 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31); 1853 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY); 1854 } 1855 1856 if (TyX == MVT::f32) 1857 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res); 1858 1859 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 1860 Op.getOperand(0), DAG.getConstant(0, MVT::i32)); 1861 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 1862} 1863 1864static SDValue LowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasR2) { 1865 unsigned WidthX = Op.getOperand(0).getValueSizeInBits(); 1866 unsigned WidthY = Op.getOperand(1).getValueSizeInBits(); 1867 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY); 1868 SDValue Const1 = DAG.getConstant(1, MVT::i32); 1869 DebugLoc DL = Op.getDebugLoc(); 1870 1871 // Bitcast to integer nodes. 1872 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0)); 1873 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1)); 1874 1875 if (HasR2) { 1876 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y 1877 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X 1878 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y, 1879 DAG.getConstant(WidthY - 1, MVT::i32), Const1); 1880 1881 if (WidthX > WidthY) 1882 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E); 1883 else if (WidthY > WidthX) 1884 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E); 1885 1886 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E, 1887 DAG.getConstant(WidthX - 1, MVT::i32), Const1, X); 1888 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I); 1889 } 1890 1891 // (d)sll SllX, X, 1 1892 // (d)srl SrlX, SllX, 1 1893 // (d)srl SrlY, Y, width(Y)-1 1894 // (d)sll SllY, SrlX, width(Y)-1 1895 // or Or, SrlX, SllY 1896 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1); 1897 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); 1898 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, 1899 DAG.getConstant(WidthY - 1, MVT::i32)); 1900 1901 if (WidthX > WidthY) 1902 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY); 1903 else if (WidthY > WidthX) 1904 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY); 1905 1906 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY, 1907 DAG.getConstant(WidthX - 1, MVT::i32)); 1908 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY); 1909 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or); 1910} 1911 1912SDValue 1913MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 1914 if (Subtarget->hasMips64()) 1915 return LowerFCOPYSIGN64(Op, DAG, Subtarget->hasMips32r2()); 1916 1917 return LowerFCOPYSIGN32(Op, DAG, Subtarget->hasMips32r2()); 1918} 1919 1920static SDValue LowerFABS32(SDValue Op, SelectionDAG &DAG, bool HasR2) { 1921 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32); 1922 DebugLoc DL = Op.getDebugLoc(); 1923 1924 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 1925 // to i32. 1926 SDValue X = (Op.getValueType() == MVT::f32) ? 1927 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 1928 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 1929 Const1); 1930 1931 // Clear MSB. 1932 if (HasR2) 1933 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, 1934 DAG.getRegister(Mips::ZERO, MVT::i32), 1935 DAG.getConstant(31, MVT::i32), Const1, X); 1936 else { 1937 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 1938 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 1939 } 1940 1941 if (Op.getValueType() == MVT::f32) 1942 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res); 1943 1944 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 1945 Op.getOperand(0), DAG.getConstant(0, MVT::i32)); 1946 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 1947} 1948 1949static SDValue LowerFABS64(SDValue Op, SelectionDAG &DAG, bool HasR2) { 1950 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32); 1951 DebugLoc DL = Op.getDebugLoc(); 1952 1953 // Bitcast to integer node. 1954 SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0)); 1955 1956 // Clear MSB. 1957 if (HasR2) 1958 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64, 1959 DAG.getRegister(Mips::ZERO_64, MVT::i64), 1960 DAG.getConstant(63, MVT::i32), Const1, X); 1961 else { 1962 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1); 1963 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1); 1964 } 1965 1966 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res); 1967} 1968 1969SDValue 1970MipsTargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const { 1971 if (Subtarget->hasMips64() && (Op.getValueType() == MVT::f64)) 1972 return LowerFABS64(Op, DAG, Subtarget->hasMips32r2()); 1973 1974 return LowerFABS32(Op, DAG, Subtarget->hasMips32r2()); 1975} 1976 1977SDValue MipsTargetLowering:: 1978LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 1979 // check the depth 1980 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 1981 "Frame address can only be determined for current frame."); 1982 1983 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1984 MFI->setFrameAddressIsTaken(true); 1985 EVT VT = Op.getValueType(); 1986 DebugLoc dl = Op.getDebugLoc(); 1987 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 1988 IsN64 ? Mips::FP_64 : Mips::FP, VT); 1989 return FrameAddr; 1990} 1991 1992SDValue MipsTargetLowering::LowerRETURNADDR(SDValue Op, 1993 SelectionDAG &DAG) const { 1994 // check the depth 1995 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 1996 "Return address can be determined only for current frame."); 1997 1998 MachineFunction &MF = DAG.getMachineFunction(); 1999 MachineFrameInfo *MFI = MF.getFrameInfo(); 2000 EVT VT = Op.getValueType(); 2001 unsigned RA = IsN64 ? Mips::RA_64 : Mips::RA; 2002 MFI->setReturnAddressIsTaken(true); 2003 2004 // Return RA, which contains the return address. Mark it an implicit live-in. 2005 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); 2006 return DAG.getCopyFromReg(DAG.getEntryNode(), Op.getDebugLoc(), Reg, VT); 2007} 2008 2009// TODO: set SType according to the desired memory barrier behavior. 2010SDValue 2011MipsTargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const { 2012 unsigned SType = 0; 2013 DebugLoc dl = Op.getDebugLoc(); 2014 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0), 2015 DAG.getConstant(SType, MVT::i32)); 2016} 2017 2018SDValue MipsTargetLowering::LowerATOMIC_FENCE(SDValue Op, 2019 SelectionDAG &DAG) const { 2020 // FIXME: Need pseudo-fence for 'singlethread' fences 2021 // FIXME: Set SType for weaker fences where supported/appropriate. 2022 unsigned SType = 0; 2023 DebugLoc dl = Op.getDebugLoc(); 2024 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0), 2025 DAG.getConstant(SType, MVT::i32)); 2026} 2027 2028SDValue MipsTargetLowering::LowerShiftLeftParts(SDValue Op, 2029 SelectionDAG &DAG) const { 2030 DebugLoc DL = Op.getDebugLoc(); 2031 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2032 SDValue Shamt = Op.getOperand(2); 2033 2034 // if shamt < 32: 2035 // lo = (shl lo, shamt) 2036 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt)) 2037 // else: 2038 // lo = 0 2039 // hi = (shl lo, shamt[4:0]) 2040 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2041 DAG.getConstant(-1, MVT::i32)); 2042 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, 2043 DAG.getConstant(1, MVT::i32)); 2044 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo, 2045 Not); 2046 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt); 2047 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo); 2048 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt); 2049 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2050 DAG.getConstant(0x20, MVT::i32)); 2051 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, 2052 DAG.getConstant(0, MVT::i32), ShiftLeftLo); 2053 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or); 2054 2055 SDValue Ops[2] = {Lo, Hi}; 2056 return DAG.getMergeValues(Ops, 2, DL); 2057} 2058 2059SDValue MipsTargetLowering::LowerShiftRightParts(SDValue Op, SelectionDAG &DAG, 2060 bool IsSRA) const { 2061 DebugLoc DL = Op.getDebugLoc(); 2062 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2063 SDValue Shamt = Op.getOperand(2); 2064 2065 // if shamt < 32: 2066 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt)) 2067 // if isSRA: 2068 // hi = (sra hi, shamt) 2069 // else: 2070 // hi = (srl hi, shamt) 2071 // else: 2072 // if isSRA: 2073 // lo = (sra hi, shamt[4:0]) 2074 // hi = (sra hi, 31) 2075 // else: 2076 // lo = (srl hi, shamt[4:0]) 2077 // hi = 0 2078 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2079 DAG.getConstant(-1, MVT::i32)); 2080 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, 2081 DAG.getConstant(1, MVT::i32)); 2082 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not); 2083 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt); 2084 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo); 2085 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32, 2086 Hi, Shamt); 2087 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2088 DAG.getConstant(0x20, MVT::i32)); 2089 SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi, 2090 DAG.getConstant(31, MVT::i32)); 2091 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or); 2092 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, 2093 IsSRA ? Shift31 : DAG.getConstant(0, MVT::i32), 2094 ShiftRightHi); 2095 2096 SDValue Ops[2] = {Lo, Hi}; 2097 return DAG.getMergeValues(Ops, 2, DL); 2098} 2099 2100static SDValue CreateLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, 2101 SDValue Chain, SDValue Src, unsigned Offset) { 2102 SDValue Ptr = LD->getBasePtr(); 2103 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT(); 2104 EVT BasePtrVT = Ptr.getValueType(); 2105 DebugLoc DL = LD->getDebugLoc(); 2106 SDVTList VTList = DAG.getVTList(VT, MVT::Other); 2107 2108 if (Offset) 2109 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2110 DAG.getConstant(Offset, BasePtrVT)); 2111 2112 SDValue Ops[] = { Chain, Ptr, Src }; 2113 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT, 2114 LD->getMemOperand()); 2115} 2116 2117// Expand an unaligned 32 or 64-bit integer load node. 2118SDValue MipsTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const { 2119 LoadSDNode *LD = cast<LoadSDNode>(Op); 2120 EVT MemVT = LD->getMemoryVT(); 2121 2122 // Return if load is aligned or if MemVT is neither i32 nor i64. 2123 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) || 2124 ((MemVT != MVT::i32) && (MemVT != MVT::i64))) 2125 return SDValue(); 2126 2127 bool IsLittle = Subtarget->isLittle(); 2128 EVT VT = Op.getValueType(); 2129 ISD::LoadExtType ExtType = LD->getExtensionType(); 2130 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT); 2131 2132 assert((VT == MVT::i32) || (VT == MVT::i64)); 2133 2134 // Expand 2135 // (set dst, (i64 (load baseptr))) 2136 // to 2137 // (set tmp, (ldl (add baseptr, 7), undef)) 2138 // (set dst, (ldr baseptr, tmp)) 2139 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) { 2140 SDValue LDL = CreateLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef, 2141 IsLittle ? 7 : 0); 2142 return CreateLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL, 2143 IsLittle ? 0 : 7); 2144 } 2145 2146 SDValue LWL = CreateLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, 2147 IsLittle ? 3 : 0); 2148 SDValue LWR = CreateLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, 2149 IsLittle ? 0 : 3); 2150 2151 // Expand 2152 // (set dst, (i32 (load baseptr))) or 2153 // (set dst, (i64 (sextload baseptr))) or 2154 // (set dst, (i64 (extload baseptr))) 2155 // to 2156 // (set tmp, (lwl (add baseptr, 3), undef)) 2157 // (set dst, (lwr baseptr, tmp)) 2158 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) || 2159 (ExtType == ISD::EXTLOAD)) 2160 return LWR; 2161 2162 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)); 2163 2164 // Expand 2165 // (set dst, (i64 (zextload baseptr))) 2166 // to 2167 // (set tmp0, (lwl (add baseptr, 3), undef)) 2168 // (set tmp1, (lwr baseptr, tmp0)) 2169 // (set tmp2, (shl tmp1, 32)) 2170 // (set dst, (srl tmp2, 32)) 2171 DebugLoc DL = LD->getDebugLoc(); 2172 SDValue Const32 = DAG.getConstant(32, MVT::i32); 2173 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); 2174 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); 2175 SDValue Ops[] = { SRL, LWR.getValue(1) }; 2176 return DAG.getMergeValues(Ops, 2, DL); 2177} 2178 2179static SDValue CreateStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, 2180 SDValue Chain, unsigned Offset) { 2181 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue(); 2182 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType(); 2183 DebugLoc DL = SD->getDebugLoc(); 2184 SDVTList VTList = DAG.getVTList(MVT::Other); 2185 2186 if (Offset) 2187 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2188 DAG.getConstant(Offset, BasePtrVT)); 2189 2190 SDValue Ops[] = { Chain, Value, Ptr }; 2191 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT, 2192 SD->getMemOperand()); 2193} 2194 2195// Expand an unaligned 32 or 64-bit integer store node. 2196SDValue MipsTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const { 2197 StoreSDNode *SD = cast<StoreSDNode>(Op); 2198 EVT MemVT = SD->getMemoryVT(); 2199 2200 // Return if store is aligned or if MemVT is neither i32 nor i64. 2201 if ((SD->getAlignment() >= MemVT.getSizeInBits() / 8) || 2202 ((MemVT != MVT::i32) && (MemVT != MVT::i64))) 2203 return SDValue(); 2204 2205 bool IsLittle = Subtarget->isLittle(); 2206 SDValue Value = SD->getValue(), Chain = SD->getChain(); 2207 EVT VT = Value.getValueType(); 2208 2209 // Expand 2210 // (store val, baseptr) or 2211 // (truncstore val, baseptr) 2212 // to 2213 // (swl val, (add baseptr, 3)) 2214 // (swr val, baseptr) 2215 if ((VT == MVT::i32) || SD->isTruncatingStore()) { 2216 SDValue SWL = CreateStoreLR(MipsISD::SWL, DAG, SD, Chain, 2217 IsLittle ? 3 : 0); 2218 return CreateStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); 2219 } 2220 2221 assert(VT == MVT::i64); 2222 2223 // Expand 2224 // (store val, baseptr) 2225 // to 2226 // (sdl val, (add baseptr, 7)) 2227 // (sdr val, baseptr) 2228 SDValue SDL = CreateStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0); 2229 return CreateStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7); 2230} 2231 2232//===----------------------------------------------------------------------===// 2233// Calling Convention Implementation 2234//===----------------------------------------------------------------------===// 2235 2236//===----------------------------------------------------------------------===// 2237// TODO: Implement a generic logic using tblgen that can support this. 2238// Mips O32 ABI rules: 2239// --- 2240// i32 - Passed in A0, A1, A2, A3 and stack 2241// f32 - Only passed in f32 registers if no int reg has been used yet to hold 2242// an argument. Otherwise, passed in A1, A2, A3 and stack. 2243// f64 - Only passed in two aliased f32 registers if no int reg has been used 2244// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 2245// not used, it must be shadowed. If only A3 is avaiable, shadow it and 2246// go to stack. 2247// 2248// For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 2249//===----------------------------------------------------------------------===// 2250 2251static bool CC_MipsO32(unsigned ValNo, MVT ValVT, 2252 MVT LocVT, CCValAssign::LocInfo LocInfo, 2253 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2254 2255 static const unsigned IntRegsSize=4, FloatRegsSize=2; 2256 2257 static const uint16_t IntRegs[] = { 2258 Mips::A0, Mips::A1, Mips::A2, Mips::A3 2259 }; 2260 static const uint16_t F32Regs[] = { 2261 Mips::F12, Mips::F14 2262 }; 2263 static const uint16_t F64Regs[] = { 2264 Mips::D6, Mips::D7 2265 }; 2266 2267 // ByVal Args 2268 if (ArgFlags.isByVal()) { 2269 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 2270 1 /*MinSize*/, 4 /*MinAlign*/, ArgFlags); 2271 unsigned NextReg = (State.getNextStackOffset() + 3) / 4; 2272 for (unsigned r = State.getFirstUnallocated(IntRegs, IntRegsSize); 2273 r < std::min(IntRegsSize, NextReg); ++r) 2274 State.AllocateReg(IntRegs[r]); 2275 return false; 2276 } 2277 2278 // Promote i8 and i16 2279 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 2280 LocVT = MVT::i32; 2281 if (ArgFlags.isSExt()) 2282 LocInfo = CCValAssign::SExt; 2283 else if (ArgFlags.isZExt()) 2284 LocInfo = CCValAssign::ZExt; 2285 else 2286 LocInfo = CCValAssign::AExt; 2287 } 2288 2289 unsigned Reg; 2290 2291 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 2292 // is true: function is vararg, argument is 3rd or higher, there is previous 2293 // argument which is not f32 or f64. 2294 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 2295 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo; 2296 unsigned OrigAlign = ArgFlags.getOrigAlign(); 2297 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8); 2298 2299 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 2300 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2301 // If this is the first part of an i64 arg, 2302 // the allocated register must be either A0 or A2. 2303 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 2304 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2305 LocVT = MVT::i32; 2306 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 2307 // Allocate int register and shadow next int register. If first 2308 // available register is Mips::A1 or Mips::A3, shadow it too. 2309 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2310 if (Reg == Mips::A1 || Reg == Mips::A3) 2311 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2312 State.AllocateReg(IntRegs, IntRegsSize); 2313 LocVT = MVT::i32; 2314 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 2315 // we are guaranteed to find an available float register 2316 if (ValVT == MVT::f32) { 2317 Reg = State.AllocateReg(F32Regs, FloatRegsSize); 2318 // Shadow int register 2319 State.AllocateReg(IntRegs, IntRegsSize); 2320 } else { 2321 Reg = State.AllocateReg(F64Regs, FloatRegsSize); 2322 // Shadow int registers 2323 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize); 2324 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 2325 State.AllocateReg(IntRegs, IntRegsSize); 2326 State.AllocateReg(IntRegs, IntRegsSize); 2327 } 2328 } else 2329 llvm_unreachable("Cannot handle this ValVT."); 2330 2331 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3; 2332 unsigned Offset = State.AllocateStack(SizeInBytes, OrigAlign); 2333 2334 if (!Reg) 2335 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 2336 else 2337 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2338 2339 return false; // CC must always match 2340} 2341 2342static const uint16_t Mips64IntRegs[8] = 2343 {Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, 2344 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64}; 2345static const uint16_t Mips64DPRegs[8] = 2346 {Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, 2347 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64}; 2348 2349static bool CC_Mips64Byval(unsigned ValNo, MVT ValVT, MVT LocVT, 2350 CCValAssign::LocInfo LocInfo, 2351 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2352 unsigned Align = std::max(ArgFlags.getByValAlign(), (unsigned)8); 2353 unsigned Size = (ArgFlags.getByValSize() + 7) / 8 * 8; 2354 unsigned FirstIdx = State.getFirstUnallocated(Mips64IntRegs, 8); 2355 2356 assert(Align <= 16 && "Cannot handle alignments larger than 16."); 2357 2358 // If byval is 16-byte aligned, the first arg register must be even. 2359 if ((Align == 16) && (FirstIdx % 2)) { 2360 State.AllocateReg(Mips64IntRegs[FirstIdx], Mips64DPRegs[FirstIdx]); 2361 ++FirstIdx; 2362 } 2363 2364 // Mark the registers allocated. 2365 for (unsigned I = FirstIdx; Size && (I < 8); Size -= 8, ++I) 2366 State.AllocateReg(Mips64IntRegs[I], Mips64DPRegs[I]); 2367 2368 // Allocate space on caller's stack. 2369 unsigned Offset = State.AllocateStack(Size, Align); 2370 2371 if (FirstIdx < 8) 2372 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Mips64IntRegs[FirstIdx], 2373 LocVT, LocInfo)); 2374 else 2375 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 2376 2377 return true; 2378} 2379 2380#include "MipsGenCallingConv.inc" 2381 2382static void 2383AnalyzeMips64CallOperands(CCState &CCInfo, 2384 const SmallVectorImpl<ISD::OutputArg> &Outs) { 2385 unsigned NumOps = Outs.size(); 2386 for (unsigned i = 0; i != NumOps; ++i) { 2387 MVT ArgVT = Outs[i].VT; 2388 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; 2389 bool R; 2390 2391 if (Outs[i].IsFixed) 2392 R = CC_MipsN(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo); 2393 else 2394 R = CC_MipsN_VarArg(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo); 2395 2396 if (R) { 2397#ifndef NDEBUG 2398 dbgs() << "Call operand #" << i << " has unhandled type " 2399 << EVT(ArgVT).getEVTString(); 2400#endif 2401 llvm_unreachable(0); 2402 } 2403 } 2404} 2405 2406//===----------------------------------------------------------------------===// 2407// Call Calling Convention Implementation 2408//===----------------------------------------------------------------------===// 2409 2410static const unsigned O32IntRegsSize = 4; 2411 2412static const uint16_t O32IntRegs[] = { 2413 Mips::A0, Mips::A1, Mips::A2, Mips::A3 2414}; 2415 2416// Return next O32 integer argument register. 2417static unsigned getNextIntArgReg(unsigned Reg) { 2418 assert((Reg == Mips::A0) || (Reg == Mips::A2)); 2419 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3; 2420} 2421 2422// Write ByVal Arg to arg registers and stack. 2423static void 2424WriteByValArg(SDValue Chain, DebugLoc dl, 2425 SmallVector<std::pair<unsigned, SDValue>, 16> &RegsToPass, 2426 SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr, 2427 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, 2428 const CCValAssign &VA, const ISD::ArgFlagsTy &Flags, 2429 MVT PtrType, bool isLittle) { 2430 unsigned LocMemOffset = VA.getLocMemOffset(); 2431 unsigned Offset = 0; 2432 uint32_t RemainingSize = Flags.getByValSize(); 2433 unsigned ByValAlign = Flags.getByValAlign(); 2434 2435 // Copy the first 4 words of byval arg to registers A0 - A3. 2436 // FIXME: Use a stricter alignment if it enables better optimization in passes 2437 // run later. 2438 for (; RemainingSize >= 4 && LocMemOffset < 4 * 4; 2439 Offset += 4, RemainingSize -= 4, LocMemOffset += 4) { 2440 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 2441 DAG.getConstant(Offset, MVT::i32)); 2442 SDValue LoadVal = DAG.getLoad(MVT::i32, dl, Chain, LoadPtr, 2443 MachinePointerInfo(), false, false, false, 2444 std::min(ByValAlign, (unsigned )4)); 2445 MemOpChains.push_back(LoadVal.getValue(1)); 2446 unsigned DstReg = O32IntRegs[LocMemOffset / 4]; 2447 RegsToPass.push_back(std::make_pair(DstReg, LoadVal)); 2448 } 2449 2450 if (RemainingSize == 0) 2451 return; 2452 2453 // If there still is a register available for argument passing, write the 2454 // remaining part of the structure to it using subword loads and shifts. 2455 if (LocMemOffset < 4 * 4) { 2456 assert(RemainingSize <= 3 && RemainingSize >= 1 && 2457 "There must be one to three bytes remaining."); 2458 unsigned LoadSize = (RemainingSize == 3 ? 2 : RemainingSize); 2459 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 2460 DAG.getConstant(Offset, MVT::i32)); 2461 unsigned Alignment = std::min(ByValAlign, (unsigned )4); 2462 SDValue LoadVal = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain, 2463 LoadPtr, MachinePointerInfo(), 2464 MVT::getIntegerVT(LoadSize * 8), false, 2465 false, Alignment); 2466 MemOpChains.push_back(LoadVal.getValue(1)); 2467 2468 // If target is big endian, shift it to the most significant half-word or 2469 // byte. 2470 if (!isLittle) 2471 LoadVal = DAG.getNode(ISD::SHL, dl, MVT::i32, LoadVal, 2472 DAG.getConstant(32 - LoadSize * 8, MVT::i32)); 2473 2474 Offset += LoadSize; 2475 RemainingSize -= LoadSize; 2476 2477 // Read second subword if necessary. 2478 if (RemainingSize != 0) { 2479 assert(RemainingSize == 1 && "There must be one byte remaining."); 2480 LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 2481 DAG.getConstant(Offset, MVT::i32)); 2482 unsigned Alignment = std::min(ByValAlign, (unsigned )2); 2483 SDValue Subword = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain, 2484 LoadPtr, MachinePointerInfo(), 2485 MVT::i8, false, false, Alignment); 2486 MemOpChains.push_back(Subword.getValue(1)); 2487 // Insert the loaded byte to LoadVal. 2488 // FIXME: Use INS if supported by target. 2489 unsigned ShiftAmt = isLittle ? 16 : 8; 2490 SDValue Shift = DAG.getNode(ISD::SHL, dl, MVT::i32, Subword, 2491 DAG.getConstant(ShiftAmt, MVT::i32)); 2492 LoadVal = DAG.getNode(ISD::OR, dl, MVT::i32, LoadVal, Shift); 2493 } 2494 2495 unsigned DstReg = O32IntRegs[LocMemOffset / 4]; 2496 RegsToPass.push_back(std::make_pair(DstReg, LoadVal)); 2497 return; 2498 } 2499 2500 // Copy remaining part of byval arg using memcpy. 2501 SDValue Src = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 2502 DAG.getConstant(Offset, MVT::i32)); 2503 SDValue Dst = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, 2504 DAG.getIntPtrConstant(LocMemOffset)); 2505 Chain = DAG.getMemcpy(Chain, dl, Dst, Src, 2506 DAG.getConstant(RemainingSize, MVT::i32), 2507 std::min(ByValAlign, (unsigned)4), 2508 /*isVolatile=*/false, /*AlwaysInline=*/false, 2509 MachinePointerInfo(0), MachinePointerInfo(0)); 2510 MemOpChains.push_back(Chain); 2511} 2512 2513// Copy Mips64 byVal arg to registers and stack. 2514void static 2515PassByValArg64(SDValue Chain, DebugLoc dl, 2516 SmallVector<std::pair<unsigned, SDValue>, 16> &RegsToPass, 2517 SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr, 2518 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, 2519 const CCValAssign &VA, const ISD::ArgFlagsTy &Flags, 2520 EVT PtrTy, bool isLittle) { 2521 unsigned ByValSize = Flags.getByValSize(); 2522 unsigned Alignment = std::min(Flags.getByValAlign(), (unsigned)8); 2523 bool IsRegLoc = VA.isRegLoc(); 2524 unsigned Offset = 0; // Offset in # of bytes from the beginning of struct. 2525 unsigned LocMemOffset = 0; 2526 unsigned MemCpySize = ByValSize; 2527 2528 if (!IsRegLoc) 2529 LocMemOffset = VA.getLocMemOffset(); 2530 else { 2531 const uint16_t *Reg = std::find(Mips64IntRegs, Mips64IntRegs + 8, 2532 VA.getLocReg()); 2533 const uint16_t *RegEnd = Mips64IntRegs + 8; 2534 2535 // Copy double words to registers. 2536 for (; (Reg != RegEnd) && (ByValSize >= Offset + 8); ++Reg, Offset += 8) { 2537 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, PtrTy, Arg, 2538 DAG.getConstant(Offset, PtrTy)); 2539 SDValue LoadVal = DAG.getLoad(MVT::i64, dl, Chain, LoadPtr, 2540 MachinePointerInfo(), false, false, false, 2541 Alignment); 2542 MemOpChains.push_back(LoadVal.getValue(1)); 2543 RegsToPass.push_back(std::make_pair(*Reg, LoadVal)); 2544 } 2545 2546 // Return if the struct has been fully copied. 2547 if (!(MemCpySize = ByValSize - Offset)) 2548 return; 2549 2550 // If there is an argument register available, copy the remainder of the 2551 // byval argument with sub-doubleword loads and shifts. 2552 if (Reg != RegEnd) { 2553 assert((ByValSize < Offset + 8) && 2554 "Size of the remainder should be smaller than 8-byte."); 2555 SDValue Val; 2556 for (unsigned LoadSize = 4; Offset < ByValSize; LoadSize /= 2) { 2557 unsigned RemSize = ByValSize - Offset; 2558 2559 if (RemSize < LoadSize) 2560 continue; 2561 2562 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, PtrTy, Arg, 2563 DAG.getConstant(Offset, PtrTy)); 2564 SDValue LoadVal = 2565 DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i64, Chain, LoadPtr, 2566 MachinePointerInfo(), MVT::getIntegerVT(LoadSize * 8), 2567 false, false, Alignment); 2568 MemOpChains.push_back(LoadVal.getValue(1)); 2569 2570 // Offset in number of bits from double word boundary. 2571 unsigned OffsetDW = (Offset % 8) * 8; 2572 unsigned Shamt = isLittle ? OffsetDW : 64 - (OffsetDW + LoadSize * 8); 2573 SDValue Shift = DAG.getNode(ISD::SHL, dl, MVT::i64, LoadVal, 2574 DAG.getConstant(Shamt, MVT::i32)); 2575 2576 Val = Val.getNode() ? DAG.getNode(ISD::OR, dl, MVT::i64, Val, Shift) : 2577 Shift; 2578 Offset += LoadSize; 2579 Alignment = std::min(Alignment, LoadSize); 2580 } 2581 2582 RegsToPass.push_back(std::make_pair(*Reg, Val)); 2583 return; 2584 } 2585 } 2586 2587 assert(MemCpySize && "MemCpySize must not be zero."); 2588 2589 // Copy remainder of byval arg to it with memcpy. 2590 SDValue Src = DAG.getNode(ISD::ADD, dl, PtrTy, Arg, 2591 DAG.getConstant(Offset, PtrTy)); 2592 SDValue Dst = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, 2593 DAG.getIntPtrConstant(LocMemOffset)); 2594 Chain = DAG.getMemcpy(Chain, dl, Dst, Src, 2595 DAG.getConstant(MemCpySize, PtrTy), Alignment, 2596 /*isVolatile=*/false, /*AlwaysInline=*/false, 2597 MachinePointerInfo(0), MachinePointerInfo(0)); 2598 MemOpChains.push_back(Chain); 2599} 2600 2601/// LowerCall - functions arguments are copied from virtual regs to 2602/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 2603/// TODO: isTailCall. 2604SDValue 2605MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 2606 SmallVectorImpl<SDValue> &InVals) const { 2607 SelectionDAG &DAG = CLI.DAG; 2608 DebugLoc &dl = CLI.DL; 2609 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; 2610 SmallVector<SDValue, 32> &OutVals = CLI.OutVals; 2611 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; 2612 SDValue Chain = CLI.Chain; 2613 SDValue Callee = CLI.Callee; 2614 bool &isTailCall = CLI.IsTailCall; 2615 CallingConv::ID CallConv = CLI.CallConv; 2616 bool isVarArg = CLI.IsVarArg; 2617 2618 // MIPs target does not yet support tail call optimization. 2619 isTailCall = false; 2620 2621 MachineFunction &MF = DAG.getMachineFunction(); 2622 MachineFrameInfo *MFI = MF.getFrameInfo(); 2623 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering(); 2624 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 2625 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2626 2627 // Analyze operands of the call, assigning locations to each operand. 2628 SmallVector<CCValAssign, 16> ArgLocs; 2629 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2630 getTargetMachine(), ArgLocs, *DAG.getContext()); 2631 2632 if (CallConv == CallingConv::Fast) 2633 CCInfo.AnalyzeCallOperands(Outs, CC_Mips_FastCC); 2634 else if (IsO32) 2635 CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32); 2636 else if (HasMips64) 2637 AnalyzeMips64CallOperands(CCInfo, Outs); 2638 else 2639 CCInfo.AnalyzeCallOperands(Outs, CC_Mips); 2640 2641 // Get a count of how many bytes are to be pushed on the stack. 2642 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 2643 unsigned StackAlignment = TFL->getStackAlignment(); 2644 NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment); 2645 2646 // Update size of the maximum argument space. 2647 // For O32, a minimum of four words (16 bytes) of argument space is 2648 // allocated. 2649 if (IsO32 && (CallConv != CallingConv::Fast)) 2650 NextStackOffset = std::max(NextStackOffset, (unsigned)16); 2651 2652 // Chain is the output chain of the last Load/Store or CopyToReg node. 2653 // ByValChain is the output chain of the last Memcpy node created for copying 2654 // byval arguments to the stack. 2655 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true); 2656 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal); 2657 2658 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, 2659 IsN64 ? Mips::SP_64 : Mips::SP, 2660 getPointerTy()); 2661 2662 if (MipsFI->getMaxCallFrameSize() < NextStackOffset) 2663 MipsFI->setMaxCallFrameSize(NextStackOffset); 2664 2665 // With EABI is it possible to have 16 args on registers. 2666 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass; 2667 SmallVector<SDValue, 8> MemOpChains; 2668 2669 // Walk the register/memloc assignments, inserting copies/loads. 2670 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2671 SDValue Arg = OutVals[i]; 2672 CCValAssign &VA = ArgLocs[i]; 2673 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); 2674 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2675 2676 // ByVal Arg. 2677 if (Flags.isByVal()) { 2678 assert(Flags.getByValSize() && 2679 "ByVal args of size 0 should have been ignored by front-end."); 2680 if (IsO32) 2681 WriteByValArg(Chain, dl, RegsToPass, MemOpChains, StackPtr, 2682 MFI, DAG, Arg, VA, Flags, getPointerTy(), 2683 Subtarget->isLittle()); 2684 else 2685 PassByValArg64(Chain, dl, RegsToPass, MemOpChains, StackPtr, 2686 MFI, DAG, Arg, VA, Flags, getPointerTy(), 2687 Subtarget->isLittle()); 2688 continue; 2689 } 2690 2691 // Promote the value if needed. 2692 switch (VA.getLocInfo()) { 2693 default: llvm_unreachable("Unknown loc info!"); 2694 case CCValAssign::Full: 2695 if (VA.isRegLoc()) { 2696 if ((ValVT == MVT::f32 && LocVT == MVT::i32) || 2697 (ValVT == MVT::f64 && LocVT == MVT::i64)) 2698 Arg = DAG.getNode(ISD::BITCAST, dl, LocVT, Arg); 2699 else if (ValVT == MVT::f64 && LocVT == MVT::i32) { 2700 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 2701 Arg, DAG.getConstant(0, MVT::i32)); 2702 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 2703 Arg, DAG.getConstant(1, MVT::i32)); 2704 if (!Subtarget->isLittle()) 2705 std::swap(Lo, Hi); 2706 unsigned LocRegLo = VA.getLocReg(); 2707 unsigned LocRegHigh = getNextIntArgReg(LocRegLo); 2708 RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); 2709 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); 2710 continue; 2711 } 2712 } 2713 break; 2714 case CCValAssign::SExt: 2715 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, LocVT, Arg); 2716 break; 2717 case CCValAssign::ZExt: 2718 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, LocVT, Arg); 2719 break; 2720 case CCValAssign::AExt: 2721 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, LocVT, Arg); 2722 break; 2723 } 2724 2725 // Arguments that can be passed on register must be kept at 2726 // RegsToPass vector 2727 if (VA.isRegLoc()) { 2728 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2729 continue; 2730 } 2731 2732 // Register can't get to this point... 2733 assert(VA.isMemLoc()); 2734 2735 // emit ISD::STORE whichs stores the 2736 // parameter value to a stack Location 2737 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, 2738 DAG.getIntPtrConstant(VA.getLocMemOffset())); 2739 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 2740 MachinePointerInfo(), false, false, 0)); 2741 } 2742 2743 // Transform all store nodes into one single node because all store 2744 // nodes are independent of each other. 2745 if (!MemOpChains.empty()) 2746 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2747 &MemOpChains[0], MemOpChains.size()); 2748 2749 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 2750 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 2751 // node so that legalize doesn't hack it. 2752 unsigned char OpFlag; 2753 bool IsPICCall = (IsN64 || IsPIC); // true if calls are translated to jalr $25 2754 bool GlobalOrExternal = false; 2755 SDValue CalleeLo; 2756 2757 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2758 if (IsPICCall && G->getGlobal()->hasInternalLinkage()) { 2759 OpFlag = IsO32 ? MipsII::MO_GOT : MipsII::MO_GOT_PAGE; 2760 unsigned char LoFlag = IsO32 ? MipsII::MO_ABS_LO : MipsII::MO_GOT_OFST; 2761 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 0, 2762 OpFlag); 2763 CalleeLo = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 2764 0, LoFlag); 2765 } else { 2766 OpFlag = IsPICCall ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG; 2767 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, 2768 getPointerTy(), 0, OpFlag); 2769 } 2770 2771 GlobalOrExternal = true; 2772 } 2773 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2774 if (IsN64 || (!IsO32 && IsPIC)) 2775 OpFlag = MipsII::MO_GOT_DISP; 2776 else if (!IsPIC) // !N64 && static 2777 OpFlag = MipsII::MO_NO_FLAG; 2778 else // O32 & PIC 2779 OpFlag = MipsII::MO_GOT_CALL; 2780 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2781 OpFlag); 2782 GlobalOrExternal = true; 2783 } 2784 2785 SDValue InFlag; 2786 2787 // Create nodes that load address of callee and copy it to T9 2788 if (IsPICCall) { 2789 if (GlobalOrExternal) { 2790 // Load callee address 2791 Callee = DAG.getNode(MipsISD::Wrapper, dl, getPointerTy(), 2792 GetGlobalReg(DAG, getPointerTy()), Callee); 2793 SDValue LoadValue = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 2794 Callee, MachinePointerInfo::getGOT(), 2795 false, false, false, 0); 2796 2797 // Use GOT+LO if callee has internal linkage. 2798 if (CalleeLo.getNode()) { 2799 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, getPointerTy(), CalleeLo); 2800 Callee = DAG.getNode(ISD::ADD, dl, getPointerTy(), LoadValue, Lo); 2801 } else 2802 Callee = LoadValue; 2803 } 2804 } 2805 2806 // T9 register operand. 2807 SDValue T9; 2808 2809 // T9 should contain the address of the callee function if 2810 // -reloction-model=pic or it is an indirect call. 2811 if (IsPICCall || !GlobalOrExternal) { 2812 // copy to T9 2813 unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9; 2814 Chain = DAG.getCopyToReg(Chain, dl, T9Reg, Callee, SDValue(0, 0)); 2815 InFlag = Chain.getValue(1); 2816 2817 if (Subtarget->inMips16Mode()) 2818 T9 = DAG.getRegister(T9Reg, getPointerTy()); 2819 else 2820 Callee = DAG.getRegister(T9Reg, getPointerTy()); 2821 } 2822 2823 // Insert node "GP copy globalreg" before call to function. 2824 // Lazy-binding stubs require GP to point to the GOT. 2825 if (IsPICCall) { 2826 unsigned GPReg = IsN64 ? Mips::GP_64 : Mips::GP; 2827 EVT Ty = IsN64 ? MVT::i64 : MVT::i32; 2828 RegsToPass.push_back(std::make_pair(GPReg, GetGlobalReg(DAG, Ty))); 2829 } 2830 2831 // Build a sequence of copy-to-reg nodes chained together with token 2832 // chain and flag operands which copy the outgoing args into registers. 2833 // The InFlag in necessary since all emitted instructions must be 2834 // stuck together. 2835 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2836 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2837 RegsToPass[i].second, InFlag); 2838 InFlag = Chain.getValue(1); 2839 } 2840 2841 // MipsJmpLink = #chain, #target_address, #opt_in_flags... 2842 // = Chain, Callee, Reg#1, Reg#2, ... 2843 // 2844 // Returns a chain & a flag for retval copy to use. 2845 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2846 SmallVector<SDValue, 8> Ops; 2847 Ops.push_back(Chain); 2848 Ops.push_back(Callee); 2849 2850 // Add argument registers to the end of the list so that they are 2851 // known live into the call. 2852 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2853 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2854 RegsToPass[i].second.getValueType())); 2855 2856 // Add T9 register operand. 2857 if (T9.getNode()) 2858 Ops.push_back(T9); 2859 2860 // Add a register mask operand representing the call-preserved registers. 2861 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 2862 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv); 2863 assert(Mask && "Missing call preserved mask for calling convention"); 2864 Ops.push_back(DAG.getRegisterMask(Mask)); 2865 2866 if (InFlag.getNode()) 2867 Ops.push_back(InFlag); 2868 2869 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size()); 2870 InFlag = Chain.getValue(1); 2871 2872 // Create the CALLSEQ_END node. 2873 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal, 2874 DAG.getIntPtrConstant(0, true), InFlag); 2875 InFlag = Chain.getValue(1); 2876 2877 // Handle result values, copying them out of physregs into vregs that we 2878 // return. 2879 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2880 Ins, dl, DAG, InVals); 2881} 2882 2883/// LowerCallResult - Lower the result values of a call into the 2884/// appropriate copies out of appropriate physical registers. 2885SDValue 2886MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 2887 CallingConv::ID CallConv, bool isVarArg, 2888 const SmallVectorImpl<ISD::InputArg> &Ins, 2889 DebugLoc dl, SelectionDAG &DAG, 2890 SmallVectorImpl<SDValue> &InVals) const { 2891 // Assign locations to each value returned by this call. 2892 SmallVector<CCValAssign, 16> RVLocs; 2893 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2894 getTargetMachine(), RVLocs, *DAG.getContext()); 2895 2896 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips); 2897 2898 // Copy all of the result registers out of their specified physreg. 2899 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2900 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), 2901 RVLocs[i].getValVT(), InFlag).getValue(1); 2902 InFlag = Chain.getValue(2); 2903 InVals.push_back(Chain.getValue(0)); 2904 } 2905 2906 return Chain; 2907} 2908 2909//===----------------------------------------------------------------------===// 2910// Formal Arguments Calling Convention Implementation 2911//===----------------------------------------------------------------------===// 2912static void ReadByValArg(MachineFunction &MF, SDValue Chain, DebugLoc dl, 2913 std::vector<SDValue> &OutChains, 2914 SelectionDAG &DAG, unsigned NumWords, SDValue FIN, 2915 const CCValAssign &VA, const ISD::ArgFlagsTy &Flags, 2916 const Argument *FuncArg) { 2917 unsigned LocMem = VA.getLocMemOffset(); 2918 unsigned FirstWord = LocMem / 4; 2919 2920 // copy register A0 - A3 to frame object 2921 for (unsigned i = 0; i < NumWords; ++i) { 2922 unsigned CurWord = FirstWord + i; 2923 if (CurWord >= O32IntRegsSize) 2924 break; 2925 2926 unsigned SrcReg = O32IntRegs[CurWord]; 2927 unsigned Reg = AddLiveIn(MF, SrcReg, &Mips::CPURegsRegClass); 2928 SDValue StorePtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIN, 2929 DAG.getConstant(i * 4, MVT::i32)); 2930 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(Reg, MVT::i32), 2931 StorePtr, MachinePointerInfo(FuncArg, i * 4), 2932 false, false, 0); 2933 OutChains.push_back(Store); 2934 } 2935} 2936 2937// Create frame object on stack and copy registers used for byval passing to it. 2938static unsigned 2939CopyMips64ByValRegs(MachineFunction &MF, SDValue Chain, DebugLoc dl, 2940 std::vector<SDValue> &OutChains, SelectionDAG &DAG, 2941 const CCValAssign &VA, const ISD::ArgFlagsTy &Flags, 2942 MachineFrameInfo *MFI, bool IsRegLoc, 2943 SmallVectorImpl<SDValue> &InVals, MipsFunctionInfo *MipsFI, 2944 EVT PtrTy, const Argument *FuncArg) { 2945 const uint16_t *Reg = Mips64IntRegs + 8; 2946 int FOOffset; // Frame object offset from virtual frame pointer. 2947 2948 if (IsRegLoc) { 2949 Reg = std::find(Mips64IntRegs, Mips64IntRegs + 8, VA.getLocReg()); 2950 FOOffset = (Reg - Mips64IntRegs) * 8 - 8 * 8; 2951 } 2952 else 2953 FOOffset = VA.getLocMemOffset(); 2954 2955 // Create frame object. 2956 unsigned NumRegs = (Flags.getByValSize() + 7) / 8; 2957 unsigned LastFI = MFI->CreateFixedObject(NumRegs * 8, FOOffset, true); 2958 SDValue FIN = DAG.getFrameIndex(LastFI, PtrTy); 2959 InVals.push_back(FIN); 2960 2961 // Copy arg registers. 2962 for (unsigned I = 0; (Reg != Mips64IntRegs + 8) && (I < NumRegs); 2963 ++Reg, ++I) { 2964 unsigned VReg = AddLiveIn(MF, *Reg, &Mips::CPU64RegsRegClass); 2965 SDValue StorePtr = DAG.getNode(ISD::ADD, dl, PtrTy, FIN, 2966 DAG.getConstant(I * 8, PtrTy)); 2967 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(VReg, MVT::i64), 2968 StorePtr, MachinePointerInfo(FuncArg, I * 8), 2969 false, false, 0); 2970 OutChains.push_back(Store); 2971 } 2972 2973 return LastFI; 2974} 2975 2976/// LowerFormalArguments - transform physical registers into virtual registers 2977/// and generate load operations for arguments places on the stack. 2978SDValue 2979MipsTargetLowering::LowerFormalArguments(SDValue Chain, 2980 CallingConv::ID CallConv, 2981 bool isVarArg, 2982 const SmallVectorImpl<ISD::InputArg> &Ins, 2983 DebugLoc dl, SelectionDAG &DAG, 2984 SmallVectorImpl<SDValue> &InVals) 2985 const { 2986 MachineFunction &MF = DAG.getMachineFunction(); 2987 MachineFrameInfo *MFI = MF.getFrameInfo(); 2988 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2989 2990 MipsFI->setVarArgsFrameIndex(0); 2991 2992 // Used with vargs to acumulate store chains. 2993 std::vector<SDValue> OutChains; 2994 2995 // Assign locations to all of the incoming arguments. 2996 SmallVector<CCValAssign, 16> ArgLocs; 2997 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2998 getTargetMachine(), ArgLocs, *DAG.getContext()); 2999 3000 if (CallConv == CallingConv::Fast) 3001 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FastCC); 3002 else if (IsO32) 3003 CCInfo.AnalyzeFormalArguments(Ins, CC_MipsO32); 3004 else 3005 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips); 3006 3007 Function::const_arg_iterator FuncArg = 3008 DAG.getMachineFunction().getFunction()->arg_begin(); 3009 int LastFI = 0;// MipsFI->LastInArgFI is 0 at the entry of this function. 3010 3011 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i, ++FuncArg) { 3012 CCValAssign &VA = ArgLocs[i]; 3013 EVT ValVT = VA.getValVT(); 3014 ISD::ArgFlagsTy Flags = Ins[i].Flags; 3015 bool IsRegLoc = VA.isRegLoc(); 3016 3017 if (Flags.isByVal()) { 3018 assert(Flags.getByValSize() && 3019 "ByVal args of size 0 should have been ignored by front-end."); 3020 if (IsO32) { 3021 unsigned NumWords = (Flags.getByValSize() + 3) / 4; 3022 LastFI = MFI->CreateFixedObject(NumWords * 4, VA.getLocMemOffset(), 3023 true); 3024 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy()); 3025 InVals.push_back(FIN); 3026 ReadByValArg(MF, Chain, dl, OutChains, DAG, NumWords, FIN, VA, Flags, 3027 &*FuncArg); 3028 } else // N32/64 3029 LastFI = CopyMips64ByValRegs(MF, Chain, dl, OutChains, DAG, VA, Flags, 3030 MFI, IsRegLoc, InVals, MipsFI, 3031 getPointerTy(), &*FuncArg); 3032 continue; 3033 } 3034 3035 // Arguments stored on registers 3036 if (IsRegLoc) { 3037 EVT RegVT = VA.getLocVT(); 3038 unsigned ArgReg = VA.getLocReg(); 3039 const TargetRegisterClass *RC; 3040 3041 if (RegVT == MVT::i32) 3042 RC = &Mips::CPURegsRegClass; 3043 else if (RegVT == MVT::i64) 3044 RC = &Mips::CPU64RegsRegClass; 3045 else if (RegVT == MVT::f32) 3046 RC = &Mips::FGR32RegClass; 3047 else if (RegVT == MVT::f64) 3048 RC = HasMips64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; 3049 else 3050 llvm_unreachable("RegVT not supported by FormalArguments Lowering"); 3051 3052 // Transform the arguments stored on 3053 // physical registers into virtual ones 3054 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgReg, RC); 3055 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 3056 3057 // If this is an 8 or 16-bit value, it has been passed promoted 3058 // to 32 bits. Insert an assert[sz]ext to capture this, then 3059 // truncate to the right size. 3060 if (VA.getLocInfo() != CCValAssign::Full) { 3061 unsigned Opcode = 0; 3062 if (VA.getLocInfo() == CCValAssign::SExt) 3063 Opcode = ISD::AssertSext; 3064 else if (VA.getLocInfo() == CCValAssign::ZExt) 3065 Opcode = ISD::AssertZext; 3066 if (Opcode) 3067 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue, 3068 DAG.getValueType(ValVT)); 3069 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, ValVT, ArgValue); 3070 } 3071 3072 // Handle floating point arguments passed in integer registers. 3073 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || 3074 (RegVT == MVT::i64 && ValVT == MVT::f64)) 3075 ArgValue = DAG.getNode(ISD::BITCAST, dl, ValVT, ArgValue); 3076 else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) { 3077 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(), 3078 getNextIntArgReg(ArgReg), RC); 3079 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT); 3080 if (!Subtarget->isLittle()) 3081 std::swap(ArgValue, ArgValue2); 3082 ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64, 3083 ArgValue, ArgValue2); 3084 } 3085 3086 InVals.push_back(ArgValue); 3087 } else { // VA.isRegLoc() 3088 3089 // sanity check 3090 assert(VA.isMemLoc()); 3091 3092 // The stack pointer offset is relative to the caller stack frame. 3093 LastFI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 3094 VA.getLocMemOffset(), true); 3095 3096 // Create load nodes to retrieve arguments from the stack 3097 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy()); 3098 InVals.push_back(DAG.getLoad(ValVT, dl, Chain, FIN, 3099 MachinePointerInfo::getFixedStack(LastFI), 3100 false, false, false, 0)); 3101 } 3102 } 3103 3104 // The mips ABIs for returning structs by value requires that we copy 3105 // the sret argument into $v0 for the return. Save the argument into 3106 // a virtual register so that we can access it from the return points. 3107 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 3108 unsigned Reg = MipsFI->getSRetReturnReg(); 3109 if (!Reg) { 3110 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32)); 3111 MipsFI->setSRetReturnReg(Reg); 3112 } 3113 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 3114 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 3115 } 3116 3117 if (isVarArg) { 3118 unsigned NumOfRegs = IsO32 ? 4 : 8; 3119 const uint16_t *ArgRegs = IsO32 ? O32IntRegs : Mips64IntRegs; 3120 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumOfRegs); 3121 int FirstRegSlotOffset = IsO32 ? 0 : -64 ; // offset of $a0's slot. 3122 const TargetRegisterClass *RC = IsO32 ? 3123 (const TargetRegisterClass*)&Mips::CPURegsRegClass : 3124 (const TargetRegisterClass*)&Mips::CPU64RegsRegClass; 3125 unsigned RegSize = RC->getSize(); 3126 int RegSlotOffset = FirstRegSlotOffset + Idx * RegSize; 3127 3128 // Offset of the first variable argument from stack pointer. 3129 int FirstVaArgOffset; 3130 3131 if (IsO32 || (Idx == NumOfRegs)) { 3132 FirstVaArgOffset = 3133 (CCInfo.getNextStackOffset() + RegSize - 1) / RegSize * RegSize; 3134 } else 3135 FirstVaArgOffset = RegSlotOffset; 3136 3137 // Record the frame index of the first variable argument 3138 // which is a value necessary to VASTART. 3139 LastFI = MFI->CreateFixedObject(RegSize, FirstVaArgOffset, true); 3140 MipsFI->setVarArgsFrameIndex(LastFI); 3141 3142 // Copy the integer registers that have not been used for argument passing 3143 // to the argument register save area. For O32, the save area is allocated 3144 // in the caller's stack frame, while for N32/64, it is allocated in the 3145 // callee's stack frame. 3146 for (int StackOffset = RegSlotOffset; 3147 Idx < NumOfRegs; ++Idx, StackOffset += RegSize) { 3148 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgRegs[Idx], RC); 3149 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, 3150 MVT::getIntegerVT(RegSize * 8)); 3151 LastFI = MFI->CreateFixedObject(RegSize, StackOffset, true); 3152 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy()); 3153 OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff, 3154 MachinePointerInfo(), false, false, 0)); 3155 } 3156 } 3157 3158 MipsFI->setLastInArgFI(LastFI); 3159 3160 // All stores are grouped in one node to allow the matching between 3161 // the size of Ins and InVals. This only happens when on varg functions 3162 if (!OutChains.empty()) { 3163 OutChains.push_back(Chain); 3164 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3165 &OutChains[0], OutChains.size()); 3166 } 3167 3168 return Chain; 3169} 3170 3171//===----------------------------------------------------------------------===// 3172// Return Value Calling Convention Implementation 3173//===----------------------------------------------------------------------===// 3174 3175SDValue 3176MipsTargetLowering::LowerReturn(SDValue Chain, 3177 CallingConv::ID CallConv, bool isVarArg, 3178 const SmallVectorImpl<ISD::OutputArg> &Outs, 3179 const SmallVectorImpl<SDValue> &OutVals, 3180 DebugLoc dl, SelectionDAG &DAG) const { 3181 3182 // CCValAssign - represent the assignment of 3183 // the return value to a location 3184 SmallVector<CCValAssign, 16> RVLocs; 3185 3186 // CCState - Info about the registers and stack slot. 3187 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 3188 getTargetMachine(), RVLocs, *DAG.getContext()); 3189 3190 // Analize return values. 3191 CCInfo.AnalyzeReturn(Outs, RetCC_Mips); 3192 3193 // If this is the first return lowered for this function, add 3194 // the regs to the liveout set for the function. 3195 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 3196 for (unsigned i = 0; i != RVLocs.size(); ++i) 3197 if (RVLocs[i].isRegLoc()) 3198 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 3199 } 3200 3201 SDValue Flag; 3202 3203 // Copy the result values into the output registers. 3204 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3205 CCValAssign &VA = RVLocs[i]; 3206 assert(VA.isRegLoc() && "Can only return in registers!"); 3207 3208 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); 3209 3210 // guarantee that all emitted copies are 3211 // stuck together, avoiding something bad 3212 Flag = Chain.getValue(1); 3213 } 3214 3215 // The mips ABIs for returning structs by value requires that we copy 3216 // the sret argument into $v0 for the return. We saved the argument into 3217 // a virtual register in the entry block, so now we copy the value out 3218 // and into $v0. 3219 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 3220 MachineFunction &MF = DAG.getMachineFunction(); 3221 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3222 unsigned Reg = MipsFI->getSRetReturnReg(); 3223 3224 if (!Reg) 3225 llvm_unreachable("sret virtual register not created in the entry block"); 3226 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 3227 3228 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag); 3229 Flag = Chain.getValue(1); 3230 } 3231 3232 // Return on Mips is always a "jr $ra" 3233 if (Flag.getNode()) 3234 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, Chain, Flag); 3235 3236 // Return Void 3237 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, Chain); 3238} 3239 3240//===----------------------------------------------------------------------===// 3241// Mips Inline Assembly Support 3242//===----------------------------------------------------------------------===// 3243 3244/// getConstraintType - Given a constraint letter, return the type of 3245/// constraint it is for this target. 3246MipsTargetLowering::ConstraintType MipsTargetLowering:: 3247getConstraintType(const std::string &Constraint) const 3248{ 3249 // Mips specific constrainy 3250 // GCC config/mips/constraints.md 3251 // 3252 // 'd' : An address register. Equivalent to r 3253 // unless generating MIPS16 code. 3254 // 'y' : Equivalent to r; retained for 3255 // backwards compatibility. 3256 // 'c' : A register suitable for use in an indirect 3257 // jump. This will always be $25 for -mabicalls. 3258 // 'l' : The lo register. 1 word storage. 3259 // 'x' : The hilo register pair. Double word storage. 3260 if (Constraint.size() == 1) { 3261 switch (Constraint[0]) { 3262 default : break; 3263 case 'd': 3264 case 'y': 3265 case 'f': 3266 case 'c': 3267 case 'l': 3268 case 'x': 3269 return C_RegisterClass; 3270 } 3271 } 3272 return TargetLowering::getConstraintType(Constraint); 3273} 3274 3275/// Examine constraint type and operand type and determine a weight value. 3276/// This object must already have been set up with the operand type 3277/// and the current alternative constraint selected. 3278TargetLowering::ConstraintWeight 3279MipsTargetLowering::getSingleConstraintMatchWeight( 3280 AsmOperandInfo &info, const char *constraint) const { 3281 ConstraintWeight weight = CW_Invalid; 3282 Value *CallOperandVal = info.CallOperandVal; 3283 // If we don't have a value, we can't do a match, 3284 // but allow it at the lowest weight. 3285 if (CallOperandVal == NULL) 3286 return CW_Default; 3287 Type *type = CallOperandVal->getType(); 3288 // Look at the constraint type. 3289 switch (*constraint) { 3290 default: 3291 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 3292 break; 3293 case 'd': 3294 case 'y': 3295 if (type->isIntegerTy()) 3296 weight = CW_Register; 3297 break; 3298 case 'f': 3299 if (type->isFloatTy()) 3300 weight = CW_Register; 3301 break; 3302 case 'c': // $25 for indirect jumps 3303 case 'l': // lo register 3304 case 'x': // hilo register pair 3305 if (type->isIntegerTy()) 3306 weight = CW_SpecificReg; 3307 break; 3308 case 'I': // signed 16 bit immediate 3309 case 'J': // integer zero 3310 case 'K': // unsigned 16 bit immediate 3311 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3312 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3313 case 'O': // signed 15 bit immediate (+- 16383) 3314 case 'P': // immediate in the range of 65535 to 1 (inclusive) 3315 if (isa<ConstantInt>(CallOperandVal)) 3316 weight = CW_Constant; 3317 break; 3318 } 3319 return weight; 3320} 3321 3322/// Given a register class constraint, like 'r', if this corresponds directly 3323/// to an LLVM register class, return a register of 0 and the register class 3324/// pointer. 3325std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering:: 3326getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const 3327{ 3328 if (Constraint.size() == 1) { 3329 switch (Constraint[0]) { 3330 case 'd': // Address register. Same as 'r' unless generating MIPS16 code. 3331 case 'y': // Same as 'r'. Exists for compatibility. 3332 case 'r': 3333 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { 3334 if (Subtarget->inMips16Mode()) 3335 return std::make_pair(0U, &Mips::CPU16RegsRegClass); 3336 return std::make_pair(0U, &Mips::CPURegsRegClass); 3337 } 3338 if (VT == MVT::i64 && !HasMips64) 3339 return std::make_pair(0U, &Mips::CPURegsRegClass); 3340 if (VT == MVT::i64 && HasMips64) 3341 return std::make_pair(0U, &Mips::CPU64RegsRegClass); 3342 // This will generate an error message 3343 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 3344 case 'f': 3345 if (VT == MVT::f32) 3346 return std::make_pair(0U, &Mips::FGR32RegClass); 3347 if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) { 3348 if (Subtarget->isFP64bit()) 3349 return std::make_pair(0U, &Mips::FGR64RegClass); 3350 return std::make_pair(0U, &Mips::AFGR64RegClass); 3351 } 3352 break; 3353 case 'c': // register suitable for indirect jump 3354 if (VT == MVT::i32) 3355 return std::make_pair((unsigned)Mips::T9, &Mips::CPURegsRegClass); 3356 assert(VT == MVT::i64 && "Unexpected type."); 3357 return std::make_pair((unsigned)Mips::T9_64, &Mips::CPU64RegsRegClass); 3358 case 'l': // register suitable for indirect jump 3359 if (VT == MVT::i32) 3360 return std::make_pair((unsigned)Mips::LO, &Mips::HILORegClass); 3361 return std::make_pair((unsigned)Mips::LO64, &Mips::HILO64RegClass); 3362 case 'x': // register suitable for indirect jump 3363 // Fixme: Not triggering the use of both hi and low 3364 // This will generate an error message 3365 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 3366 } 3367 } 3368 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 3369} 3370 3371/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 3372/// vector. If it is invalid, don't add anything to Ops. 3373void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 3374 std::string &Constraint, 3375 std::vector<SDValue>&Ops, 3376 SelectionDAG &DAG) const { 3377 SDValue Result(0, 0); 3378 3379 // Only support length 1 constraints for now. 3380 if (Constraint.length() > 1) return; 3381 3382 char ConstraintLetter = Constraint[0]; 3383 switch (ConstraintLetter) { 3384 default: break; // This will fall through to the generic implementation 3385 case 'I': // Signed 16 bit constant 3386 // If this fails, the parent routine will give an error 3387 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3388 EVT Type = Op.getValueType(); 3389 int64_t Val = C->getSExtValue(); 3390 if (isInt<16>(Val)) { 3391 Result = DAG.getTargetConstant(Val, Type); 3392 break; 3393 } 3394 } 3395 return; 3396 case 'J': // integer zero 3397 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3398 EVT Type = Op.getValueType(); 3399 int64_t Val = C->getZExtValue(); 3400 if (Val == 0) { 3401 Result = DAG.getTargetConstant(0, Type); 3402 break; 3403 } 3404 } 3405 return; 3406 case 'K': // unsigned 16 bit immediate 3407 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3408 EVT Type = Op.getValueType(); 3409 uint64_t Val = (uint64_t)C->getZExtValue(); 3410 if (isUInt<16>(Val)) { 3411 Result = DAG.getTargetConstant(Val, Type); 3412 break; 3413 } 3414 } 3415 return; 3416 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3417 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3418 EVT Type = Op.getValueType(); 3419 int64_t Val = C->getSExtValue(); 3420 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){ 3421 Result = DAG.getTargetConstant(Val, Type); 3422 break; 3423 } 3424 } 3425 return; 3426 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3427 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3428 EVT Type = Op.getValueType(); 3429 int64_t Val = C->getSExtValue(); 3430 if ((Val >= -65535) && (Val <= -1)) { 3431 Result = DAG.getTargetConstant(Val, Type); 3432 break; 3433 } 3434 } 3435 return; 3436 case 'O': // signed 15 bit immediate 3437 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3438 EVT Type = Op.getValueType(); 3439 int64_t Val = C->getSExtValue(); 3440 if ((isInt<15>(Val))) { 3441 Result = DAG.getTargetConstant(Val, Type); 3442 break; 3443 } 3444 } 3445 return; 3446 case 'P': // immediate in the range of 1 to 65535 (inclusive) 3447 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3448 EVT Type = Op.getValueType(); 3449 int64_t Val = C->getSExtValue(); 3450 if ((Val <= 65535) && (Val >= 1)) { 3451 Result = DAG.getTargetConstant(Val, Type); 3452 break; 3453 } 3454 } 3455 return; 3456 } 3457 3458 if (Result.getNode()) { 3459 Ops.push_back(Result); 3460 return; 3461 } 3462 3463 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 3464} 3465 3466bool 3467MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 3468 // The Mips target isn't yet aware of offsets. 3469 return false; 3470} 3471 3472EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 3473 unsigned SrcAlign, bool IsZeroVal, 3474 bool MemcpyStrSrc, 3475 MachineFunction &MF) const { 3476 if (Subtarget->hasMips64()) 3477 return MVT::i64; 3478 3479 return MVT::i32; 3480} 3481 3482bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3483 if (VT != MVT::f32 && VT != MVT::f64) 3484 return false; 3485 if (Imm.isNegZero()) 3486 return false; 3487 return Imm.isZero(); 3488} 3489 3490unsigned MipsTargetLowering::getJumpTableEncoding() const { 3491 if (IsN64) 3492 return MachineJumpTableInfo::EK_GPRel64BlockAddress; 3493 3494 return TargetLowering::getJumpTableEncoding(); 3495} 3496