MipsISelLowering.h revision 01f7089bca51744226306e09db4954e3df02b3be 
1//===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that Mips uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef MipsISELLOWERING_H
16#define MipsISELLOWERING_H
17
18#include "Mips.h"
19#include "MipsSubtarget.h"
20#include "llvm/CodeGen/SelectionDAG.h"
21#include "llvm/Target/TargetLowering.h"
22
23namespace llvm {
24  namespace MipsISD {
25    enum NodeType {
26      // Start the numbering from where ISD NodeType finishes.
27      FIRST_NUMBER = ISD::BUILTIN_OP_END,
28
29      // Jump and link (call)
30      JmpLink,
31
32      // Get the Higher 16 bits from a 32-bit immediate
33      // No relation with Mips Hi register
34      Hi,
35
36      // Get the Lower 16 bits from a 32-bit immediate
37      // No relation with Mips Lo register
38      Lo,
39
40      // Handle gp_rel (small data/bss sections) relocation.
41      GPRel,
42
43      // Thread Pointer
44      ThreadPointer,
45
46      // Floating Point Branch Conditional
47      FPBrcond,
48
49      // Floating Point Compare
50      FPCmp,
51
52      // Floating Point Conditional Moves
53      CMovFP_T,
54      CMovFP_F,
55
56      // Floating Point Rounding
57      FPRound,
58
59      // Return
60      Ret,
61
62      // MAdd/Sub nodes
63      MAdd,
64      MAddu,
65      MSub,
66      MSubu,
67
68      // DivRem(u)
69      DivRem,
70      DivRemU,
71
72      BuildPairF64,
73      ExtractElementF64,
74
75      Wrapper,
76
77      DynAlloc,
78
79      Sync,
80
81      Ext,
82      Ins,
83
84      // EXTR.W instrinsic nodes.
85      EXTP,
86      EXTPDP,
87      EXTR_S_H,
88      EXTR_W,
89      EXTR_R_W,
90      EXTR_RS_W,
91      SHILO,
92      MTHLIP,
93
94      // DPA.W intrinsic nodes.
95      MULSAQ_S_W_PH,
96      MAQ_S_W_PHL,
97      MAQ_S_W_PHR,
98      MAQ_SA_W_PHL,
99      MAQ_SA_W_PHR,
100      DPAU_H_QBL,
101      DPAU_H_QBR,
102      DPSU_H_QBL,
103      DPSU_H_QBR,
104      DPAQ_S_W_PH,
105      DPSQ_S_W_PH,
106      DPAQ_SA_L_W,
107      DPSQ_SA_L_W,
108      DPA_W_PH,
109      DPS_W_PH,
110      DPAQX_S_W_PH,
111      DPAQX_SA_W_PH,
112      DPAX_W_PH,
113      DPSX_W_PH,
114      DPSQX_S_W_PH,
115      DPSQX_SA_W_PH,
116      MULSA_W_PH,
117
118      MULT,
119      MULTU,
120      MADD_DSP,
121      MADDU_DSP,
122      MSUB_DSP,
123      MSUBU_DSP,
124
125      // Load/Store Left/Right nodes.
126      LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
127      LWR,
128      SWL,
129      SWR,
130      LDL,
131      LDR,
132      SDL,
133      SDR
134    };
135  }
136
137  //===--------------------------------------------------------------------===//
138  // TargetLowering Implementation
139  //===--------------------------------------------------------------------===//
140
141  class MipsTargetLowering : public TargetLowering  {
142  public:
143    explicit MipsTargetLowering(MipsTargetMachine &TM);
144
145    virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
146
147    virtual bool allowsUnalignedMemoryAccesses (EVT VT) const;
148
149    virtual void LowerOperationWrapper(SDNode *N,
150                                       SmallVectorImpl<SDValue> &Results,
151                                       SelectionDAG &DAG) const;
152
153    /// LowerOperation - Provide custom lowering hooks for some operations.
154    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
155
156    /// ReplaceNodeResults - Replace the results of node with an illegal result
157    /// type with new values built out of custom code.
158    ///
159    virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
160                                    SelectionDAG &DAG) const;
161
162    /// getTargetNodeName - This method returns the name of a target specific
163    //  DAG node.
164    virtual const char *getTargetNodeName(unsigned Opcode) const;
165
166    /// getSetCCResultType - get the ISD::SETCC result ValueType
167    EVT getSetCCResultType(EVT VT) const;
168
169    virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
170  private:
171    // Subtarget Info
172    const MipsSubtarget *Subtarget;
173
174    bool HasMips64, IsN64, IsO32;
175
176    // Lower Operand helpers
177    SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
178                            CallingConv::ID CallConv, bool isVarArg,
179                            const SmallVectorImpl<ISD::InputArg> &Ins,
180                            DebugLoc dl, SelectionDAG &DAG,
181                            SmallVectorImpl<SDValue> &InVals) const;
182
183    // Lower Operand specifics
184    SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
185    SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
186    SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
187    SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
188    SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
189    SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
190    SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
191    SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
192    SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
193    SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
194    SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
195    SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
196    SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
197    SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
198    SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
199    SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
200    SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
201    SDValue LowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
202                                 bool IsSRA) const;
203    SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
204    SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
205    SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
206    SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
207
208    virtual SDValue
209      LowerFormalArguments(SDValue Chain,
210                           CallingConv::ID CallConv, bool isVarArg,
211                           const SmallVectorImpl<ISD::InputArg> &Ins,
212                           DebugLoc dl, SelectionDAG &DAG,
213                           SmallVectorImpl<SDValue> &InVals) const;
214
215    virtual SDValue
216      LowerCall(TargetLowering::CallLoweringInfo &CLI,
217                SmallVectorImpl<SDValue> &InVals) const;
218
219    virtual SDValue
220      LowerReturn(SDValue Chain,
221                  CallingConv::ID CallConv, bool isVarArg,
222                  const SmallVectorImpl<ISD::OutputArg> &Outs,
223                  const SmallVectorImpl<SDValue> &OutVals,
224                  DebugLoc dl, SelectionDAG &DAG) const;
225
226    virtual MachineBasicBlock *
227      EmitInstrWithCustomInserter(MachineInstr *MI,
228                                  MachineBasicBlock *MBB) const;
229
230    // Inline asm support
231    ConstraintType getConstraintType(const std::string &Constraint) const;
232
233    /// Examine constraint string and operand type and determine a weight value.
234    /// The operand object must already have been set up with the operand type.
235    ConstraintWeight getSingleConstraintMatchWeight(
236      AsmOperandInfo &info, const char *constraint) const;
237
238    std::pair<unsigned, const TargetRegisterClass*>
239              getRegForInlineAsmConstraint(const std::string &Constraint,
240              EVT VT) const;
241
242    /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
243    /// vector.  If it is invalid, don't add anything to Ops. If hasMemory is
244    /// true it means one of the asm constraint of the inline asm instruction
245    /// being processed is 'm'.
246    virtual void LowerAsmOperandForConstraint(SDValue Op,
247                                              std::string &Constraint,
248                                              std::vector<SDValue> &Ops,
249                                              SelectionDAG &DAG) const;
250
251    virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
252
253    virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
254                                    unsigned SrcAlign, bool IsZeroVal,
255                                    bool MemcpyStrSrc,
256                                    MachineFunction &MF) const;
257
258    /// isFPImmLegal - Returns true if the target can instruction select the
259    /// specified FP immediate natively. If false, the legalizer will
260    /// materialize the FP immediate as a load from a constant pool.
261    virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
262
263    virtual unsigned getJumpTableEncoding() const;
264
265    MachineBasicBlock *EmitBPOSGE32(MachineInstr *MI,
266                                    MachineBasicBlock *BB) const;
267    MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
268                    unsigned Size, unsigned BinOpcode, bool Nand = false) const;
269    MachineBasicBlock *EmitAtomicBinaryPartword(MachineInstr *MI,
270                    MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
271                    bool Nand = false) const;
272    MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
273                                  MachineBasicBlock *BB, unsigned Size) const;
274    MachineBasicBlock *EmitAtomicCmpSwapPartword(MachineInstr *MI,
275                                  MachineBasicBlock *BB, unsigned Size) const;
276  };
277}
278
279#endif // MipsISELLOWERING_H
280