MipsISelLowering.h revision 200a7434f6abc1e469fdf1ee547bc3fe4fbfcc02
1//===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that Mips uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef MipsISELLOWERING_H 16#define MipsISELLOWERING_H 17 18#include "Mips.h" 19#include "MipsSubtarget.h" 20#include "MCTargetDesc/MipsBaseInfo.h" 21#include "llvm/CodeGen/CallingConvLower.h" 22#include "llvm/CodeGen/SelectionDAG.h" 23#include "llvm/IR/Function.h" 24#include "llvm/Target/TargetLowering.h" 25#include <deque> 26#include <string> 27 28namespace llvm { 29 namespace MipsISD { 30 enum NodeType { 31 // Start the numbering from where ISD NodeType finishes. 32 FIRST_NUMBER = ISD::BUILTIN_OP_END, 33 34 // Jump and link (call) 35 JmpLink, 36 37 // Tail call 38 TailCall, 39 40 // Get the Higher 16 bits from a 32-bit immediate 41 // No relation with Mips Hi register 42 Hi, 43 44 // Get the Lower 16 bits from a 32-bit immediate 45 // No relation with Mips Lo register 46 Lo, 47 48 // Handle gp_rel (small data/bss sections) relocation. 49 GPRel, 50 51 // Thread Pointer 52 ThreadPointer, 53 54 // Floating Point Branch Conditional 55 FPBrcond, 56 57 // Floating Point Compare 58 FPCmp, 59 60 // Floating Point Conditional Moves 61 CMovFP_T, 62 CMovFP_F, 63 64 // FP-to-int truncation node. 65 TruncIntFP, 66 67 // Return 68 Ret, 69 70 EH_RETURN, 71 72 // Node used to extract integer from accumulator. 73 ExtractLOHI, 74 75 // Node used to insert integers to accumulator. 76 InsertLOHI, 77 78 // Mult nodes. 79 Mult, 80 Multu, 81 82 // MAdd/Sub nodes 83 MAdd, 84 MAddu, 85 MSub, 86 MSubu, 87 88 // DivRem(u) 89 DivRem, 90 DivRemU, 91 DivRem16, 92 DivRemU16, 93 94 BuildPairF64, 95 ExtractElementF64, 96 97 Wrapper, 98 99 DynAlloc, 100 101 Sync, 102 103 Ext, 104 Ins, 105 106 // EXTR.W instrinsic nodes. 107 EXTP, 108 EXTPDP, 109 EXTR_S_H, 110 EXTR_W, 111 EXTR_R_W, 112 EXTR_RS_W, 113 SHILO, 114 MTHLIP, 115 116 // DPA.W intrinsic nodes. 117 MULSAQ_S_W_PH, 118 MAQ_S_W_PHL, 119 MAQ_S_W_PHR, 120 MAQ_SA_W_PHL, 121 MAQ_SA_W_PHR, 122 DPAU_H_QBL, 123 DPAU_H_QBR, 124 DPSU_H_QBL, 125 DPSU_H_QBR, 126 DPAQ_S_W_PH, 127 DPSQ_S_W_PH, 128 DPAQ_SA_L_W, 129 DPSQ_SA_L_W, 130 DPA_W_PH, 131 DPS_W_PH, 132 DPAQX_S_W_PH, 133 DPAQX_SA_W_PH, 134 DPAX_W_PH, 135 DPSX_W_PH, 136 DPSQX_S_W_PH, 137 DPSQX_SA_W_PH, 138 MULSA_W_PH, 139 140 MULT, 141 MULTU, 142 MADD_DSP, 143 MADDU_DSP, 144 MSUB_DSP, 145 MSUBU_DSP, 146 147 // DSP shift nodes. 148 SHLL_DSP, 149 SHRA_DSP, 150 SHRL_DSP, 151 152 // DSP setcc and select_cc nodes. 153 SETCC_DSP, 154 SELECT_CC_DSP, 155 156 // Vector comparisons. 157 // These take a vector and return a boolean. 158 VALL_ZERO, 159 VANY_ZERO, 160 VALL_NONZERO, 161 VANY_NONZERO, 162 163 // These take a vector and return a vector bitmask. 164 VCEQ, 165 VCLE_S, 166 VCLE_U, 167 VCLT_S, 168 VCLT_U, 169 170 // Element-wise vector max/min. 171 VSMAX, 172 VSMIN, 173 VUMAX, 174 VUMIN, 175 176 // Vector Shuffle with mask as an operand 177 VSHF, // Generic shuffle 178 SHF, // 4-element set shuffle. 179 ILVEV, // Interleave even elements 180 ILVOD, // Interleave odd elements 181 ILVL, // Interleave left elements 182 ILVR, // Interleave right elements 183 PCKEV, // Pack even elements 184 PCKOD, // Pack odd elements 185 186 // Combined (XOR (OR $a, $b), -1) 187 VNOR, 188 189 // Extended vector element extraction 190 VEXTRACT_SEXT_ELT, 191 VEXTRACT_ZEXT_ELT, 192 193 // Load/Store Left/Right nodes. 194 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE, 195 LWR, 196 SWL, 197 SWR, 198 LDL, 199 LDR, 200 SDL, 201 SDR 202 }; 203 } 204 205 //===--------------------------------------------------------------------===// 206 // TargetLowering Implementation 207 //===--------------------------------------------------------------------===// 208 class MipsFunctionInfo; 209 210 class MipsTargetLowering : public TargetLowering { 211 public: 212 explicit MipsTargetLowering(MipsTargetMachine &TM); 213 214 static const MipsTargetLowering *create(MipsTargetMachine &TM); 215 216 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; } 217 218 virtual void LowerOperationWrapper(SDNode *N, 219 SmallVectorImpl<SDValue> &Results, 220 SelectionDAG &DAG) const; 221 222 /// LowerOperation - Provide custom lowering hooks for some operations. 223 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 224 225 /// ReplaceNodeResults - Replace the results of node with an illegal result 226 /// type with new values built out of custom code. 227 /// 228 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 229 SelectionDAG &DAG) const; 230 231 /// getTargetNodeName - This method returns the name of a target specific 232 // DAG node. 233 virtual const char *getTargetNodeName(unsigned Opcode) const; 234 235 /// getSetCCResultType - get the ISD::SETCC result ValueType 236 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const; 237 238 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 239 240 virtual MachineBasicBlock * 241 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const; 242 243 struct LTStr { 244 bool operator()(const char *S1, const char *S2) const { 245 return strcmp(S1, S2) < 0; 246 } 247 }; 248 249 protected: 250 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const; 251 252 // This method creates the following nodes, which are necessary for 253 // computing a local symbol's address: 254 // 255 // (add (load (wrapper $gp, %got(sym)), %lo(sym)) 256 template<class NodeTy> 257 SDValue getAddrLocal(NodeTy *N, EVT Ty, SelectionDAG &DAG, 258 bool HasMips64) const { 259 SDLoc DL(N); 260 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT; 261 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty), 262 getTargetNode(N, Ty, DAG, GOTFlag)); 263 SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT, 264 MachinePointerInfo::getGOT(), false, false, 265 false, 0); 266 unsigned LoFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO; 267 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty, 268 getTargetNode(N, Ty, DAG, LoFlag)); 269 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo); 270 } 271 272 // This method creates the following nodes, which are necessary for 273 // computing a global symbol's address: 274 // 275 // (load (wrapper $gp, %got(sym))) 276 template<class NodeTy> 277 SDValue getAddrGlobal(NodeTy *N, EVT Ty, SelectionDAG &DAG, 278 unsigned Flag) const { 279 SDLoc DL(N); 280 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty), 281 getTargetNode(N, Ty, DAG, Flag)); 282 return DAG.getLoad(Ty, DL, DAG.getEntryNode(), Tgt, 283 MachinePointerInfo::getGOT(), false, false, false, 0); 284 } 285 286 // This method creates the following nodes, which are necessary for 287 // computing a global symbol's address in large-GOT mode: 288 // 289 // (load (wrapper (add %hi(sym), $gp), %lo(sym))) 290 template<class NodeTy> 291 SDValue getAddrGlobalLargeGOT(NodeTy *N, EVT Ty, SelectionDAG &DAG, 292 unsigned HiFlag, unsigned LoFlag) const { 293 SDLoc DL(N); 294 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, Ty, 295 getTargetNode(N, Ty, DAG, HiFlag)); 296 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty)); 297 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi, 298 getTargetNode(N, Ty, DAG, LoFlag)); 299 return DAG.getLoad(Ty, DL, DAG.getEntryNode(), Wrapper, 300 MachinePointerInfo::getGOT(), false, false, false, 0); 301 } 302 303 // This method creates the following nodes, which are necessary for 304 // computing a symbol's address in non-PIC mode: 305 // 306 // (add %hi(sym), %lo(sym)) 307 template<class NodeTy> 308 SDValue getAddrNonPIC(NodeTy *N, EVT Ty, SelectionDAG &DAG) const { 309 SDLoc DL(N); 310 SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI); 311 SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO); 312 return DAG.getNode(ISD::ADD, DL, Ty, 313 DAG.getNode(MipsISD::Hi, DL, Ty, Hi), 314 DAG.getNode(MipsISD::Lo, DL, Ty, Lo)); 315 } 316 317 /// This function fills Ops, which is the list of operands that will later 318 /// be used when a function call node is created. It also generates 319 /// copyToReg nodes to set up argument registers. 320 virtual void 321 getOpndList(SmallVectorImpl<SDValue> &Ops, 322 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 323 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 324 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const; 325 326 /// ByValArgInfo - Byval argument information. 327 struct ByValArgInfo { 328 unsigned FirstIdx; // Index of the first register used. 329 unsigned NumRegs; // Number of registers used for this argument. 330 unsigned Address; // Offset of the stack area used to pass this argument. 331 332 ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {} 333 }; 334 335 /// MipsCC - This class provides methods used to analyze formal and call 336 /// arguments and inquire about calling convention information. 337 class MipsCC { 338 public: 339 enum SpecialCallingConvType { 340 Mips16RetHelperConv, NoSpecialCallingConv 341 }; 342 343 MipsCC(CallingConv::ID CallConv, bool IsO32, bool IsFP64, CCState &Info, 344 SpecialCallingConvType SpecialCallingConv = NoSpecialCallingConv); 345 346 347 void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, 348 bool IsVarArg, bool IsSoftFloat, 349 const SDNode *CallNode, 350 std::vector<ArgListEntry> &FuncArgs); 351 void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, 352 bool IsSoftFloat, 353 Function::const_arg_iterator FuncArg); 354 355 void analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, 356 bool IsSoftFloat, const SDNode *CallNode, 357 const Type *RetTy) const; 358 359 void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, 360 bool IsSoftFloat, const Type *RetTy) const; 361 362 const CCState &getCCInfo() const { return CCInfo; } 363 364 /// hasByValArg - Returns true if function has byval arguments. 365 bool hasByValArg() const { return !ByValArgs.empty(); } 366 367 /// regSize - Size (in number of bits) of integer registers. 368 unsigned regSize() const { return IsO32 ? 4 : 8; } 369 370 /// numIntArgRegs - Number of integer registers available for calls. 371 unsigned numIntArgRegs() const; 372 373 /// reservedArgArea - The size of the area the caller reserves for 374 /// register arguments. This is 16-byte if ABI is O32. 375 unsigned reservedArgArea() const; 376 377 /// Return pointer to array of integer argument registers. 378 const uint16_t *intArgRegs() const; 379 380 typedef SmallVectorImpl<ByValArgInfo>::const_iterator byval_iterator; 381 byval_iterator byval_begin() const { return ByValArgs.begin(); } 382 byval_iterator byval_end() const { return ByValArgs.end(); } 383 384 private: 385 void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT, 386 CCValAssign::LocInfo LocInfo, 387 ISD::ArgFlagsTy ArgFlags); 388 389 /// useRegsForByval - Returns true if the calling convention allows the 390 /// use of registers to pass byval arguments. 391 bool useRegsForByval() const { return CallConv != CallingConv::Fast; } 392 393 /// Return the function that analyzes fixed argument list functions. 394 llvm::CCAssignFn *fixedArgFn() const; 395 396 /// Return the function that analyzes variable argument list functions. 397 llvm::CCAssignFn *varArgFn() const; 398 399 const uint16_t *shadowRegs() const; 400 401 void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize, 402 unsigned Align); 403 404 /// Return the type of the register which is used to pass an argument or 405 /// return a value. This function returns f64 if the argument is an i64 406 /// value which has been generated as a result of softening an f128 value. 407 /// Otherwise, it just returns VT. 408 MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode, 409 bool IsSoftFloat) const; 410 411 template<typename Ty> 412 void analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat, 413 const SDNode *CallNode, const Type *RetTy) const; 414 415 CCState &CCInfo; 416 CallingConv::ID CallConv; 417 bool IsO32, IsFP64; 418 SpecialCallingConvType SpecialCallingConv; 419 SmallVector<ByValArgInfo, 2> ByValArgs; 420 }; 421 protected: 422 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const; 423 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const; 424 425 // Subtarget Info 426 const MipsSubtarget *Subtarget; 427 428 bool HasMips64, IsN64, IsO32; 429 430 private: 431 // Create a TargetGlobalAddress node. 432 SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG, 433 unsigned Flag) const; 434 435 // Create a TargetExternalSymbol node. 436 SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG, 437 unsigned Flag) const; 438 439 // Create a TargetBlockAddress node. 440 SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG, 441 unsigned Flag) const; 442 443 // Create a TargetJumpTable node. 444 SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG, 445 unsigned Flag) const; 446 447 // Create a TargetConstantPool node. 448 SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG, 449 unsigned Flag) const; 450 451 MipsCC::SpecialCallingConvType getSpecialCallingConv(SDValue Callee) const; 452 // Lower Operand helpers 453 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 454 CallingConv::ID CallConv, bool isVarArg, 455 const SmallVectorImpl<ISD::InputArg> &Ins, 456 SDLoc dl, SelectionDAG &DAG, 457 SmallVectorImpl<SDValue> &InVals, 458 const SDNode *CallNode, const Type *RetTy) const; 459 460 // Lower Operand specifics 461 SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 462 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 463 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 464 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 465 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 466 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 467 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 468 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const; 469 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 470 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const; 471 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const; 472 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 473 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const; 474 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 475 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 476 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const; 477 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const; 478 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const; 479 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG, 480 bool IsSRA) const; 481 SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const; 482 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const; 483 484 /// isEligibleForTailCallOptimization - Check whether the call is eligible 485 /// for tail call optimization. 486 virtual bool 487 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo, 488 unsigned NextStackOffset, 489 const MipsFunctionInfo& FI) const = 0; 490 491 /// copyByValArg - Copy argument registers which were used to pass a byval 492 /// argument to the stack. Create a stack frame object for the byval 493 /// argument. 494 void copyByValRegs(SDValue Chain, SDLoc DL, 495 std::vector<SDValue> &OutChains, SelectionDAG &DAG, 496 const ISD::ArgFlagsTy &Flags, 497 SmallVectorImpl<SDValue> &InVals, 498 const Argument *FuncArg, 499 const MipsCC &CC, const ByValArgInfo &ByVal) const; 500 501 /// passByValArg - Pass a byval argument in registers or on stack. 502 void passByValArg(SDValue Chain, SDLoc DL, 503 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 504 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, 505 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, 506 const MipsCC &CC, const ByValArgInfo &ByVal, 507 const ISD::ArgFlagsTy &Flags, bool isLittle) const; 508 509 /// writeVarArgRegs - Write variable function arguments passed in registers 510 /// to the stack. Also create a stack frame object for the first variable 511 /// argument. 512 void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC, 513 SDValue Chain, SDLoc DL, SelectionDAG &DAG) const; 514 515 virtual SDValue 516 LowerFormalArguments(SDValue Chain, 517 CallingConv::ID CallConv, bool isVarArg, 518 const SmallVectorImpl<ISD::InputArg> &Ins, 519 SDLoc dl, SelectionDAG &DAG, 520 SmallVectorImpl<SDValue> &InVals) const; 521 522 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain, 523 SDValue Arg, SDLoc DL, bool IsTailCall, 524 SelectionDAG &DAG) const; 525 526 virtual SDValue 527 LowerCall(TargetLowering::CallLoweringInfo &CLI, 528 SmallVectorImpl<SDValue> &InVals) const; 529 530 virtual bool 531 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 532 bool isVarArg, 533 const SmallVectorImpl<ISD::OutputArg> &Outs, 534 LLVMContext &Context) const; 535 536 virtual SDValue 537 LowerReturn(SDValue Chain, 538 CallingConv::ID CallConv, bool isVarArg, 539 const SmallVectorImpl<ISD::OutputArg> &Outs, 540 const SmallVectorImpl<SDValue> &OutVals, 541 SDLoc dl, SelectionDAG &DAG) const; 542 543 // Inline asm support 544 ConstraintType getConstraintType(const std::string &Constraint) const; 545 546 /// Examine constraint string and operand type and determine a weight value. 547 /// The operand object must already have been set up with the operand type. 548 ConstraintWeight getSingleConstraintMatchWeight( 549 AsmOperandInfo &info, const char *constraint) const; 550 551 /// This function parses registers that appear in inline-asm constraints. 552 /// It returns pair (0, 0) on failure. 553 std::pair<unsigned, const TargetRegisterClass *> 554 parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const; 555 556 std::pair<unsigned, const TargetRegisterClass*> 557 getRegForInlineAsmConstraint(const std::string &Constraint, 558 MVT VT) const; 559 560 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 561 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 562 /// true it means one of the asm constraint of the inline asm instruction 563 /// being processed is 'm'. 564 virtual void LowerAsmOperandForConstraint(SDValue Op, 565 std::string &Constraint, 566 std::vector<SDValue> &Ops, 567 SelectionDAG &DAG) const; 568 569 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const; 570 571 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 572 573 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 574 unsigned SrcAlign, 575 bool IsMemset, bool ZeroMemset, 576 bool MemcpyStrSrc, 577 MachineFunction &MF) const; 578 579 /// isFPImmLegal - Returns true if the target can instruction select the 580 /// specified FP immediate natively. If false, the legalizer will 581 /// materialize the FP immediate as a load from a constant pool. 582 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; 583 584 virtual unsigned getJumpTableEncoding() const; 585 586 MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 587 unsigned Size, unsigned BinOpcode, bool Nand = false) const; 588 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI, 589 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode, 590 bool Nand = false) const; 591 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI, 592 MachineBasicBlock *BB, unsigned Size) const; 593 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI, 594 MachineBasicBlock *BB, unsigned Size) const; 595 }; 596 597 /// Create MipsTargetLowering objects. 598 const MipsTargetLowering *createMips16TargetLowering(MipsTargetMachine &TM); 599 const MipsTargetLowering *createMipsSETargetLowering(MipsTargetMachine &TM); 600} 601 602#endif // MipsISELLOWERING_H 603