MipsISelLowering.h revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338 
1//===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that Mips uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef MipsISELLOWERING_H
16#define MipsISELLOWERING_H
17
18#include "MCTargetDesc/MipsBaseInfo.h"
19#include "Mips.h"
20#include "MipsSubtarget.h"
21#include "llvm/CodeGen/CallingConvLower.h"
22#include "llvm/CodeGen/SelectionDAG.h"
23#include "llvm/IR/Function.h"
24#include "llvm/Target/TargetLowering.h"
25#include <deque>
26#include <string>
27
28namespace llvm {
29  namespace MipsISD {
30    enum NodeType {
31      // Start the numbering from where ISD NodeType finishes.
32      FIRST_NUMBER = ISD::BUILTIN_OP_END,
33
34      // Jump and link (call)
35      JmpLink,
36
37      // Tail call
38      TailCall,
39
40      // Get the Higher 16 bits from a 32-bit immediate
41      // No relation with Mips Hi register
42      Hi,
43
44      // Get the Lower 16 bits from a 32-bit immediate
45      // No relation with Mips Lo register
46      Lo,
47
48      // Handle gp_rel (small data/bss sections) relocation.
49      GPRel,
50
51      // Thread Pointer
52      ThreadPointer,
53
54      // Floating Point Branch Conditional
55      FPBrcond,
56
57      // Floating Point Compare
58      FPCmp,
59
60      // Floating Point Conditional Moves
61      CMovFP_T,
62      CMovFP_F,
63
64      // FP-to-int truncation node.
65      TruncIntFP,
66
67      // Return
68      Ret,
69
70      EH_RETURN,
71
72      // Node used to extract integer from accumulator.
73      MFHI,
74      MFLO,
75
76      // Node used to insert integers to accumulator.
77      MTLOHI,
78
79      // Mult nodes.
80      Mult,
81      Multu,
82
83      // MAdd/Sub nodes
84      MAdd,
85      MAddu,
86      MSub,
87      MSubu,
88
89      // DivRem(u)
90      DivRem,
91      DivRemU,
92      DivRem16,
93      DivRemU16,
94
95      BuildPairF64,
96      ExtractElementF64,
97
98      Wrapper,
99
100      DynAlloc,
101
102      Sync,
103
104      Ext,
105      Ins,
106
107      // EXTR.W instrinsic nodes.
108      EXTP,
109      EXTPDP,
110      EXTR_S_H,
111      EXTR_W,
112      EXTR_R_W,
113      EXTR_RS_W,
114      SHILO,
115      MTHLIP,
116
117      // DPA.W intrinsic nodes.
118      MULSAQ_S_W_PH,
119      MAQ_S_W_PHL,
120      MAQ_S_W_PHR,
121      MAQ_SA_W_PHL,
122      MAQ_SA_W_PHR,
123      DPAU_H_QBL,
124      DPAU_H_QBR,
125      DPSU_H_QBL,
126      DPSU_H_QBR,
127      DPAQ_S_W_PH,
128      DPSQ_S_W_PH,
129      DPAQ_SA_L_W,
130      DPSQ_SA_L_W,
131      DPA_W_PH,
132      DPS_W_PH,
133      DPAQX_S_W_PH,
134      DPAQX_SA_W_PH,
135      DPAX_W_PH,
136      DPSX_W_PH,
137      DPSQX_S_W_PH,
138      DPSQX_SA_W_PH,
139      MULSA_W_PH,
140
141      MULT,
142      MULTU,
143      MADD_DSP,
144      MADDU_DSP,
145      MSUB_DSP,
146      MSUBU_DSP,
147
148      // DSP shift nodes.
149      SHLL_DSP,
150      SHRA_DSP,
151      SHRL_DSP,
152
153      // DSP setcc and select_cc nodes.
154      SETCC_DSP,
155      SELECT_CC_DSP,
156
157      // Vector comparisons.
158      // These take a vector and return a boolean.
159      VALL_ZERO,
160      VANY_ZERO,
161      VALL_NONZERO,
162      VANY_NONZERO,
163
164      // These take a vector and return a vector bitmask.
165      VCEQ,
166      VCLE_S,
167      VCLE_U,
168      VCLT_S,
169      VCLT_U,
170
171      // Element-wise vector max/min.
172      VSMAX,
173      VSMIN,
174      VUMAX,
175      VUMIN,
176
177      // Vector Shuffle with mask as an operand
178      VSHF,  // Generic shuffle
179      SHF,   // 4-element set shuffle.
180      ILVEV, // Interleave even elements
181      ILVOD, // Interleave odd elements
182      ILVL,  // Interleave left elements
183      ILVR,  // Interleave right elements
184      PCKEV, // Pack even elements
185      PCKOD, // Pack odd elements
186
187      // Vector Lane Copy
188      INSVE, // Copy element from one vector to another
189
190      // Combined (XOR (OR $a, $b), -1)
191      VNOR,
192
193      // Extended vector element extraction
194      VEXTRACT_SEXT_ELT,
195      VEXTRACT_ZEXT_ELT,
196
197      // Load/Store Left/Right nodes.
198      LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
199      LWR,
200      SWL,
201      SWR,
202      LDL,
203      LDR,
204      SDL,
205      SDR
206    };
207  }
208
209  //===--------------------------------------------------------------------===//
210  // TargetLowering Implementation
211  //===--------------------------------------------------------------------===//
212  class MipsFunctionInfo;
213
214  class MipsTargetLowering : public TargetLowering  {
215    bool isMicroMips;
216  public:
217    explicit MipsTargetLowering(MipsTargetMachine &TM);
218
219    static const MipsTargetLowering *create(MipsTargetMachine &TM);
220
221    virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
222
223    virtual void LowerOperationWrapper(SDNode *N,
224                                       SmallVectorImpl<SDValue> &Results,
225                                       SelectionDAG &DAG) const;
226
227    /// LowerOperation - Provide custom lowering hooks for some operations.
228    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
229
230    /// ReplaceNodeResults - Replace the results of node with an illegal result
231    /// type with new values built out of custom code.
232    ///
233    virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
234                                    SelectionDAG &DAG) const;
235
236    /// getTargetNodeName - This method returns the name of a target specific
237    //  DAG node.
238    virtual const char *getTargetNodeName(unsigned Opcode) const;
239
240    /// getSetCCResultType - get the ISD::SETCC result ValueType
241    EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
242
243    virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
244
245    virtual MachineBasicBlock *
246    EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
247
248    struct LTStr {
249      bool operator()(const char *S1, const char *S2) const {
250        return strcmp(S1, S2) < 0;
251      }
252    };
253
254  protected:
255    SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
256
257    // This method creates the following nodes, which are necessary for
258    // computing a local symbol's address:
259    //
260    // (add (load (wrapper $gp, %got(sym)), %lo(sym))
261    template <class NodeTy>
262    SDValue getAddrLocal(NodeTy *N, EVT Ty, SelectionDAG &DAG,
263                         bool IsN32OrN64) const {
264      SDLoc DL(N);
265      unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
266      SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
267                                getTargetNode(N, Ty, DAG, GOTFlag));
268      SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
269                                 MachinePointerInfo::getGOT(), false, false,
270                                 false, 0);
271      unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
272      SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
273                               getTargetNode(N, Ty, DAG, LoFlag));
274      return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
275    }
276
277    // This method creates the following nodes, which are necessary for
278    // computing a global symbol's address:
279    //
280    // (load (wrapper $gp, %got(sym)))
281    template<class NodeTy>
282    SDValue getAddrGlobal(NodeTy *N, EVT Ty, SelectionDAG &DAG,
283                          unsigned Flag, SDValue Chain,
284                          const MachinePointerInfo &PtrInfo) const {
285      SDLoc DL(N);
286      SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
287                                getTargetNode(N, Ty, DAG, Flag));
288      return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo, false, false, false, 0);
289    }
290
291    // This method creates the following nodes, which are necessary for
292    // computing a global symbol's address in large-GOT mode:
293    //
294    // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
295    template<class NodeTy>
296    SDValue getAddrGlobalLargeGOT(NodeTy *N, EVT Ty, SelectionDAG &DAG,
297                                  unsigned HiFlag, unsigned LoFlag,
298                                  SDValue Chain,
299                                  const MachinePointerInfo &PtrInfo) const {
300      SDLoc DL(N);
301      SDValue Hi = DAG.getNode(MipsISD::Hi, DL, Ty,
302                               getTargetNode(N, Ty, DAG, HiFlag));
303      Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
304      SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
305                                    getTargetNode(N, Ty, DAG, LoFlag));
306      return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo, false, false, false,
307                         0);
308    }
309
310    // This method creates the following nodes, which are necessary for
311    // computing a symbol's address in non-PIC mode:
312    //
313    // (add %hi(sym), %lo(sym))
314    template<class NodeTy>
315    SDValue getAddrNonPIC(NodeTy *N, EVT Ty, SelectionDAG &DAG) const {
316      SDLoc DL(N);
317      SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
318      SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
319      return DAG.getNode(ISD::ADD, DL, Ty,
320                         DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
321                         DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
322    }
323
324    /// This function fills Ops, which is the list of operands that will later
325    /// be used when a function call node is created. It also generates
326    /// copyToReg nodes to set up argument registers.
327    virtual void
328    getOpndList(SmallVectorImpl<SDValue> &Ops,
329                std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
330                bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
331                CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
332
333    /// ByValArgInfo - Byval argument information.
334    struct ByValArgInfo {
335      unsigned FirstIdx; // Index of the first register used.
336      unsigned NumRegs;  // Number of registers used for this argument.
337      unsigned Address;  // Offset of the stack area used to pass this argument.
338
339      ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
340    };
341
342    /// MipsCC - This class provides methods used to analyze formal and call
343    /// arguments and inquire about calling convention information.
344    class MipsCC {
345    public:
346      enum SpecialCallingConvType {
347        Mips16RetHelperConv, NoSpecialCallingConv
348      };
349
350      MipsCC(CallingConv::ID CallConv, bool IsO32, bool IsFP64, CCState &Info,
351             SpecialCallingConvType SpecialCallingConv = NoSpecialCallingConv);
352
353
354      void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
355                               bool IsVarArg, bool IsSoftFloat,
356                               const SDNode *CallNode,
357                               std::vector<ArgListEntry> &FuncArgs);
358      void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
359                                  bool IsSoftFloat,
360                                  Function::const_arg_iterator FuncArg);
361
362      void analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
363                             bool IsSoftFloat, const SDNode *CallNode,
364                             const Type *RetTy) const;
365
366      void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
367                         bool IsSoftFloat, const Type *RetTy) const;
368
369      const CCState &getCCInfo() const { return CCInfo; }
370
371      /// hasByValArg - Returns true if function has byval arguments.
372      bool hasByValArg() const { return !ByValArgs.empty(); }
373
374      /// regSize - Size (in number of bits) of integer registers.
375      unsigned regSize() const { return IsO32 ? 4 : 8; }
376
377      /// numIntArgRegs - Number of integer registers available for calls.
378      unsigned numIntArgRegs() const;
379
380      /// reservedArgArea - The size of the area the caller reserves for
381      /// register arguments. This is 16-byte if ABI is O32.
382      unsigned reservedArgArea() const;
383
384      /// Return pointer to array of integer argument registers.
385      const uint16_t *intArgRegs() const;
386
387      typedef SmallVectorImpl<ByValArgInfo>::const_iterator byval_iterator;
388      byval_iterator byval_begin() const { return ByValArgs.begin(); }
389      byval_iterator byval_end() const { return ByValArgs.end(); }
390
391    private:
392      void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
393                          CCValAssign::LocInfo LocInfo,
394                          ISD::ArgFlagsTy ArgFlags);
395
396      /// useRegsForByval - Returns true if the calling convention allows the
397      /// use of registers to pass byval arguments.
398      bool useRegsForByval() const { return CallConv != CallingConv::Fast; }
399
400      /// Return the function that analyzes fixed argument list functions.
401      llvm::CCAssignFn *fixedArgFn() const;
402
403      /// Return the function that analyzes variable argument list functions.
404      llvm::CCAssignFn *varArgFn() const;
405
406      const uint16_t *shadowRegs() const;
407
408      void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
409                        unsigned Align);
410
411      /// Return the type of the register which is used to pass an argument or
412      /// return a value. This function returns f64 if the argument is an i64
413      /// value which has been generated as a result of softening an f128 value.
414      /// Otherwise, it just returns VT.
415      MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode,
416                   bool IsSoftFloat) const;
417
418      template<typename Ty>
419      void analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat,
420                         const SDNode *CallNode, const Type *RetTy) const;
421
422      CCState &CCInfo;
423      CallingConv::ID CallConv;
424      bool IsO32, IsFP64;
425      SpecialCallingConvType SpecialCallingConv;
426      SmallVector<ByValArgInfo, 2> ByValArgs;
427    };
428  protected:
429    SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
430    SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
431
432    // Subtarget Info
433    const MipsSubtarget *Subtarget;
434
435    bool hasMips64() const { return Subtarget->hasMips64(); }
436    bool isGP64bit() const { return Subtarget->isGP64bit(); }
437    bool isO32() const { return Subtarget->isABI_O32(); }
438    bool isN32() const { return Subtarget->isABI_N32(); }
439    bool isN64() const { return Subtarget->isABI_N64(); }
440
441  private:
442    // Create a TargetGlobalAddress node.
443    SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
444                          unsigned Flag) const;
445
446    // Create a TargetExternalSymbol node.
447    SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG,
448                          unsigned Flag) const;
449
450    // Create a TargetBlockAddress node.
451    SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
452                          unsigned Flag) const;
453
454    // Create a TargetJumpTable node.
455    SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
456                          unsigned Flag) const;
457
458    // Create a TargetConstantPool node.
459    SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
460                          unsigned Flag) const;
461
462    MipsCC::SpecialCallingConvType getSpecialCallingConv(SDValue Callee) const;
463    // Lower Operand helpers
464    SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
465                            CallingConv::ID CallConv, bool isVarArg,
466                            const SmallVectorImpl<ISD::InputArg> &Ins,
467                            SDLoc dl, SelectionDAG &DAG,
468                            SmallVectorImpl<SDValue> &InVals,
469                            const SDNode *CallNode, const Type *RetTy) const;
470
471    // Lower Operand specifics
472    SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
473    SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
474    SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
475    SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
476    SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
477    SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
478    SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
479    SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
480    SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
481    SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
482    SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
483    SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
484    SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
485    SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
486    SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
487    SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
488    SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
489    SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
490    SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
491                                 bool IsSRA) const;
492    SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
493    SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
494
495    /// isEligibleForTailCallOptimization - Check whether the call is eligible
496    /// for tail call optimization.
497    virtual bool
498    isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
499                                      unsigned NextStackOffset,
500                                      const MipsFunctionInfo& FI) const = 0;
501
502    /// copyByValArg - Copy argument registers which were used to pass a byval
503    /// argument to the stack. Create a stack frame object for the byval
504    /// argument.
505    void copyByValRegs(SDValue Chain, SDLoc DL,
506                       std::vector<SDValue> &OutChains, SelectionDAG &DAG,
507                       const ISD::ArgFlagsTy &Flags,
508                       SmallVectorImpl<SDValue> &InVals,
509                       const Argument *FuncArg,
510                       const MipsCC &CC, const ByValArgInfo &ByVal) const;
511
512    /// passByValArg - Pass a byval argument in registers or on stack.
513    void passByValArg(SDValue Chain, SDLoc DL,
514                      std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
515                      SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
516                      MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
517                      const MipsCC &CC, const ByValArgInfo &ByVal,
518                      const ISD::ArgFlagsTy &Flags, bool isLittle) const;
519
520    /// writeVarArgRegs - Write variable function arguments passed in registers
521    /// to the stack. Also create a stack frame object for the first variable
522    /// argument.
523    void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
524                         SDValue Chain, SDLoc DL, SelectionDAG &DAG) const;
525
526    virtual SDValue
527      LowerFormalArguments(SDValue Chain,
528                           CallingConv::ID CallConv, bool isVarArg,
529                           const SmallVectorImpl<ISD::InputArg> &Ins,
530                           SDLoc dl, SelectionDAG &DAG,
531                           SmallVectorImpl<SDValue> &InVals) const;
532
533    SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
534                           SDValue Arg, SDLoc DL, bool IsTailCall,
535                           SelectionDAG &DAG) const;
536
537    virtual SDValue
538      LowerCall(TargetLowering::CallLoweringInfo &CLI,
539                SmallVectorImpl<SDValue> &InVals) const;
540
541    virtual bool
542      CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
543                     bool isVarArg,
544                     const SmallVectorImpl<ISD::OutputArg> &Outs,
545                     LLVMContext &Context) const;
546
547    virtual SDValue
548      LowerReturn(SDValue Chain,
549                  CallingConv::ID CallConv, bool isVarArg,
550                  const SmallVectorImpl<ISD::OutputArg> &Outs,
551                  const SmallVectorImpl<SDValue> &OutVals,
552                  SDLoc dl, SelectionDAG &DAG) const;
553
554    // Inline asm support
555    ConstraintType getConstraintType(const std::string &Constraint) const;
556
557    /// Examine constraint string and operand type and determine a weight value.
558    /// The operand object must already have been set up with the operand type.
559    ConstraintWeight getSingleConstraintMatchWeight(
560      AsmOperandInfo &info, const char *constraint) const;
561
562    /// This function parses registers that appear in inline-asm constraints.
563    /// It returns pair (0, 0) on failure.
564    std::pair<unsigned, const TargetRegisterClass *>
565    parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const;
566
567    std::pair<unsigned, const TargetRegisterClass*>
568              getRegForInlineAsmConstraint(const std::string &Constraint,
569                                           MVT VT) const;
570
571    /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
572    /// vector.  If it is invalid, don't add anything to Ops. If hasMemory is
573    /// true it means one of the asm constraint of the inline asm instruction
574    /// being processed is 'm'.
575    virtual void LowerAsmOperandForConstraint(SDValue Op,
576                                              std::string &Constraint,
577                                              std::vector<SDValue> &Ops,
578                                              SelectionDAG &DAG) const;
579
580    virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
581
582    virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
583
584    virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
585                                    unsigned SrcAlign,
586                                    bool IsMemset, bool ZeroMemset,
587                                    bool MemcpyStrSrc,
588                                    MachineFunction &MF) const;
589
590    /// isFPImmLegal - Returns true if the target can instruction select the
591    /// specified FP immediate natively. If false, the legalizer will
592    /// materialize the FP immediate as a load from a constant pool.
593    virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
594
595    virtual unsigned getJumpTableEncoding() const;
596
597    MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
598                    unsigned Size, unsigned BinOpcode, bool Nand = false) const;
599    MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
600                    MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
601                    bool Nand = false) const;
602    MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
603                                  MachineBasicBlock *BB, unsigned Size) const;
604    MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
605                                  MachineBasicBlock *BB, unsigned Size) const;
606  };
607
608  /// Create MipsTargetLowering objects.
609  const MipsTargetLowering *createMips16TargetLowering(MipsTargetMachine &TM);
610  const MipsTargetLowering *createMipsSETargetLowering(MipsTargetMachine &TM);
611}
612
613#endif // MipsISELLOWERING_H
614