MipsISelLowering.h revision 3706eda52c4565016959902a3f5aaf7271516286 
1//===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that Mips uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef MipsISELLOWERING_H
16#define MipsISELLOWERING_H
17
18#include "Mips.h"
19#include "MipsSubtarget.h"
20#include "llvm/CodeGen/CallingConvLower.h"
21#include "llvm/CodeGen/SelectionDAG.h"
22#include "llvm/IR/Function.h"
23#include "llvm/Target/TargetLowering.h"
24#include <deque>
25#include <string>
26
27namespace llvm {
28  namespace MipsISD {
29    enum NodeType {
30      // Start the numbering from where ISD NodeType finishes.
31      FIRST_NUMBER = ISD::BUILTIN_OP_END,
32
33      // Jump and link (call)
34      JmpLink,
35
36      // Tail call
37      TailCall,
38
39      // Get the Higher 16 bits from a 32-bit immediate
40      // No relation with Mips Hi register
41      Hi,
42
43      // Get the Lower 16 bits from a 32-bit immediate
44      // No relation with Mips Lo register
45      Lo,
46
47      // Handle gp_rel (small data/bss sections) relocation.
48      GPRel,
49
50      // Thread Pointer
51      ThreadPointer,
52
53      // Floating Point Branch Conditional
54      FPBrcond,
55
56      // Floating Point Compare
57      FPCmp,
58
59      // Floating Point Conditional Moves
60      CMovFP_T,
61      CMovFP_F,
62
63      // FP-to-int truncation node.
64      TruncIntFP,
65
66      // Return
67      Ret,
68
69      EH_RETURN,
70
71      // Node used to extract integer from accumulator.
72      ExtractLOHI,
73
74      // Node used to insert integers to accumulator.
75      InsertLOHI,
76
77      // Mult nodes.
78      Mult,
79      Multu,
80
81      // MAdd/Sub nodes
82      MAdd,
83      MAddu,
84      MSub,
85      MSubu,
86
87      // DivRem(u)
88      DivRem,
89      DivRemU,
90      DivRem16,
91      DivRemU16,
92
93      BuildPairF64,
94      ExtractElementF64,
95
96      Wrapper,
97
98      DynAlloc,
99
100      Sync,
101
102      Ext,
103      Ins,
104
105      // EXTR.W instrinsic nodes.
106      EXTP,
107      EXTPDP,
108      EXTR_S_H,
109      EXTR_W,
110      EXTR_R_W,
111      EXTR_RS_W,
112      SHILO,
113      MTHLIP,
114
115      // DPA.W intrinsic nodes.
116      MULSAQ_S_W_PH,
117      MAQ_S_W_PHL,
118      MAQ_S_W_PHR,
119      MAQ_SA_W_PHL,
120      MAQ_SA_W_PHR,
121      DPAU_H_QBL,
122      DPAU_H_QBR,
123      DPSU_H_QBL,
124      DPSU_H_QBR,
125      DPAQ_S_W_PH,
126      DPSQ_S_W_PH,
127      DPAQ_SA_L_W,
128      DPSQ_SA_L_W,
129      DPA_W_PH,
130      DPS_W_PH,
131      DPAQX_S_W_PH,
132      DPAQX_SA_W_PH,
133      DPAX_W_PH,
134      DPSX_W_PH,
135      DPSQX_S_W_PH,
136      DPSQX_SA_W_PH,
137      MULSA_W_PH,
138
139      MULT,
140      MULTU,
141      MADD_DSP,
142      MADDU_DSP,
143      MSUB_DSP,
144      MSUBU_DSP,
145
146      // DSP shift nodes.
147      SHLL_DSP,
148      SHRA_DSP,
149      SHRL_DSP,
150
151      // DSP setcc and select_cc nodes.
152      SETCC_DSP,
153      SELECT_CC_DSP,
154
155      // Vector comparisons.
156      // These take a vector and return a boolean.
157      VALL_ZERO,
158      VANY_ZERO,
159      VALL_NONZERO,
160      VANY_NONZERO,
161
162      // These take a vector and return a vector bitmask.
163      VCEQ,
164      VCLE_S,
165      VCLE_U,
166      VCLT_S,
167      VCLT_U,
168
169      // Element-wise vector max/min.
170      VSMAX,
171      VSMIN,
172      VUMAX,
173      VUMIN,
174
175      // Vector Shuffle with mask as an operand
176      VSHF,  // Generic shuffle
177      SHF,   // 4-element set shuffle.
178      ILVEV, // Interleave even elements
179      ILVOD, // Interleave odd elements
180      ILVL,  // Interleave left elements
181      ILVR,  // Interleave right elements
182      PCKEV, // Pack even elements
183      PCKOD, // Pack odd elements
184
185      // Combined (XOR (OR $a, $b), -1)
186      VNOR,
187
188      // Extended vector element extraction
189      VEXTRACT_SEXT_ELT,
190      VEXTRACT_ZEXT_ELT,
191
192      // Load/Store Left/Right nodes.
193      LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
194      LWR,
195      SWL,
196      SWR,
197      LDL,
198      LDR,
199      SDL,
200      SDR
201    };
202  }
203
204  //===--------------------------------------------------------------------===//
205  // TargetLowering Implementation
206  //===--------------------------------------------------------------------===//
207  class MipsFunctionInfo;
208
209  class MipsTargetLowering : public TargetLowering  {
210  public:
211    explicit MipsTargetLowering(MipsTargetMachine &TM);
212
213    static const MipsTargetLowering *create(MipsTargetMachine &TM);
214
215    virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
216
217    virtual void LowerOperationWrapper(SDNode *N,
218                                       SmallVectorImpl<SDValue> &Results,
219                                       SelectionDAG &DAG) const;
220
221    /// LowerOperation - Provide custom lowering hooks for some operations.
222    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
223
224    /// ReplaceNodeResults - Replace the results of node with an illegal result
225    /// type with new values built out of custom code.
226    ///
227    virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
228                                    SelectionDAG &DAG) const;
229
230    /// getTargetNodeName - This method returns the name of a target specific
231    //  DAG node.
232    virtual const char *getTargetNodeName(unsigned Opcode) const;
233
234    /// getSetCCResultType - get the ISD::SETCC result ValueType
235    EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
236
237    virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
238
239    virtual MachineBasicBlock *
240    EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
241
242    struct LTStr {
243      bool operator()(const char *S1, const char *S2) const {
244        return strcmp(S1, S2) < 0;
245      }
246    };
247
248  protected:
249    SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
250
251    SDValue getAddrLocal(SDValue Op, SelectionDAG &DAG, bool HasMips64) const;
252
253    SDValue getAddrGlobal(SDValue Op, SelectionDAG &DAG, unsigned Flag) const;
254
255    SDValue getAddrGlobalLargeGOT(SDValue Op, SelectionDAG &DAG,
256                                  unsigned HiFlag, unsigned LoFlag) const;
257
258    /// This function fills Ops, which is the list of operands that will later
259    /// be used when a function call node is created. It also generates
260    /// copyToReg nodes to set up argument registers.
261    virtual void
262    getOpndList(SmallVectorImpl<SDValue> &Ops,
263                std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
264                bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
265                CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
266
267    /// ByValArgInfo - Byval argument information.
268    struct ByValArgInfo {
269      unsigned FirstIdx; // Index of the first register used.
270      unsigned NumRegs;  // Number of registers used for this argument.
271      unsigned Address;  // Offset of the stack area used to pass this argument.
272
273      ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
274    };
275
276    /// MipsCC - This class provides methods used to analyze formal and call
277    /// arguments and inquire about calling convention information.
278    class MipsCC {
279    public:
280      enum SpecialCallingConvType {
281        Mips16RetHelperConv, NoSpecialCallingConv
282      };
283
284      MipsCC(CallingConv::ID CallConv, bool IsO32, bool IsFP64, CCState &Info,
285             SpecialCallingConvType SpecialCallingConv = NoSpecialCallingConv);
286
287
288      void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
289                               bool IsVarArg, bool IsSoftFloat,
290                               const SDNode *CallNode,
291                               std::vector<ArgListEntry> &FuncArgs);
292      void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
293                                  bool IsSoftFloat,
294                                  Function::const_arg_iterator FuncArg);
295
296      void analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
297                             bool IsSoftFloat, const SDNode *CallNode,
298                             const Type *RetTy) const;
299
300      void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
301                         bool IsSoftFloat, const Type *RetTy) const;
302
303      const CCState &getCCInfo() const { return CCInfo; }
304
305      /// hasByValArg - Returns true if function has byval arguments.
306      bool hasByValArg() const { return !ByValArgs.empty(); }
307
308      /// regSize - Size (in number of bits) of integer registers.
309      unsigned regSize() const { return IsO32 ? 4 : 8; }
310
311      /// numIntArgRegs - Number of integer registers available for calls.
312      unsigned numIntArgRegs() const;
313
314      /// reservedArgArea - The size of the area the caller reserves for
315      /// register arguments. This is 16-byte if ABI is O32.
316      unsigned reservedArgArea() const;
317
318      /// Return pointer to array of integer argument registers.
319      const uint16_t *intArgRegs() const;
320
321      typedef SmallVectorImpl<ByValArgInfo>::const_iterator byval_iterator;
322      byval_iterator byval_begin() const { return ByValArgs.begin(); }
323      byval_iterator byval_end() const { return ByValArgs.end(); }
324
325    private:
326      void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
327                          CCValAssign::LocInfo LocInfo,
328                          ISD::ArgFlagsTy ArgFlags);
329
330      /// useRegsForByval - Returns true if the calling convention allows the
331      /// use of registers to pass byval arguments.
332      bool useRegsForByval() const { return CallConv != CallingConv::Fast; }
333
334      /// Return the function that analyzes fixed argument list functions.
335      llvm::CCAssignFn *fixedArgFn() const;
336
337      /// Return the function that analyzes variable argument list functions.
338      llvm::CCAssignFn *varArgFn() const;
339
340      const uint16_t *shadowRegs() const;
341
342      void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
343                        unsigned Align);
344
345      /// Return the type of the register which is used to pass an argument or
346      /// return a value. This function returns f64 if the argument is an i64
347      /// value which has been generated as a result of softening an f128 value.
348      /// Otherwise, it just returns VT.
349      MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode,
350                   bool IsSoftFloat) const;
351
352      template<typename Ty>
353      void analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat,
354                         const SDNode *CallNode, const Type *RetTy) const;
355
356      CCState &CCInfo;
357      CallingConv::ID CallConv;
358      bool IsO32, IsFP64;
359      SpecialCallingConvType SpecialCallingConv;
360      SmallVector<ByValArgInfo, 2> ByValArgs;
361    };
362  protected:
363    SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
364    SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
365
366    // Subtarget Info
367    const MipsSubtarget *Subtarget;
368
369    bool HasMips64, IsN64, IsO32;
370
371  private:
372
373    MipsCC::SpecialCallingConvType getSpecialCallingConv(SDValue Callee) const;
374    // Lower Operand helpers
375    SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
376                            CallingConv::ID CallConv, bool isVarArg,
377                            const SmallVectorImpl<ISD::InputArg> &Ins,
378                            SDLoc dl, SelectionDAG &DAG,
379                            SmallVectorImpl<SDValue> &InVals,
380                            const SDNode *CallNode, const Type *RetTy) const;
381
382    // Lower Operand specifics
383    SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
384    SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
385    SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
386    SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
387    SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
388    SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
389    SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
390    SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
391    SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
392    SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
393    SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
394    SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
395    SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
396    SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
397    SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
398    SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
399    SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
400    SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
401    SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
402                                 bool IsSRA) const;
403    SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
404    SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
405
406    /// isEligibleForTailCallOptimization - Check whether the call is eligible
407    /// for tail call optimization.
408    virtual bool
409    isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
410                                      unsigned NextStackOffset,
411                                      const MipsFunctionInfo& FI) const = 0;
412
413    /// copyByValArg - Copy argument registers which were used to pass a byval
414    /// argument to the stack. Create a stack frame object for the byval
415    /// argument.
416    void copyByValRegs(SDValue Chain, SDLoc DL,
417                       std::vector<SDValue> &OutChains, SelectionDAG &DAG,
418                       const ISD::ArgFlagsTy &Flags,
419                       SmallVectorImpl<SDValue> &InVals,
420                       const Argument *FuncArg,
421                       const MipsCC &CC, const ByValArgInfo &ByVal) const;
422
423    /// passByValArg - Pass a byval argument in registers or on stack.
424    void passByValArg(SDValue Chain, SDLoc DL,
425                      std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
426                      SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
427                      MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
428                      const MipsCC &CC, const ByValArgInfo &ByVal,
429                      const ISD::ArgFlagsTy &Flags, bool isLittle) const;
430
431    /// writeVarArgRegs - Write variable function arguments passed in registers
432    /// to the stack. Also create a stack frame object for the first variable
433    /// argument.
434    void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
435                         SDValue Chain, SDLoc DL, SelectionDAG &DAG) const;
436
437    virtual SDValue
438      LowerFormalArguments(SDValue Chain,
439                           CallingConv::ID CallConv, bool isVarArg,
440                           const SmallVectorImpl<ISD::InputArg> &Ins,
441                           SDLoc dl, SelectionDAG &DAG,
442                           SmallVectorImpl<SDValue> &InVals) const;
443
444    SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
445                           SDValue Arg, SDLoc DL, bool IsTailCall,
446                           SelectionDAG &DAG) const;
447
448    virtual SDValue
449      LowerCall(TargetLowering::CallLoweringInfo &CLI,
450                SmallVectorImpl<SDValue> &InVals) const;
451
452    virtual bool
453      CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
454                     bool isVarArg,
455                     const SmallVectorImpl<ISD::OutputArg> &Outs,
456                     LLVMContext &Context) const;
457
458    virtual SDValue
459      LowerReturn(SDValue Chain,
460                  CallingConv::ID CallConv, bool isVarArg,
461                  const SmallVectorImpl<ISD::OutputArg> &Outs,
462                  const SmallVectorImpl<SDValue> &OutVals,
463                  SDLoc dl, SelectionDAG &DAG) const;
464
465    // Inline asm support
466    ConstraintType getConstraintType(const std::string &Constraint) const;
467
468    /// Examine constraint string and operand type and determine a weight value.
469    /// The operand object must already have been set up with the operand type.
470    ConstraintWeight getSingleConstraintMatchWeight(
471      AsmOperandInfo &info, const char *constraint) const;
472
473    /// This function parses registers that appear in inline-asm constraints.
474    /// It returns pair (0, 0) on failure.
475    std::pair<unsigned, const TargetRegisterClass *>
476    parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const;
477
478    std::pair<unsigned, const TargetRegisterClass*>
479              getRegForInlineAsmConstraint(const std::string &Constraint,
480                                           MVT VT) const;
481
482    /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
483    /// vector.  If it is invalid, don't add anything to Ops. If hasMemory is
484    /// true it means one of the asm constraint of the inline asm instruction
485    /// being processed is 'm'.
486    virtual void LowerAsmOperandForConstraint(SDValue Op,
487                                              std::string &Constraint,
488                                              std::vector<SDValue> &Ops,
489                                              SelectionDAG &DAG) const;
490
491    virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
492
493    virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
494
495    virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
496                                    unsigned SrcAlign,
497                                    bool IsMemset, bool ZeroMemset,
498                                    bool MemcpyStrSrc,
499                                    MachineFunction &MF) const;
500
501    /// isFPImmLegal - Returns true if the target can instruction select the
502    /// specified FP immediate natively. If false, the legalizer will
503    /// materialize the FP immediate as a load from a constant pool.
504    virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
505
506    virtual unsigned getJumpTableEncoding() const;
507
508    MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
509                    unsigned Size, unsigned BinOpcode, bool Nand = false) const;
510    MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
511                    MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
512                    bool Nand = false) const;
513    MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
514                                  MachineBasicBlock *BB, unsigned Size) const;
515    MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
516                                  MachineBasicBlock *BB, unsigned Size) const;
517  };
518
519  /// Create MipsTargetLowering objects.
520  const MipsTargetLowering *createMips16TargetLowering(MipsTargetMachine &TM);
521  const MipsTargetLowering *createMipsSETargetLowering(MipsTargetMachine &TM);
522}
523
524#endif // MipsISELLOWERING_H
525