MipsISelLowering.h revision 38b5e86b9c67f601f354f8bcc11f5a515e200315 
1//===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that Mips uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef MipsISELLOWERING_H
16#define MipsISELLOWERING_H
17
18#include "llvm/CodeGen/SelectionDAG.h"
19#include "llvm/Target/TargetLowering.h"
20#include "Mips.h"
21#include "MipsSubtarget.h"
22
23namespace llvm {
24  namespace MipsISD {
25    enum NodeType {
26      // Start the numbering from where ISD NodeType finishes.
27      FIRST_NUMBER = ISD::BUILTIN_OP_END,
28
29      // Jump and link (call)
30      JmpLink,
31
32      // Get the Higher 16 bits from a 32-bit immediate
33      // No relation with Mips Hi register
34      Hi,
35
36      // Get the Lower 16 bits from a 32-bit immediate
37      // No relation with Mips Lo register
38      Lo,
39
40      // Handle gp_rel (small data/bss sections) relocation.
41      GPRel,
42
43      // Select CC Pseudo Instruction
44      SelectCC,
45
46      // Floating Point Select CC Pseudo Instruction
47      FPSelectCC,
48
49      // Floating Point Branch Conditional
50      FPBrcond,
51
52      // Floating Point Compare
53      FPCmp,
54
55      // Floating Point Rounding
56      FPRound,
57
58      // Return
59      Ret,
60
61      // MAdd/Sub nodes
62      MAdd,
63      MAddu,
64      MSub,
65      MSubu,
66
67      // DivRem(u)
68      DivRem,
69      DivRemU
70    };
71  }
72
73  //===--------------------------------------------------------------------===//
74  // TargetLowering Implementation
75  //===--------------------------------------------------------------------===//
76
77  class MipsTargetLowering : public TargetLowering  {
78  public:
79    explicit MipsTargetLowering(MipsTargetMachine &TM);
80
81    /// LowerOperation - Provide custom lowering hooks for some operations.
82    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
83
84    /// getTargetNodeName - This method returns the name of a target specific
85    //  DAG node.
86    virtual const char *getTargetNodeName(unsigned Opcode) const;
87
88    /// getSetCCResultType - get the ISD::SETCC result ValueType
89    MVT::SimpleValueType getSetCCResultType(EVT VT) const;
90
91    /// getFunctionAlignment - Return the Log2 alignment of this function.
92    virtual unsigned getFunctionAlignment(const Function *F) const;
93
94    virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
95  private:
96    // Subtarget Info
97    const MipsSubtarget *Subtarget;
98
99
100    // Lower Operand helpers
101    SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
102                            CallingConv::ID CallConv, bool isVarArg,
103                            const SmallVectorImpl<ISD::InputArg> &Ins,
104                            DebugLoc dl, SelectionDAG &DAG,
105                            SmallVectorImpl<SDValue> &InVals) const;
106
107    // Lower Operand specifics
108    SDValue LowerANDOR(SDValue Op, SelectionDAG &DAG) const;
109    SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
110    SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
111    SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
112    SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
113    SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
114    SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
115    SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
116    SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
117    SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
118    SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
119    SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
120
121    virtual SDValue
122      LowerFormalArguments(SDValue Chain,
123                           CallingConv::ID CallConv, bool isVarArg,
124                           const SmallVectorImpl<ISD::InputArg> &Ins,
125                           DebugLoc dl, SelectionDAG &DAG,
126                           SmallVectorImpl<SDValue> &InVals) const;
127
128    virtual SDValue
129      LowerCall(SDValue Chain, SDValue Callee,
130                CallingConv::ID CallConv, bool isVarArg,
131                bool &isTailCall,
132                const SmallVectorImpl<ISD::OutputArg> &Outs,
133                const SmallVectorImpl<SDValue> &OutVals,
134                const SmallVectorImpl<ISD::InputArg> &Ins,
135                DebugLoc dl, SelectionDAG &DAG,
136                SmallVectorImpl<SDValue> &InVals) const;
137
138    virtual SDValue
139      LowerReturn(SDValue Chain,
140                  CallingConv::ID CallConv, bool isVarArg,
141                  const SmallVectorImpl<ISD::OutputArg> &Outs,
142                  const SmallVectorImpl<SDValue> &OutVals,
143                  DebugLoc dl, SelectionDAG &DAG) const;
144
145    virtual MachineBasicBlock *
146      EmitInstrWithCustomInserter(MachineInstr *MI,
147                                  MachineBasicBlock *MBB) const;
148
149    // Inline asm support
150    ConstraintType getConstraintType(const std::string &Constraint) const;
151
152    /// Examine constraint string and operand type and determine a weight value.
153    /// The operand object must already have been set up with the operand type.
154    ConstraintWeight getSingleConstraintMatchWeight(
155      AsmOperandInfo &info, const char *constraint) const;
156
157    std::pair<unsigned, const TargetRegisterClass*>
158              getRegForInlineAsmConstraint(const std::string &Constraint,
159              EVT VT) const;
160
161    std::vector<unsigned>
162    getRegClassForInlineAsmConstraint(const std::string &Constraint,
163              EVT VT) const;
164
165    virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
166
167    /// isFPImmLegal - Returns true if the target can instruction select the
168    /// specified FP immediate natively. If false, the legalizer will
169    /// materialize the FP immediate as a load from a constant pool.
170    virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
171  };
172}
173
174#endif // MipsISELLOWERING_H
175