MipsISelLowering.h revision 3c380d5e28f86984b147fcd424736c498773f37e 
1//===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that Mips uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef MipsISELLOWERING_H
16#define MipsISELLOWERING_H
17
18#include "Mips.h"
19#include "MipsSubtarget.h"
20#include "llvm/CodeGen/CallingConvLower.h"
21#include "llvm/CodeGen/SelectionDAG.h"
22#include "llvm/IR/Function.h"
23#include "llvm/Target/TargetLowering.h"
24#include <deque>
25#include <string>
26
27namespace llvm {
28  namespace MipsISD {
29    enum NodeType {
30      // Start the numbering from where ISD NodeType finishes.
31      FIRST_NUMBER = ISD::BUILTIN_OP_END,
32
33      // Jump and link (call)
34      JmpLink,
35
36      // Tail call
37      TailCall,
38
39      // Get the Higher 16 bits from a 32-bit immediate
40      // No relation with Mips Hi register
41      Hi,
42
43      // Get the Lower 16 bits from a 32-bit immediate
44      // No relation with Mips Lo register
45      Lo,
46
47      // Handle gp_rel (small data/bss sections) relocation.
48      GPRel,
49
50      // Thread Pointer
51      ThreadPointer,
52
53      // Floating Point Branch Conditional
54      FPBrcond,
55
56      // Floating Point Compare
57      FPCmp,
58
59      // Floating Point Conditional Moves
60      CMovFP_T,
61      CMovFP_F,
62
63      // FP-to-int truncation node.
64      TruncIntFP,
65
66      // Return
67      Ret,
68
69      EH_RETURN,
70
71      // Node used to extract integer from accumulator.
72      ExtractLOHI,
73
74      // Node used to insert integers to accumulator.
75      InsertLOHI,
76
77      // Mult nodes.
78      Mult,
79      Multu,
80
81      // MAdd/Sub nodes
82      MAdd,
83      MAddu,
84      MSub,
85      MSubu,
86
87      // DivRem(u)
88      DivRem,
89      DivRemU,
90      DivRem16,
91      DivRemU16,
92
93      BuildPairF64,
94      ExtractElementF64,
95
96      Wrapper,
97
98      DynAlloc,
99
100      Sync,
101
102      Ext,
103      Ins,
104
105      // EXTR.W instrinsic nodes.
106      EXTP,
107      EXTPDP,
108      EXTR_S_H,
109      EXTR_W,
110      EXTR_R_W,
111      EXTR_RS_W,
112      SHILO,
113      MTHLIP,
114
115      // DPA.W intrinsic nodes.
116      MULSAQ_S_W_PH,
117      MAQ_S_W_PHL,
118      MAQ_S_W_PHR,
119      MAQ_SA_W_PHL,
120      MAQ_SA_W_PHR,
121      DPAU_H_QBL,
122      DPAU_H_QBR,
123      DPSU_H_QBL,
124      DPSU_H_QBR,
125      DPAQ_S_W_PH,
126      DPSQ_S_W_PH,
127      DPAQ_SA_L_W,
128      DPSQ_SA_L_W,
129      DPA_W_PH,
130      DPS_W_PH,
131      DPAQX_S_W_PH,
132      DPAQX_SA_W_PH,
133      DPAX_W_PH,
134      DPSX_W_PH,
135      DPSQX_S_W_PH,
136      DPSQX_SA_W_PH,
137      MULSA_W_PH,
138
139      MULT,
140      MULTU,
141      MADD_DSP,
142      MADDU_DSP,
143      MSUB_DSP,
144      MSUBU_DSP,
145
146      // DSP shift nodes.
147      SHLL_DSP,
148      SHRA_DSP,
149      SHRL_DSP,
150
151      // DSP setcc and select_cc nodes.
152      SETCC_DSP,
153      SELECT_CC_DSP,
154
155      // Vector comparisons
156      VALL_ZERO,
157      VANY_ZERO,
158      VALL_NONZERO,
159      VANY_NONZERO,
160
161      // Load/Store Left/Right nodes.
162      LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
163      LWR,
164      SWL,
165      SWR,
166      LDL,
167      LDR,
168      SDL,
169      SDR
170    };
171  }
172
173  //===--------------------------------------------------------------------===//
174  // TargetLowering Implementation
175  //===--------------------------------------------------------------------===//
176  class MipsFunctionInfo;
177
178  class MipsTargetLowering : public TargetLowering  {
179  public:
180    explicit MipsTargetLowering(MipsTargetMachine &TM);
181
182    static const MipsTargetLowering *create(MipsTargetMachine &TM);
183
184    virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
185
186    virtual void LowerOperationWrapper(SDNode *N,
187                                       SmallVectorImpl<SDValue> &Results,
188                                       SelectionDAG &DAG) const;
189
190    /// LowerOperation - Provide custom lowering hooks for some operations.
191    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
192
193    /// ReplaceNodeResults - Replace the results of node with an illegal result
194    /// type with new values built out of custom code.
195    ///
196    virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
197                                    SelectionDAG &DAG) const;
198
199    /// getTargetNodeName - This method returns the name of a target specific
200    //  DAG node.
201    virtual const char *getTargetNodeName(unsigned Opcode) const;
202
203    /// getSetCCResultType - get the ISD::SETCC result ValueType
204    EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
205
206    virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
207
208    virtual MachineBasicBlock *
209    EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
210
211    struct LTStr {
212      bool operator()(const char *S1, const char *S2) const {
213        return strcmp(S1, S2) < 0;
214      }
215    };
216
217  protected:
218    SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
219
220    SDValue getAddrLocal(SDValue Op, SelectionDAG &DAG, bool HasMips64) const;
221
222    SDValue getAddrGlobal(SDValue Op, SelectionDAG &DAG, unsigned Flag) const;
223
224    SDValue getAddrGlobalLargeGOT(SDValue Op, SelectionDAG &DAG,
225                                  unsigned HiFlag, unsigned LoFlag) const;
226
227    /// This function fills Ops, which is the list of operands that will later
228    /// be used when a function call node is created. It also generates
229    /// copyToReg nodes to set up argument registers.
230    virtual void
231    getOpndList(SmallVectorImpl<SDValue> &Ops,
232                std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
233                bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
234                CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
235
236    /// ByValArgInfo - Byval argument information.
237    struct ByValArgInfo {
238      unsigned FirstIdx; // Index of the first register used.
239      unsigned NumRegs;  // Number of registers used for this argument.
240      unsigned Address;  // Offset of the stack area used to pass this argument.
241
242      ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
243    };
244
245    /// MipsCC - This class provides methods used to analyze formal and call
246    /// arguments and inquire about calling convention information.
247    class MipsCC {
248    public:
249      enum SpecialCallingConvType {
250        Mips16RetHelperConv, NoSpecialCallingConv
251      };
252
253      MipsCC(CallingConv::ID CallConv, bool IsO32, bool IsFP64, CCState &Info,
254             SpecialCallingConvType SpecialCallingConv = NoSpecialCallingConv);
255
256
257      void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
258                               bool IsVarArg, bool IsSoftFloat,
259                               const SDNode *CallNode,
260                               std::vector<ArgListEntry> &FuncArgs);
261      void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
262                                  bool IsSoftFloat,
263                                  Function::const_arg_iterator FuncArg);
264
265      void analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
266                             bool IsSoftFloat, const SDNode *CallNode,
267                             const Type *RetTy) const;
268
269      void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
270                         bool IsSoftFloat, const Type *RetTy) const;
271
272      const CCState &getCCInfo() const { return CCInfo; }
273
274      /// hasByValArg - Returns true if function has byval arguments.
275      bool hasByValArg() const { return !ByValArgs.empty(); }
276
277      /// regSize - Size (in number of bits) of integer registers.
278      unsigned regSize() const { return IsO32 ? 4 : 8; }
279
280      /// numIntArgRegs - Number of integer registers available for calls.
281      unsigned numIntArgRegs() const;
282
283      /// reservedArgArea - The size of the area the caller reserves for
284      /// register arguments. This is 16-byte if ABI is O32.
285      unsigned reservedArgArea() const;
286
287      /// Return pointer to array of integer argument registers.
288      const uint16_t *intArgRegs() const;
289
290      typedef SmallVectorImpl<ByValArgInfo>::const_iterator byval_iterator;
291      byval_iterator byval_begin() const { return ByValArgs.begin(); }
292      byval_iterator byval_end() const { return ByValArgs.end(); }
293
294    private:
295      void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
296                          CCValAssign::LocInfo LocInfo,
297                          ISD::ArgFlagsTy ArgFlags);
298
299      /// useRegsForByval - Returns true if the calling convention allows the
300      /// use of registers to pass byval arguments.
301      bool useRegsForByval() const { return CallConv != CallingConv::Fast; }
302
303      /// Return the function that analyzes fixed argument list functions.
304      llvm::CCAssignFn *fixedArgFn() const;
305
306      /// Return the function that analyzes variable argument list functions.
307      llvm::CCAssignFn *varArgFn() const;
308
309      const uint16_t *shadowRegs() const;
310
311      void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
312                        unsigned Align);
313
314      /// Return the type of the register which is used to pass an argument or
315      /// return a value. This function returns f64 if the argument is an i64
316      /// value which has been generated as a result of softening an f128 value.
317      /// Otherwise, it just returns VT.
318      MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode,
319                   bool IsSoftFloat) const;
320
321      template<typename Ty>
322      void analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat,
323                         const SDNode *CallNode, const Type *RetTy) const;
324
325      CCState &CCInfo;
326      CallingConv::ID CallConv;
327      bool IsO32, IsFP64;
328      SpecialCallingConvType SpecialCallingConv;
329      SmallVector<ByValArgInfo, 2> ByValArgs;
330    };
331  protected:
332    // Subtarget Info
333    const MipsSubtarget *Subtarget;
334
335    bool HasMips64, IsN64, IsO32;
336
337  private:
338
339    MipsCC::SpecialCallingConvType getSpecialCallingConv(SDValue Callee) const;
340    // Lower Operand helpers
341    SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
342                            CallingConv::ID CallConv, bool isVarArg,
343                            const SmallVectorImpl<ISD::InputArg> &Ins,
344                            SDLoc dl, SelectionDAG &DAG,
345                            SmallVectorImpl<SDValue> &InVals,
346                            const SDNode *CallNode, const Type *RetTy) const;
347
348    // Lower Operand specifics
349    SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
350    SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
351    SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
352    SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
353    SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
354    SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
355    SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
356    SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
357    SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
358    SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
359    SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
360    SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
361    SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
362    SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
363    SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
364    SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
365    SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
366    SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
367    SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
368                                 bool IsSRA) const;
369    SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
370    SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
371    SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
372    SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
373
374    /// isEligibleForTailCallOptimization - Check whether the call is eligible
375    /// for tail call optimization.
376    virtual bool
377    isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
378                                      unsigned NextStackOffset,
379                                      const MipsFunctionInfo& FI) const = 0;
380
381    /// copyByValArg - Copy argument registers which were used to pass a byval
382    /// argument to the stack. Create a stack frame object for the byval
383    /// argument.
384    void copyByValRegs(SDValue Chain, SDLoc DL,
385                       std::vector<SDValue> &OutChains, SelectionDAG &DAG,
386                       const ISD::ArgFlagsTy &Flags,
387                       SmallVectorImpl<SDValue> &InVals,
388                       const Argument *FuncArg,
389                       const MipsCC &CC, const ByValArgInfo &ByVal) const;
390
391    /// passByValArg - Pass a byval argument in registers or on stack.
392    void passByValArg(SDValue Chain, SDLoc DL,
393                      std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
394                      SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
395                      MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
396                      const MipsCC &CC, const ByValArgInfo &ByVal,
397                      const ISD::ArgFlagsTy &Flags, bool isLittle) const;
398
399    /// writeVarArgRegs - Write variable function arguments passed in registers
400    /// to the stack. Also create a stack frame object for the first variable
401    /// argument.
402    void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
403                         SDValue Chain, SDLoc DL, SelectionDAG &DAG) const;
404
405    virtual SDValue
406      LowerFormalArguments(SDValue Chain,
407                           CallingConv::ID CallConv, bool isVarArg,
408                           const SmallVectorImpl<ISD::InputArg> &Ins,
409                           SDLoc dl, SelectionDAG &DAG,
410                           SmallVectorImpl<SDValue> &InVals) const;
411
412    SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
413                           SDValue Arg, SDLoc DL, bool IsTailCall,
414                           SelectionDAG &DAG) const;
415
416    virtual SDValue
417      LowerCall(TargetLowering::CallLoweringInfo &CLI,
418                SmallVectorImpl<SDValue> &InVals) const;
419
420    virtual bool
421      CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
422                     bool isVarArg,
423                     const SmallVectorImpl<ISD::OutputArg> &Outs,
424                     LLVMContext &Context) const;
425
426    virtual SDValue
427      LowerReturn(SDValue Chain,
428                  CallingConv::ID CallConv, bool isVarArg,
429                  const SmallVectorImpl<ISD::OutputArg> &Outs,
430                  const SmallVectorImpl<SDValue> &OutVals,
431                  SDLoc dl, SelectionDAG &DAG) const;
432
433    // Inline asm support
434    ConstraintType getConstraintType(const std::string &Constraint) const;
435
436    /// Examine constraint string and operand type and determine a weight value.
437    /// The operand object must already have been set up with the operand type.
438    ConstraintWeight getSingleConstraintMatchWeight(
439      AsmOperandInfo &info, const char *constraint) const;
440
441    /// This function parses registers that appear in inline-asm constraints.
442    /// It returns pair (0, 0) on failure.
443    std::pair<unsigned, const TargetRegisterClass *>
444    parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const;
445
446    std::pair<unsigned, const TargetRegisterClass*>
447              getRegForInlineAsmConstraint(const std::string &Constraint,
448                                           MVT VT) const;
449
450    /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
451    /// vector.  If it is invalid, don't add anything to Ops. If hasMemory is
452    /// true it means one of the asm constraint of the inline asm instruction
453    /// being processed is 'm'.
454    virtual void LowerAsmOperandForConstraint(SDValue Op,
455                                              std::string &Constraint,
456                                              std::vector<SDValue> &Ops,
457                                              SelectionDAG &DAG) const;
458
459    virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
460
461    virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
462
463    virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
464                                    unsigned SrcAlign,
465                                    bool IsMemset, bool ZeroMemset,
466                                    bool MemcpyStrSrc,
467                                    MachineFunction &MF) const;
468
469    /// isFPImmLegal - Returns true if the target can instruction select the
470    /// specified FP immediate natively. If false, the legalizer will
471    /// materialize the FP immediate as a load from a constant pool.
472    virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
473
474    virtual unsigned getJumpTableEncoding() const;
475
476    MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
477                    unsigned Size, unsigned BinOpcode, bool Nand = false) const;
478    MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
479                    MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
480                    bool Nand = false) const;
481    MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
482                                  MachineBasicBlock *BB, unsigned Size) const;
483    MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
484                                  MachineBasicBlock *BB, unsigned Size) const;
485  };
486
487  /// Create MipsTargetLowering objects.
488  const MipsTargetLowering *createMips16TargetLowering(MipsTargetMachine &TM);
489  const MipsTargetLowering *createMipsSETargetLowering(MipsTargetMachine &TM);
490}
491
492#endif // MipsISELLOWERING_H
493