MipsISelLowering.h revision 46090914b783b632618268f2a5c99aab83732688 
1//===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that Mips uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef MipsISELLOWERING_H
16#define MipsISELLOWERING_H
17
18#include "Mips.h"
19#include "MipsSubtarget.h"
20#include "llvm/CodeGen/CallingConvLower.h"
21#include "llvm/CodeGen/SelectionDAG.h"
22#include "llvm/IR/Function.h"
23#include "llvm/Target/TargetLowering.h"
24#include <deque>
25#include <string>
26
27namespace llvm {
28  namespace MipsISD {
29    enum NodeType {
30      // Start the numbering from where ISD NodeType finishes.
31      FIRST_NUMBER = ISD::BUILTIN_OP_END,
32
33      // Jump and link (call)
34      JmpLink,
35
36      // Tail call
37      TailCall,
38
39      // Get the Higher 16 bits from a 32-bit immediate
40      // No relation with Mips Hi register
41      Hi,
42
43      // Get the Lower 16 bits from a 32-bit immediate
44      // No relation with Mips Lo register
45      Lo,
46
47      // Handle gp_rel (small data/bss sections) relocation.
48      GPRel,
49
50      // Thread Pointer
51      ThreadPointer,
52
53      // Floating Point Branch Conditional
54      FPBrcond,
55
56      // Floating Point Compare
57      FPCmp,
58
59      // Floating Point Conditional Moves
60      CMovFP_T,
61      CMovFP_F,
62
63      // Floating Point Rounding
64      FPRound,
65
66      // Return
67      Ret,
68
69      EH_RETURN,
70
71      // Node used to extract integer from accumulator.
72      ExtractLOHI,
73
74      // Node used to insert integers to accumulator.
75      InsertLOHI,
76
77      // Mult nodes.
78      Mult,
79      Multu,
80
81      // MAdd/Sub nodes
82      MAdd,
83      MAddu,
84      MSub,
85      MSubu,
86
87      // DivRem(u)
88      DivRem,
89      DivRemU,
90      DivRem16,
91      DivRemU16,
92
93      BuildPairF64,
94      ExtractElementF64,
95
96      Wrapper,
97
98      DynAlloc,
99
100      Sync,
101
102      Ext,
103      Ins,
104
105      // EXTR.W instrinsic nodes.
106      EXTP,
107      EXTPDP,
108      EXTR_S_H,
109      EXTR_W,
110      EXTR_R_W,
111      EXTR_RS_W,
112      SHILO,
113      MTHLIP,
114
115      // DPA.W intrinsic nodes.
116      MULSAQ_S_W_PH,
117      MAQ_S_W_PHL,
118      MAQ_S_W_PHR,
119      MAQ_SA_W_PHL,
120      MAQ_SA_W_PHR,
121      DPAU_H_QBL,
122      DPAU_H_QBR,
123      DPSU_H_QBL,
124      DPSU_H_QBR,
125      DPAQ_S_W_PH,
126      DPSQ_S_W_PH,
127      DPAQ_SA_L_W,
128      DPSQ_SA_L_W,
129      DPA_W_PH,
130      DPS_W_PH,
131      DPAQX_S_W_PH,
132      DPAQX_SA_W_PH,
133      DPAX_W_PH,
134      DPSX_W_PH,
135      DPSQX_S_W_PH,
136      DPSQX_SA_W_PH,
137      MULSA_W_PH,
138
139      MULT,
140      MULTU,
141      MADD_DSP,
142      MADDU_DSP,
143      MSUB_DSP,
144      MSUBU_DSP,
145
146      // DSP shift nodes.
147      SHLL_DSP,
148      SHRA_DSP,
149      SHRL_DSP,
150
151      // DSP setcc and select_cc nodes.
152      SETCC_DSP,
153      SELECT_CC_DSP,
154
155      // Load/Store Left/Right nodes.
156      LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
157      LWR,
158      SWL,
159      SWR,
160      LDL,
161      LDR,
162      SDL,
163      SDR
164    };
165  }
166
167  //===--------------------------------------------------------------------===//
168  // TargetLowering Implementation
169  //===--------------------------------------------------------------------===//
170  class MipsFunctionInfo;
171
172  class MipsTargetLowering : public TargetLowering  {
173  public:
174    explicit MipsTargetLowering(MipsTargetMachine &TM);
175
176    static const MipsTargetLowering *create(MipsTargetMachine &TM);
177
178    virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
179
180    virtual void LowerOperationWrapper(SDNode *N,
181                                       SmallVectorImpl<SDValue> &Results,
182                                       SelectionDAG &DAG) const;
183
184    /// LowerOperation - Provide custom lowering hooks for some operations.
185    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
186
187    /// ReplaceNodeResults - Replace the results of node with an illegal result
188    /// type with new values built out of custom code.
189    ///
190    virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
191                                    SelectionDAG &DAG) const;
192
193    /// getTargetNodeName - This method returns the name of a target specific
194    //  DAG node.
195    virtual const char *getTargetNodeName(unsigned Opcode) const;
196
197    /// getSetCCResultType - get the ISD::SETCC result ValueType
198    EVT getSetCCResultType(EVT VT) const;
199
200    virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
201
202    virtual MachineBasicBlock *
203    EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
204
205    struct LTStr {
206      bool operator()(const char *S1, const char *S2) const {
207        return strcmp(S1, S2) < 0;
208      }
209    };
210
211  protected:
212    SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
213
214    SDValue getAddrLocal(SDValue Op, SelectionDAG &DAG, bool HasMips64) const;
215
216    SDValue getAddrGlobal(SDValue Op, SelectionDAG &DAG, unsigned Flag) const;
217
218    SDValue getAddrGlobalLargeGOT(SDValue Op, SelectionDAG &DAG,
219                                  unsigned HiFlag, unsigned LoFlag) const;
220
221    /// This function fills Ops, which is the list of operands that will later
222    /// be used when a function call node is created. It also generates
223    /// copyToReg nodes to set up argument registers.
224    virtual void
225    getOpndList(SmallVectorImpl<SDValue> &Ops,
226                std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
227                bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
228                CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
229
230    /// ByValArgInfo - Byval argument information.
231    struct ByValArgInfo {
232      unsigned FirstIdx; // Index of the first register used.
233      unsigned NumRegs;  // Number of registers used for this argument.
234      unsigned Address;  // Offset of the stack area used to pass this argument.
235
236      ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
237    };
238
239    /// MipsCC - This class provides methods used to analyze formal and call
240    /// arguments and inquire about calling convention information.
241    class MipsCC {
242    public:
243      enum SpecialCallingConvType {
244        Mips16RetHelperConv, NoSpecialCallingConv
245      };
246
247      MipsCC(
248        CallingConv::ID CallConv, bool IsO32, CCState &Info,
249        SpecialCallingConvType SpecialCallingConv = NoSpecialCallingConv);
250
251
252      void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
253                               bool IsVarArg, bool IsSoftFloat,
254                               const SDNode *CallNode,
255                               std::vector<ArgListEntry> &FuncArgs);
256      void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
257                                  bool IsSoftFloat,
258                                  Function::const_arg_iterator FuncArg);
259
260      void analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
261                             bool IsSoftFloat, const SDNode *CallNode,
262                             const Type *RetTy) const;
263
264      void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
265                         bool IsSoftFloat, const Type *RetTy) const;
266
267      const CCState &getCCInfo() const { return CCInfo; }
268
269      /// hasByValArg - Returns true if function has byval arguments.
270      bool hasByValArg() const { return !ByValArgs.empty(); }
271
272      /// regSize - Size (in number of bits) of integer registers.
273      unsigned regSize() const { return IsO32 ? 4 : 8; }
274
275      /// numIntArgRegs - Number of integer registers available for calls.
276      unsigned numIntArgRegs() const;
277
278      /// reservedArgArea - The size of the area the caller reserves for
279      /// register arguments. This is 16-byte if ABI is O32.
280      unsigned reservedArgArea() const;
281
282      /// Return pointer to array of integer argument registers.
283      const uint16_t *intArgRegs() const;
284
285      typedef SmallVector<ByValArgInfo, 2>::const_iterator byval_iterator;
286      byval_iterator byval_begin() const { return ByValArgs.begin(); }
287      byval_iterator byval_end() const { return ByValArgs.end(); }
288
289    private:
290      void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
291                          CCValAssign::LocInfo LocInfo,
292                          ISD::ArgFlagsTy ArgFlags);
293
294      /// useRegsForByval - Returns true if the calling convention allows the
295      /// use of registers to pass byval arguments.
296      bool useRegsForByval() const { return CallConv != CallingConv::Fast; }
297
298      /// Return the function that analyzes fixed argument list functions.
299      llvm::CCAssignFn *fixedArgFn() const;
300
301      /// Return the function that analyzes variable argument list functions.
302      llvm::CCAssignFn *varArgFn() const;
303
304      const uint16_t *shadowRegs() const;
305
306      void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
307                        unsigned Align);
308
309      /// Return the type of the register which is used to pass an argument or
310      /// return a value. This function returns f64 if the argument is an i64
311      /// value which has been generated as a result of softening an f128 value.
312      /// Otherwise, it just returns VT.
313      MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode,
314                   bool IsSoftFloat) const;
315
316      template<typename Ty>
317      void analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat,
318                         const SDNode *CallNode, const Type *RetTy) const;
319
320      CCState &CCInfo;
321      CallingConv::ID CallConv;
322      bool IsO32;
323      SpecialCallingConvType SpecialCallingConv;
324      SmallVector<ByValArgInfo, 2> ByValArgs;
325    };
326  protected:
327    // Subtarget Info
328    const MipsSubtarget *Subtarget;
329
330    bool HasMips64, IsN64, IsO32;
331
332  private:
333
334    MipsCC::SpecialCallingConvType getSpecialCallingConv(SDValue Callee) const;
335    // Lower Operand helpers
336    SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
337                            CallingConv::ID CallConv, bool isVarArg,
338                            const SmallVectorImpl<ISD::InputArg> &Ins,
339                            DebugLoc dl, SelectionDAG &DAG,
340                            SmallVectorImpl<SDValue> &InVals,
341                            const SDNode *CallNode, const Type *RetTy) const;
342
343    // Lower Operand specifics
344    SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
345    SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
346    SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
347    SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
348    SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
349    SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
350    SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
351    SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
352    SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
353    SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
354    SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
355    SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
356    SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
357    SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
358    SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
359    SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
360    SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
361    SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
362    SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
363                                 bool IsSRA) const;
364    SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
365    SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
366    SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
367
368    /// isEligibleForTailCallOptimization - Check whether the call is eligible
369    /// for tail call optimization.
370    virtual bool
371    isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
372                                      unsigned NextStackOffset,
373                                      const MipsFunctionInfo& FI) const = 0;
374
375    /// copyByValArg - Copy argument registers which were used to pass a byval
376    /// argument to the stack. Create a stack frame object for the byval
377    /// argument.
378    void copyByValRegs(SDValue Chain, DebugLoc DL,
379                       std::vector<SDValue> &OutChains, SelectionDAG &DAG,
380                       const ISD::ArgFlagsTy &Flags,
381                       SmallVectorImpl<SDValue> &InVals,
382                       const Argument *FuncArg,
383                       const MipsCC &CC, const ByValArgInfo &ByVal) const;
384
385    /// passByValArg - Pass a byval argument in registers or on stack.
386    void passByValArg(SDValue Chain, DebugLoc DL,
387                      std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
388                      SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr,
389                      MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
390                      const MipsCC &CC, const ByValArgInfo &ByVal,
391                      const ISD::ArgFlagsTy &Flags, bool isLittle) const;
392
393    /// writeVarArgRegs - Write variable function arguments passed in registers
394    /// to the stack. Also create a stack frame object for the first variable
395    /// argument.
396    void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
397                         SDValue Chain, DebugLoc DL, SelectionDAG &DAG) const;
398
399    virtual SDValue
400      LowerFormalArguments(SDValue Chain,
401                           CallingConv::ID CallConv, bool isVarArg,
402                           const SmallVectorImpl<ISD::InputArg> &Ins,
403                           DebugLoc dl, SelectionDAG &DAG,
404                           SmallVectorImpl<SDValue> &InVals) const;
405
406    SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
407                           SDValue Arg, DebugLoc DL, bool IsTailCall,
408                           SelectionDAG &DAG) const;
409
410    virtual SDValue
411      LowerCall(TargetLowering::CallLoweringInfo &CLI,
412                SmallVectorImpl<SDValue> &InVals) const;
413
414    virtual bool
415      CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
416                     bool isVarArg,
417                     const SmallVectorImpl<ISD::OutputArg> &Outs,
418                     LLVMContext &Context) const;
419
420    virtual SDValue
421      LowerReturn(SDValue Chain,
422                  CallingConv::ID CallConv, bool isVarArg,
423                  const SmallVectorImpl<ISD::OutputArg> &Outs,
424                  const SmallVectorImpl<SDValue> &OutVals,
425                  DebugLoc dl, SelectionDAG &DAG) const;
426
427    // Inline asm support
428    ConstraintType getConstraintType(const std::string &Constraint) const;
429
430    /// Examine constraint string and operand type and determine a weight value.
431    /// The operand object must already have been set up with the operand type.
432    ConstraintWeight getSingleConstraintMatchWeight(
433      AsmOperandInfo &info, const char *constraint) const;
434
435    std::pair<unsigned, const TargetRegisterClass*>
436              getRegForInlineAsmConstraint(const std::string &Constraint,
437              EVT VT) const;
438
439    /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
440    /// vector.  If it is invalid, don't add anything to Ops. If hasMemory is
441    /// true it means one of the asm constraint of the inline asm instruction
442    /// being processed is 'm'.
443    virtual void LowerAsmOperandForConstraint(SDValue Op,
444                                              std::string &Constraint,
445                                              std::vector<SDValue> &Ops,
446                                              SelectionDAG &DAG) const;
447
448    virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
449
450    virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
451
452    virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
453                                    unsigned SrcAlign,
454                                    bool IsMemset, bool ZeroMemset,
455                                    bool MemcpyStrSrc,
456                                    MachineFunction &MF) const;
457
458    /// isFPImmLegal - Returns true if the target can instruction select the
459    /// specified FP immediate natively. If false, the legalizer will
460    /// materialize the FP immediate as a load from a constant pool.
461    virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
462
463    virtual unsigned getJumpTableEncoding() const;
464
465    MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
466                    unsigned Size, unsigned BinOpcode, bool Nand = false) const;
467    MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
468                    MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
469                    bool Nand = false) const;
470    MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
471                                  MachineBasicBlock *BB, unsigned Size) const;
472    MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
473                                  MachineBasicBlock *BB, unsigned Size) const;
474  };
475
476  /// Create MipsTargetLowering objects.
477  const MipsTargetLowering *createMips16TargetLowering(MipsTargetMachine &TM);
478  const MipsTargetLowering *createMipsSETargetLowering(MipsTargetMachine &TM);
479}
480
481#endif // MipsISELLOWERING_H
482