MipsISelLowering.h revision 544cc21cf4807116251a699d8b1d3d4bace21597
1//===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that Mips uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef MipsISELLOWERING_H 16#define MipsISELLOWERING_H 17 18#include "Mips.h" 19#include "MipsSubtarget.h" 20#include "llvm/CodeGen/CallingConvLower.h" 21#include "llvm/CodeGen/SelectionDAG.h" 22#include "llvm/Target/TargetLowering.h" 23#include <deque> 24#include <string> 25 26namespace llvm { 27 namespace MipsISD { 28 enum NodeType { 29 // Start the numbering from where ISD NodeType finishes. 30 FIRST_NUMBER = ISD::BUILTIN_OP_END, 31 32 // Jump and link (call) 33 JmpLink, 34 35 // Tail call 36 TailCall, 37 38 // Get the Higher 16 bits from a 32-bit immediate 39 // No relation with Mips Hi register 40 Hi, 41 42 // Get the Lower 16 bits from a 32-bit immediate 43 // No relation with Mips Lo register 44 Lo, 45 46 // Handle gp_rel (small data/bss sections) relocation. 47 GPRel, 48 49 // Thread Pointer 50 ThreadPointer, 51 52 // Floating Point Branch Conditional 53 FPBrcond, 54 55 // Floating Point Compare 56 FPCmp, 57 58 // Floating Point Conditional Moves 59 CMovFP_T, 60 CMovFP_F, 61 62 // Floating Point Rounding 63 FPRound, 64 65 // Return 66 Ret, 67 68 EH_RETURN, 69 70 // MAdd/Sub nodes 71 MAdd, 72 MAddu, 73 MSub, 74 MSubu, 75 76 // DivRem(u) 77 DivRem, 78 DivRemU, 79 80 BuildPairF64, 81 ExtractElementF64, 82 83 Wrapper, 84 85 DynAlloc, 86 87 Sync, 88 89 Ext, 90 Ins, 91 92 // EXTR.W instrinsic nodes. 93 EXTP, 94 EXTPDP, 95 EXTR_S_H, 96 EXTR_W, 97 EXTR_R_W, 98 EXTR_RS_W, 99 SHILO, 100 MTHLIP, 101 102 // DPA.W intrinsic nodes. 103 MULSAQ_S_W_PH, 104 MAQ_S_W_PHL, 105 MAQ_S_W_PHR, 106 MAQ_SA_W_PHL, 107 MAQ_SA_W_PHR, 108 DPAU_H_QBL, 109 DPAU_H_QBR, 110 DPSU_H_QBL, 111 DPSU_H_QBR, 112 DPAQ_S_W_PH, 113 DPSQ_S_W_PH, 114 DPAQ_SA_L_W, 115 DPSQ_SA_L_W, 116 DPA_W_PH, 117 DPS_W_PH, 118 DPAQX_S_W_PH, 119 DPAQX_SA_W_PH, 120 DPAX_W_PH, 121 DPSX_W_PH, 122 DPSQX_S_W_PH, 123 DPSQX_SA_W_PH, 124 MULSA_W_PH, 125 126 MULT, 127 MULTU, 128 MADD_DSP, 129 MADDU_DSP, 130 MSUB_DSP, 131 MSUBU_DSP, 132 133 // Load/Store Left/Right nodes. 134 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE, 135 LWR, 136 SWL, 137 SWR, 138 LDL, 139 LDR, 140 SDL, 141 SDR 142 }; 143 } 144 145 //===--------------------------------------------------------------------===// 146 // TargetLowering Implementation 147 //===--------------------------------------------------------------------===// 148 class MipsFunctionInfo; 149 150 class MipsTargetLowering : public TargetLowering { 151 public: 152 explicit MipsTargetLowering(MipsTargetMachine &TM); 153 154 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; } 155 156 virtual bool allowsUnalignedMemoryAccesses (EVT VT, bool *Fast) const; 157 158 virtual void LowerOperationWrapper(SDNode *N, 159 SmallVectorImpl<SDValue> &Results, 160 SelectionDAG &DAG) const; 161 162 /// LowerOperation - Provide custom lowering hooks for some operations. 163 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 164 165 /// ReplaceNodeResults - Replace the results of node with an illegal result 166 /// type with new values built out of custom code. 167 /// 168 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 169 SelectionDAG &DAG) const; 170 171 /// getTargetNodeName - This method returns the name of a target specific 172 // DAG node. 173 virtual const char *getTargetNodeName(unsigned Opcode) const; 174 175 /// getSetCCResultType - get the ISD::SETCC result ValueType 176 EVT getSetCCResultType(EVT VT) const; 177 178 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 179 private: 180 181 void SetMips16LibcallName(RTLIB::Libcall, const char *Name); 182 183 void setMips16HardFloatLibCalls(); 184 185 unsigned int 186 getMips16HelperFunctionStubNumber(ArgListTy &Args) const; 187 188 const char *getMips16HelperFunction 189 (Type* RetTy, ArgListTy &Args, bool &needHelper) const; 190 191 /// ByValArgInfo - Byval argument information. 192 struct ByValArgInfo { 193 unsigned FirstIdx; // Index of the first register used. 194 unsigned NumRegs; // Number of registers used for this argument. 195 unsigned Address; // Offset of the stack area used to pass this argument. 196 197 ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {} 198 }; 199 200 /// MipsCC - This class provides methods used to analyze formal and call 201 /// arguments and inquire about calling convention information. 202 class MipsCC { 203 public: 204 MipsCC(CallingConv::ID CallConv, bool IsVarArg, bool IsO32, 205 CCState &Info); 206 207 void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs); 208 void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins); 209 void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT, 210 CCValAssign::LocInfo LocInfo, 211 ISD::ArgFlagsTy ArgFlags); 212 213 const CCState &getCCInfo() const { return CCInfo; } 214 215 /// hasByValArg - Returns true if function has byval arguments. 216 bool hasByValArg() const { return !ByValArgs.empty(); } 217 218 /// useRegsForByval - Returns true if the calling convention allows the 219 /// use of registers to pass byval arguments. 220 bool useRegsForByval() const { return UseRegsForByval; } 221 222 /// regSize - Size (in number of bits) of integer registers. 223 unsigned regSize() const { return RegSize; } 224 225 /// numIntArgRegs - Number of integer registers available for calls. 226 unsigned numIntArgRegs() const { return NumIntArgRegs; } 227 228 /// reservedArgArea - The size of the area the caller reserves for 229 /// register arguments. This is 16-byte if ABI is O32. 230 unsigned reservedArgArea() const { return ReservedArgArea; } 231 232 /// intArgRegs - Pointer to array of integer registers. 233 const uint16_t *intArgRegs() const { return IntArgRegs; } 234 235 typedef SmallVector<ByValArgInfo, 2>::const_iterator byval_iterator; 236 byval_iterator byval_begin() const { return ByValArgs.begin(); } 237 byval_iterator byval_end() const { return ByValArgs.end(); } 238 239 private: 240 void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize, 241 unsigned Align); 242 243 CCState &CCInfo; 244 bool UseRegsForByval; 245 unsigned RegSize; 246 unsigned NumIntArgRegs; 247 unsigned ReservedArgArea; 248 const uint16_t *IntArgRegs, *ShadowRegs; 249 SmallVector<ByValArgInfo, 2> ByValArgs; 250 llvm::CCAssignFn *FixedFn, *VarFn; 251 }; 252 253 // Subtarget Info 254 const MipsSubtarget *Subtarget; 255 256 bool HasMips64, IsN64, IsO32; 257 258 // Lower Operand helpers 259 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 260 CallingConv::ID CallConv, bool isVarArg, 261 const SmallVectorImpl<ISD::InputArg> &Ins, 262 DebugLoc dl, SelectionDAG &DAG, 263 SmallVectorImpl<SDValue> &InVals) const; 264 265 // Lower Operand specifics 266 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 267 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 268 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 269 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 270 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 271 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 272 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 273 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 274 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 275 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; 276 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 277 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const; 278 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 279 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 280 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const; 281 SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const; 282 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const; 283 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const; 284 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG& DAG, 285 bool IsSRA) const; 286 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 287 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 288 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 289 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 290 SDValue LowerADD(SDValue Op, SelectionDAG &DAG) const; 291 292 /// IsEligibleForTailCallOptimization - Check whether the call is eligible 293 /// for tail call optimization. 294 bool IsEligibleForTailCallOptimization(const MipsCC &MipsCCInfo, 295 unsigned NextStackOffset, 296 const MipsFunctionInfo& FI) const; 297 298 /// copyByValArg - Copy argument registers which were used to pass a byval 299 /// argument to the stack. Create a stack frame object for the byval 300 /// argument. 301 void copyByValRegs(SDValue Chain, DebugLoc DL, 302 std::vector<SDValue> &OutChains, SelectionDAG &DAG, 303 const ISD::ArgFlagsTy &Flags, 304 SmallVectorImpl<SDValue> &InVals, 305 const Argument *FuncArg, 306 const MipsCC &CC, const ByValArgInfo &ByVal) const; 307 308 /// passByValArg - Pass a byval argument in registers or on stack. 309 void passByValArg(SDValue Chain, DebugLoc DL, 310 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 311 SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr, 312 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, 313 const MipsCC &CC, const ByValArgInfo &ByVal, 314 const ISD::ArgFlagsTy &Flags, bool isLittle) const; 315 316 /// writeVarArgRegs - Write variable function arguments passed in registers 317 /// to the stack. Also create a stack frame object for the first variable 318 /// argument. 319 void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC, 320 SDValue Chain, DebugLoc DL, SelectionDAG &DAG) const; 321 322 virtual SDValue 323 LowerFormalArguments(SDValue Chain, 324 CallingConv::ID CallConv, bool isVarArg, 325 const SmallVectorImpl<ISD::InputArg> &Ins, 326 DebugLoc dl, SelectionDAG &DAG, 327 SmallVectorImpl<SDValue> &InVals) const; 328 329 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain, 330 SDValue Arg, DebugLoc DL, bool IsTailCall, 331 SelectionDAG &DAG) const; 332 333 virtual SDValue 334 LowerCall(TargetLowering::CallLoweringInfo &CLI, 335 SmallVectorImpl<SDValue> &InVals) const; 336 337 virtual bool 338 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 339 bool isVarArg, 340 const SmallVectorImpl<ISD::OutputArg> &Outs, 341 LLVMContext &Context) const; 342 343 virtual SDValue 344 LowerReturn(SDValue Chain, 345 CallingConv::ID CallConv, bool isVarArg, 346 const SmallVectorImpl<ISD::OutputArg> &Outs, 347 const SmallVectorImpl<SDValue> &OutVals, 348 DebugLoc dl, SelectionDAG &DAG) const; 349 350 virtual MachineBasicBlock * 351 EmitInstrWithCustomInserter(MachineInstr *MI, 352 MachineBasicBlock *MBB) const; 353 354 // Inline asm support 355 ConstraintType getConstraintType(const std::string &Constraint) const; 356 357 /// Examine constraint string and operand type and determine a weight value. 358 /// The operand object must already have been set up with the operand type. 359 ConstraintWeight getSingleConstraintMatchWeight( 360 AsmOperandInfo &info, const char *constraint) const; 361 362 std::pair<unsigned, const TargetRegisterClass*> 363 getRegForInlineAsmConstraint(const std::string &Constraint, 364 EVT VT) const; 365 366 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 367 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 368 /// true it means one of the asm constraint of the inline asm instruction 369 /// being processed is 'm'. 370 virtual void LowerAsmOperandForConstraint(SDValue Op, 371 std::string &Constraint, 372 std::vector<SDValue> &Ops, 373 SelectionDAG &DAG) const; 374 375 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const; 376 377 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 378 379 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 380 unsigned SrcAlign, 381 bool IsMemset, bool ZeroMemset, 382 bool MemcpyStrSrc, 383 MachineFunction &MF) const; 384 385 /// isFPImmLegal - Returns true if the target can instruction select the 386 /// specified FP immediate natively. If false, the legalizer will 387 /// materialize the FP immediate as a load from a constant pool. 388 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; 389 390 virtual unsigned getJumpTableEncoding() const; 391 392 MachineBasicBlock *EmitBPOSGE32(MachineInstr *MI, 393 MachineBasicBlock *BB) const; 394 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 395 unsigned Size, unsigned BinOpcode, bool Nand = false) const; 396 MachineBasicBlock *EmitAtomicBinaryPartword(MachineInstr *MI, 397 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode, 398 bool Nand = false) const; 399 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI, 400 MachineBasicBlock *BB, unsigned Size) const; 401 MachineBasicBlock *EmitAtomicCmpSwapPartword(MachineInstr *MI, 402 MachineBasicBlock *BB, unsigned Size) const; 403 }; 404} 405 406#endif // MipsISELLOWERING_H 407