MipsISelLowering.h revision 58d1e3f72a61b5f8ace620c9e16baaecbb3f53f1 
1//===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that Mips uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef MipsISELLOWERING_H
16#define MipsISELLOWERING_H
17
18#include "Mips.h"
19#include "MipsSubtarget.h"
20#include "llvm/CodeGen/SelectionDAG.h"
21#include "llvm/Target/TargetLowering.h"
22
23namespace llvm {
24  namespace MipsISD {
25    enum NodeType {
26      // Start the numbering from where ISD NodeType finishes.
27      FIRST_NUMBER = ISD::BUILTIN_OP_END,
28
29      // Jump and link (call)
30      JmpLink,
31
32      // Tail call
33      TailCall,
34
35      // Get the Higher 16 bits from a 32-bit immediate
36      // No relation with Mips Hi register
37      Hi,
38
39      // Get the Lower 16 bits from a 32-bit immediate
40      // No relation with Mips Lo register
41      Lo,
42
43      // Handle gp_rel (small data/bss sections) relocation.
44      GPRel,
45
46      // Thread Pointer
47      ThreadPointer,
48
49      // Floating Point Branch Conditional
50      FPBrcond,
51
52      // Floating Point Compare
53      FPCmp,
54
55      // Floating Point Conditional Moves
56      CMovFP_T,
57      CMovFP_F,
58
59      // Floating Point Rounding
60      FPRound,
61
62      // Return
63      Ret,
64
65      // MAdd/Sub nodes
66      MAdd,
67      MAddu,
68      MSub,
69      MSubu,
70
71      // DivRem(u)
72      DivRem,
73      DivRemU,
74
75      BuildPairF64,
76      ExtractElementF64,
77
78      Wrapper,
79
80      DynAlloc,
81
82      Sync,
83
84      Ext,
85      Ins,
86
87      // EXTR.W instrinsic nodes.
88      EXTP,
89      EXTPDP,
90      EXTR_S_H,
91      EXTR_W,
92      EXTR_R_W,
93      EXTR_RS_W,
94      SHILO,
95      MTHLIP,
96
97      // DPA.W intrinsic nodes.
98      MULSAQ_S_W_PH,
99      MAQ_S_W_PHL,
100      MAQ_S_W_PHR,
101      MAQ_SA_W_PHL,
102      MAQ_SA_W_PHR,
103      DPAU_H_QBL,
104      DPAU_H_QBR,
105      DPSU_H_QBL,
106      DPSU_H_QBR,
107      DPAQ_S_W_PH,
108      DPSQ_S_W_PH,
109      DPAQ_SA_L_W,
110      DPSQ_SA_L_W,
111      DPA_W_PH,
112      DPS_W_PH,
113      DPAQX_S_W_PH,
114      DPAQX_SA_W_PH,
115      DPAX_W_PH,
116      DPSX_W_PH,
117      DPSQX_S_W_PH,
118      DPSQX_SA_W_PH,
119      MULSA_W_PH,
120
121      MULT,
122      MULTU,
123      MADD_DSP,
124      MADDU_DSP,
125      MSUB_DSP,
126      MSUBU_DSP,
127
128      // Load/Store Left/Right nodes.
129      LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
130      LWR,
131      SWL,
132      SWR,
133      LDL,
134      LDR,
135      SDL,
136      SDR
137    };
138  }
139
140  //===--------------------------------------------------------------------===//
141  // TargetLowering Implementation
142  //===--------------------------------------------------------------------===//
143
144  class MipsTargetLowering : public TargetLowering  {
145  public:
146    explicit MipsTargetLowering(MipsTargetMachine &TM);
147
148    virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
149
150    virtual bool allowsUnalignedMemoryAccesses (EVT VT) const;
151
152    virtual void LowerOperationWrapper(SDNode *N,
153                                       SmallVectorImpl<SDValue> &Results,
154                                       SelectionDAG &DAG) const;
155
156    /// LowerOperation - Provide custom lowering hooks for some operations.
157    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
158
159    /// ReplaceNodeResults - Replace the results of node with an illegal result
160    /// type with new values built out of custom code.
161    ///
162    virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
163                                    SelectionDAG &DAG) const;
164
165    /// getTargetNodeName - This method returns the name of a target specific
166    //  DAG node.
167    virtual const char *getTargetNodeName(unsigned Opcode) const;
168
169    /// getSetCCResultType - get the ISD::SETCC result ValueType
170    EVT getSetCCResultType(EVT VT) const;
171
172    virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
173  private:
174    // Subtarget Info
175    const MipsSubtarget *Subtarget;
176
177    bool HasMips64, IsN64, IsO32;
178
179    // Lower Operand helpers
180    SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
181                            CallingConv::ID CallConv, bool isVarArg,
182                            const SmallVectorImpl<ISD::InputArg> &Ins,
183                            DebugLoc dl, SelectionDAG &DAG,
184                            SmallVectorImpl<SDValue> &InVals) const;
185
186    // Lower Operand specifics
187    SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
188    SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
189    SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
190    SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
191    SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
192    SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
193    SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
194    SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
195    SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
196    SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
197    SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
198    SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
199    SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
200    SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
201    SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
202    SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
203    SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
204    SDValue LowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
205                                 bool IsSRA) const;
206    SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
207    SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
208    SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
209    SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
210
211    virtual SDValue
212      LowerFormalArguments(SDValue Chain,
213                           CallingConv::ID CallConv, bool isVarArg,
214                           const SmallVectorImpl<ISD::InputArg> &Ins,
215                           DebugLoc dl, SelectionDAG &DAG,
216                           SmallVectorImpl<SDValue> &InVals) const;
217
218    virtual SDValue
219      LowerCall(TargetLowering::CallLoweringInfo &CLI,
220                SmallVectorImpl<SDValue> &InVals) const;
221
222    virtual bool
223      CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
224                     bool isVarArg,
225                     const SmallVectorImpl<ISD::OutputArg> &Outs,
226                     LLVMContext &Context) const;
227
228    virtual SDValue
229      LowerReturn(SDValue Chain,
230                  CallingConv::ID CallConv, bool isVarArg,
231                  const SmallVectorImpl<ISD::OutputArg> &Outs,
232                  const SmallVectorImpl<SDValue> &OutVals,
233                  DebugLoc dl, SelectionDAG &DAG) const;
234
235    virtual MachineBasicBlock *
236      EmitInstrWithCustomInserter(MachineInstr *MI,
237                                  MachineBasicBlock *MBB) const;
238
239    // Inline asm support
240    ConstraintType getConstraintType(const std::string &Constraint) const;
241
242    /// Examine constraint string and operand type and determine a weight value.
243    /// The operand object must already have been set up with the operand type.
244    ConstraintWeight getSingleConstraintMatchWeight(
245      AsmOperandInfo &info, const char *constraint) const;
246
247    std::pair<unsigned, const TargetRegisterClass*>
248              getRegForInlineAsmConstraint(const std::string &Constraint,
249              EVT VT) const;
250
251    /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
252    /// vector.  If it is invalid, don't add anything to Ops. If hasMemory is
253    /// true it means one of the asm constraint of the inline asm instruction
254    /// being processed is 'm'.
255    virtual void LowerAsmOperandForConstraint(SDValue Op,
256                                              std::string &Constraint,
257                                              std::vector<SDValue> &Ops,
258                                              SelectionDAG &DAG) const;
259
260    virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
261
262    virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
263                                    unsigned SrcAlign, bool IsZeroVal,
264                                    bool MemcpyStrSrc,
265                                    MachineFunction &MF) const;
266
267    /// isFPImmLegal - Returns true if the target can instruction select the
268    /// specified FP immediate natively. If false, the legalizer will
269    /// materialize the FP immediate as a load from a constant pool.
270    virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
271
272    virtual unsigned getJumpTableEncoding() const;
273
274    MachineBasicBlock *EmitBPOSGE32(MachineInstr *MI,
275                                    MachineBasicBlock *BB) const;
276    MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
277                    unsigned Size, unsigned BinOpcode, bool Nand = false) const;
278    MachineBasicBlock *EmitAtomicBinaryPartword(MachineInstr *MI,
279                    MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
280                    bool Nand = false) const;
281    MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
282                                  MachineBasicBlock *BB, unsigned Size) const;
283    MachineBasicBlock *EmitAtomicCmpSwapPartword(MachineInstr *MI,
284                                  MachineBasicBlock *BB, unsigned Size) const;
285  };
286}
287
288#endif // MipsISELLOWERING_H
289