MipsISelLowering.h revision 6265d5c91a18b2fb6499eb581c488315880c044d 
1//===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that Mips uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef MipsISELLOWERING_H
16#define MipsISELLOWERING_H
17
18#include "Mips.h"
19#include "MipsSubtarget.h"
20#include "llvm/CodeGen/CallingConvLower.h"
21#include "llvm/CodeGen/SelectionDAG.h"
22#include "llvm/IR/Function.h"
23#include "llvm/Target/TargetLowering.h"
24#include <deque>
25#include <string>
26
27namespace llvm {
28  namespace MipsISD {
29    enum NodeType {
30      // Start the numbering from where ISD NodeType finishes.
31      FIRST_NUMBER = ISD::BUILTIN_OP_END,
32
33      // Jump and link (call)
34      JmpLink,
35
36      // Tail call
37      TailCall,
38
39      // Get the Higher 16 bits from a 32-bit immediate
40      // No relation with Mips Hi register
41      Hi,
42
43      // Get the Lower 16 bits from a 32-bit immediate
44      // No relation with Mips Lo register
45      Lo,
46
47      // Handle gp_rel (small data/bss sections) relocation.
48      GPRel,
49
50      // Thread Pointer
51      ThreadPointer,
52
53      // Floating Point Branch Conditional
54      FPBrcond,
55
56      // Floating Point Compare
57      FPCmp,
58
59      // Floating Point Conditional Moves
60      CMovFP_T,
61      CMovFP_F,
62
63      // Floating Point Rounding
64      FPRound,
65
66      // Return
67      Ret,
68
69      EH_RETURN,
70
71      // Node used to extract integer from accumulator.
72      ExtractLOHI,
73
74      // Node used to insert integers to accumulator.
75      InsertLOHI,
76
77      // Mult nodes.
78      Mult,
79      Multu,
80
81      // MAdd/Sub nodes
82      MAdd,
83      MAddu,
84      MSub,
85      MSubu,
86
87      // DivRem(u)
88      DivRem,
89      DivRemU,
90      DivRem16,
91      DivRemU16,
92
93      BuildPairF64,
94      ExtractElementF64,
95
96      Wrapper,
97
98      DynAlloc,
99
100      Sync,
101
102      Ext,
103      Ins,
104
105      // EXTR.W instrinsic nodes.
106      EXTP,
107      EXTPDP,
108      EXTR_S_H,
109      EXTR_W,
110      EXTR_R_W,
111      EXTR_RS_W,
112      SHILO,
113      MTHLIP,
114
115      // DPA.W intrinsic nodes.
116      MULSAQ_S_W_PH,
117      MAQ_S_W_PHL,
118      MAQ_S_W_PHR,
119      MAQ_SA_W_PHL,
120      MAQ_SA_W_PHR,
121      DPAU_H_QBL,
122      DPAU_H_QBR,
123      DPSU_H_QBL,
124      DPSU_H_QBR,
125      DPAQ_S_W_PH,
126      DPSQ_S_W_PH,
127      DPAQ_SA_L_W,
128      DPSQ_SA_L_W,
129      DPA_W_PH,
130      DPS_W_PH,
131      DPAQX_S_W_PH,
132      DPAQX_SA_W_PH,
133      DPAX_W_PH,
134      DPSX_W_PH,
135      DPSQX_S_W_PH,
136      DPSQX_SA_W_PH,
137      MULSA_W_PH,
138
139      MULT,
140      MULTU,
141      MADD_DSP,
142      MADDU_DSP,
143      MSUB_DSP,
144      MSUBU_DSP,
145
146      // DSP shift nodes.
147      SHLL_DSP,
148      SHRA_DSP,
149      SHRL_DSP,
150
151      // Load/Store Left/Right nodes.
152      LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
153      LWR,
154      SWL,
155      SWR,
156      LDL,
157      LDR,
158      SDL,
159      SDR
160    };
161  }
162
163  //===--------------------------------------------------------------------===//
164  // TargetLowering Implementation
165  //===--------------------------------------------------------------------===//
166  class MipsFunctionInfo;
167
168  class MipsTargetLowering : public TargetLowering  {
169  public:
170    explicit MipsTargetLowering(MipsTargetMachine &TM);
171
172    static const MipsTargetLowering *create(MipsTargetMachine &TM);
173
174    virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
175
176    virtual void LowerOperationWrapper(SDNode *N,
177                                       SmallVectorImpl<SDValue> &Results,
178                                       SelectionDAG &DAG) const;
179
180    /// LowerOperation - Provide custom lowering hooks for some operations.
181    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
182
183    /// ReplaceNodeResults - Replace the results of node with an illegal result
184    /// type with new values built out of custom code.
185    ///
186    virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
187                                    SelectionDAG &DAG) const;
188
189    /// getTargetNodeName - This method returns the name of a target specific
190    //  DAG node.
191    virtual const char *getTargetNodeName(unsigned Opcode) const;
192
193    /// getSetCCResultType - get the ISD::SETCC result ValueType
194    EVT getSetCCResultType(EVT VT) const;
195
196    virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
197
198    virtual MachineBasicBlock *
199    EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
200
201    struct LTStr {
202      bool operator()(const char *S1, const char *S2) const {
203        return strcmp(S1, S2) < 0;
204      }
205    };
206
207  protected:
208    SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
209
210    SDValue getAddrLocal(SDValue Op, SelectionDAG &DAG, bool HasMips64) const;
211
212    SDValue getAddrGlobal(SDValue Op, SelectionDAG &DAG, unsigned Flag) const;
213
214    SDValue getAddrGlobalLargeGOT(SDValue Op, SelectionDAG &DAG,
215                                  unsigned HiFlag, unsigned LoFlag) const;
216
217    /// This function fills Ops, which is the list of operands that will later
218    /// be used when a function call node is created. It also generates
219    /// copyToReg nodes to set up argument registers.
220    virtual void
221    getOpndList(SmallVectorImpl<SDValue> &Ops,
222                std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
223                bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
224                CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
225
226    /// ByValArgInfo - Byval argument information.
227    struct ByValArgInfo {
228      unsigned FirstIdx; // Index of the first register used.
229      unsigned NumRegs;  // Number of registers used for this argument.
230      unsigned Address;  // Offset of the stack area used to pass this argument.
231
232      ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
233    };
234
235    /// MipsCC - This class provides methods used to analyze formal and call
236    /// arguments and inquire about calling convention information.
237    class MipsCC {
238    public:
239      MipsCC(CallingConv::ID CallConv, bool IsO32, CCState &Info);
240
241      void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
242                               bool IsVarArg, bool IsSoftFloat,
243                               const SDNode *CallNode,
244                               std::vector<ArgListEntry> &FuncArgs);
245      void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
246                                  bool IsSoftFloat,
247                                  Function::const_arg_iterator FuncArg);
248
249      void analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
250                             bool IsSoftFloat, const SDNode *CallNode,
251                             const Type *RetTy) const;
252
253      void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
254                         bool IsSoftFloat, const Type *RetTy) const;
255
256      const CCState &getCCInfo() const { return CCInfo; }
257
258      /// hasByValArg - Returns true if function has byval arguments.
259      bool hasByValArg() const { return !ByValArgs.empty(); }
260
261      /// regSize - Size (in number of bits) of integer registers.
262      unsigned regSize() const { return IsO32 ? 4 : 8; }
263
264      /// numIntArgRegs - Number of integer registers available for calls.
265      unsigned numIntArgRegs() const;
266
267      /// reservedArgArea - The size of the area the caller reserves for
268      /// register arguments. This is 16-byte if ABI is O32.
269      unsigned reservedArgArea() const;
270
271      /// Return pointer to array of integer argument registers.
272      const uint16_t *intArgRegs() const;
273
274      typedef SmallVector<ByValArgInfo, 2>::const_iterator byval_iterator;
275      byval_iterator byval_begin() const { return ByValArgs.begin(); }
276      byval_iterator byval_end() const { return ByValArgs.end(); }
277
278    private:
279      void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
280                          CCValAssign::LocInfo LocInfo,
281                          ISD::ArgFlagsTy ArgFlags);
282
283      /// useRegsForByval - Returns true if the calling convention allows the
284      /// use of registers to pass byval arguments.
285      bool useRegsForByval() const { return CallConv != CallingConv::Fast; }
286
287      /// Return the function that analyzes fixed argument list functions.
288      llvm::CCAssignFn *fixedArgFn() const;
289
290      /// Return the function that analyzes variable argument list functions.
291      llvm::CCAssignFn *varArgFn() const;
292
293      const uint16_t *shadowRegs() const;
294
295      void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
296                        unsigned Align);
297
298      /// Return the type of the register which is used to pass an argument or
299      /// return a value. This function returns f64 if the argument is an i64
300      /// value which has been generated as a result of softening an f128 value.
301      /// Otherwise, it just returns VT.
302      MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode,
303                   bool IsSoftFloat) const;
304
305      template<typename Ty>
306      void analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat,
307                         const SDNode *CallNode, const Type *RetTy) const;
308
309      CCState &CCInfo;
310      CallingConv::ID CallConv;
311      bool IsO32;
312      SmallVector<ByValArgInfo, 2> ByValArgs;
313    };
314
315    // Subtarget Info
316    const MipsSubtarget *Subtarget;
317
318    bool HasMips64, IsN64, IsO32;
319
320  private:
321    // Lower Operand helpers
322    SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
323                            CallingConv::ID CallConv, bool isVarArg,
324                            const SmallVectorImpl<ISD::InputArg> &Ins,
325                            DebugLoc dl, SelectionDAG &DAG,
326                            SmallVectorImpl<SDValue> &InVals,
327                            const SDNode *CallNode, const Type *RetTy) const;
328
329    // Lower Operand specifics
330    SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
331    SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
332    SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
333    SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
334    SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
335    SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
336    SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
337    SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
338    SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
339    SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
340    SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
341    SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
342    SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
343    SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
344    SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
345    SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
346    SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
347    SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
348    SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
349                                 bool IsSRA) const;
350    SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
351    SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
352    SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
353
354    /// isEligibleForTailCallOptimization - Check whether the call is eligible
355    /// for tail call optimization.
356    virtual bool
357    isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
358                                      unsigned NextStackOffset,
359                                      const MipsFunctionInfo& FI) const = 0;
360
361    /// copyByValArg - Copy argument registers which were used to pass a byval
362    /// argument to the stack. Create a stack frame object for the byval
363    /// argument.
364    void copyByValRegs(SDValue Chain, DebugLoc DL,
365                       std::vector<SDValue> &OutChains, SelectionDAG &DAG,
366                       const ISD::ArgFlagsTy &Flags,
367                       SmallVectorImpl<SDValue> &InVals,
368                       const Argument *FuncArg,
369                       const MipsCC &CC, const ByValArgInfo &ByVal) const;
370
371    /// passByValArg - Pass a byval argument in registers or on stack.
372    void passByValArg(SDValue Chain, DebugLoc DL,
373                      std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
374                      SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr,
375                      MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
376                      const MipsCC &CC, const ByValArgInfo &ByVal,
377                      const ISD::ArgFlagsTy &Flags, bool isLittle) const;
378
379    /// writeVarArgRegs - Write variable function arguments passed in registers
380    /// to the stack. Also create a stack frame object for the first variable
381    /// argument.
382    void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
383                         SDValue Chain, DebugLoc DL, SelectionDAG &DAG) const;
384
385    virtual SDValue
386      LowerFormalArguments(SDValue Chain,
387                           CallingConv::ID CallConv, bool isVarArg,
388                           const SmallVectorImpl<ISD::InputArg> &Ins,
389                           DebugLoc dl, SelectionDAG &DAG,
390                           SmallVectorImpl<SDValue> &InVals) const;
391
392    SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
393                           SDValue Arg, DebugLoc DL, bool IsTailCall,
394                           SelectionDAG &DAG) const;
395
396    virtual SDValue
397      LowerCall(TargetLowering::CallLoweringInfo &CLI,
398                SmallVectorImpl<SDValue> &InVals) const;
399
400    virtual bool
401      CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
402                     bool isVarArg,
403                     const SmallVectorImpl<ISD::OutputArg> &Outs,
404                     LLVMContext &Context) const;
405
406    virtual SDValue
407      LowerReturn(SDValue Chain,
408                  CallingConv::ID CallConv, bool isVarArg,
409                  const SmallVectorImpl<ISD::OutputArg> &Outs,
410                  const SmallVectorImpl<SDValue> &OutVals,
411                  DebugLoc dl, SelectionDAG &DAG) const;
412
413    // Inline asm support
414    ConstraintType getConstraintType(const std::string &Constraint) const;
415
416    /// Examine constraint string and operand type and determine a weight value.
417    /// The operand object must already have been set up with the operand type.
418    ConstraintWeight getSingleConstraintMatchWeight(
419      AsmOperandInfo &info, const char *constraint) const;
420
421    std::pair<unsigned, const TargetRegisterClass*>
422              getRegForInlineAsmConstraint(const std::string &Constraint,
423              EVT VT) const;
424
425    /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
426    /// vector.  If it is invalid, don't add anything to Ops. If hasMemory is
427    /// true it means one of the asm constraint of the inline asm instruction
428    /// being processed is 'm'.
429    virtual void LowerAsmOperandForConstraint(SDValue Op,
430                                              std::string &Constraint,
431                                              std::vector<SDValue> &Ops,
432                                              SelectionDAG &DAG) const;
433
434    virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
435
436    virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
437
438    virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
439                                    unsigned SrcAlign,
440                                    bool IsMemset, bool ZeroMemset,
441                                    bool MemcpyStrSrc,
442                                    MachineFunction &MF) const;
443
444    /// isFPImmLegal - Returns true if the target can instruction select the
445    /// specified FP immediate natively. If false, the legalizer will
446    /// materialize the FP immediate as a load from a constant pool.
447    virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
448
449    virtual unsigned getJumpTableEncoding() const;
450
451    MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
452                    unsigned Size, unsigned BinOpcode, bool Nand = false) const;
453    MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
454                    MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
455                    bool Nand = false) const;
456    MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
457                                  MachineBasicBlock *BB, unsigned Size) const;
458    MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
459                                  MachineBasicBlock *BB, unsigned Size) const;
460  };
461
462  /// Create MipsTargetLowering objects.
463  const MipsTargetLowering *createMips16TargetLowering(MipsTargetMachine &TM);
464  const MipsTargetLowering *createMipsSETargetLowering(MipsTargetMachine &TM);
465}
466
467#endif // MipsISELLOWERING_H
468