MipsISelLowering.h revision 69b9044c668dfb92038385a96c030778de64edfd 
1//===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that Mips uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef MipsISELLOWERING_H
16#define MipsISELLOWERING_H
17
18#include "llvm/CodeGen/SelectionDAG.h"
19#include "llvm/Target/TargetLowering.h"
20#include "Mips.h"
21#include "MipsSubtarget.h"
22
23namespace llvm {
24  namespace MipsISD {
25    enum NodeType {
26      // Start the numbering from where ISD NodeType finishes.
27      FIRST_NUMBER = ISD::BUILTIN_OP_END,
28
29      // Jump and link (call)
30      JmpLink,
31
32      // Get the Higher 16 bits from a 32-bit immediate
33      // No relation with Mips Hi register
34      Hi,
35
36      // Get the Lower 16 bits from a 32-bit immediate
37      // No relation with Mips Lo register
38      Lo,
39
40      // Handle gp_rel (small data/bss sections) relocation.
41      GPRel,
42
43      // General Dynamic TLS
44      TlsGd,
45
46      // Local Exec TLS
47      TprelHi,
48      TprelLo,
49
50      // Thread Pointer
51      ThreadPointer,
52
53      // Floating Point Branch Conditional
54      FPBrcond,
55
56      // Floating Point Compare
57      FPCmp,
58
59      // Floating Point Conditional Moves
60      CMovFP_T,
61      CMovFP_F,
62
63      // Floating Point Rounding
64      FPRound,
65
66      // Return
67      Ret,
68
69      // MAdd/Sub nodes
70      MAdd,
71      MAddu,
72      MSub,
73      MSubu,
74
75      // DivRem(u)
76      DivRem,
77      DivRemU,
78
79      BuildPairF64,
80      ExtractElementF64,
81
82      WrapperPIC,
83
84      DynAlloc
85    };
86  }
87
88  //===--------------------------------------------------------------------===//
89  // TargetLowering Implementation
90  //===--------------------------------------------------------------------===//
91
92  class MipsTargetLowering : public TargetLowering  {
93  public:
94    explicit MipsTargetLowering(MipsTargetMachine &TM);
95
96    /// LowerOperation - Provide custom lowering hooks for some operations.
97    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
98
99    /// getTargetNodeName - This method returns the name of a target specific
100    //  DAG node.
101    virtual const char *getTargetNodeName(unsigned Opcode) const;
102
103    /// getSetCCResultType - get the ISD::SETCC result ValueType
104    MVT::SimpleValueType getSetCCResultType(EVT VT) const;
105
106    virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
107  private:
108    // Subtarget Info
109    const MipsSubtarget *Subtarget;
110
111
112    // Lower Operand helpers
113    SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
114                            CallingConv::ID CallConv, bool isVarArg,
115                            const SmallVectorImpl<ISD::InputArg> &Ins,
116                            DebugLoc dl, SelectionDAG &DAG,
117                            SmallVectorImpl<SDValue> &InVals) const;
118
119    // Lower Operand specifics
120    SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
121    SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
122    SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
123    SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
124    SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
125    SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
126    SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
127    SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
128    SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
129    SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
130    SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
131
132    virtual SDValue
133      LowerFormalArguments(SDValue Chain,
134                           CallingConv::ID CallConv, bool isVarArg,
135                           const SmallVectorImpl<ISD::InputArg> &Ins,
136                           DebugLoc dl, SelectionDAG &DAG,
137                           SmallVectorImpl<SDValue> &InVals) const;
138
139    virtual SDValue
140      LowerCall(SDValue Chain, SDValue Callee,
141                CallingConv::ID CallConv, bool isVarArg,
142                bool &isTailCall,
143                const SmallVectorImpl<ISD::OutputArg> &Outs,
144                const SmallVectorImpl<SDValue> &OutVals,
145                const SmallVectorImpl<ISD::InputArg> &Ins,
146                DebugLoc dl, SelectionDAG &DAG,
147                SmallVectorImpl<SDValue> &InVals) const;
148
149    virtual SDValue
150      LowerReturn(SDValue Chain,
151                  CallingConv::ID CallConv, bool isVarArg,
152                  const SmallVectorImpl<ISD::OutputArg> &Outs,
153                  const SmallVectorImpl<SDValue> &OutVals,
154                  DebugLoc dl, SelectionDAG &DAG) const;
155
156    virtual MachineBasicBlock *
157      EmitInstrWithCustomInserter(MachineInstr *MI,
158                                  MachineBasicBlock *MBB) const;
159
160    // Inline asm support
161    ConstraintType getConstraintType(const std::string &Constraint) const;
162
163    /// Examine constraint string and operand type and determine a weight value.
164    /// The operand object must already have been set up with the operand type.
165    ConstraintWeight getSingleConstraintMatchWeight(
166      AsmOperandInfo &info, const char *constraint) const;
167
168    std::pair<unsigned, const TargetRegisterClass*>
169              getRegForInlineAsmConstraint(const std::string &Constraint,
170              EVT VT) const;
171
172    std::vector<unsigned>
173    getRegClassForInlineAsmConstraint(const std::string &Constraint,
174              EVT VT) const;
175
176    virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
177
178    /// isFPImmLegal - Returns true if the target can instruction select the
179    /// specified FP immediate natively. If false, the legalizer will
180    /// materialize the FP immediate as a load from a constant pool.
181    virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
182
183    MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
184                    unsigned Size, unsigned BinOpcode, bool Nand = false) const;
185    MachineBasicBlock *EmitAtomicBinaryPartword(MachineInstr *MI,
186                    MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
187                    bool Nand = false) const;
188    MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
189                                  MachineBasicBlock *BB, unsigned Size) const;
190    MachineBasicBlock *EmitAtomicCmpSwapPartword(MachineInstr *MI,
191                                  MachineBasicBlock *BB, unsigned Size) const;
192  };
193}
194
195#endif // MipsISELLOWERING_H
196