MipsISelLowering.h revision 6ff59a16a05d43fdda587ce600b5b42a63cf3d33 
1//===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that Mips uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef MipsISELLOWERING_H
16#define MipsISELLOWERING_H
17
18#include "Mips.h"
19#include "MipsSubtarget.h"
20#include "MCTargetDesc/MipsBaseInfo.h"
21#include "llvm/CodeGen/CallingConvLower.h"
22#include "llvm/CodeGen/SelectionDAG.h"
23#include "llvm/IR/Function.h"
24#include "llvm/Target/TargetLowering.h"
25#include <deque>
26#include <string>
27
28namespace llvm {
29  namespace MipsISD {
30    enum NodeType {
31      // Start the numbering from where ISD NodeType finishes.
32      FIRST_NUMBER = ISD::BUILTIN_OP_END,
33
34      // Jump and link (call)
35      JmpLink,
36
37      // Tail call
38      TailCall,
39
40      // Get the Higher 16 bits from a 32-bit immediate
41      // No relation with Mips Hi register
42      Hi,
43
44      // Get the Lower 16 bits from a 32-bit immediate
45      // No relation with Mips Lo register
46      Lo,
47
48      // Handle gp_rel (small data/bss sections) relocation.
49      GPRel,
50
51      // Thread Pointer
52      ThreadPointer,
53
54      // Floating Point Branch Conditional
55      FPBrcond,
56
57      // Floating Point Compare
58      FPCmp,
59
60      // Floating Point Conditional Moves
61      CMovFP_T,
62      CMovFP_F,
63
64      // FP-to-int truncation node.
65      TruncIntFP,
66
67      // Return
68      Ret,
69
70      EH_RETURN,
71
72      // Node used to extract integer from accumulator.
73      ExtractLOHI,
74
75      // Node used to insert integers to accumulator.
76      InsertLOHI,
77
78      // Mult nodes.
79      Mult,
80      Multu,
81
82      // MAdd/Sub nodes
83      MAdd,
84      MAddu,
85      MSub,
86      MSubu,
87
88      // DivRem(u)
89      DivRem,
90      DivRemU,
91      DivRem16,
92      DivRemU16,
93
94      BuildPairF64,
95      ExtractElementF64,
96
97      Wrapper,
98
99      DynAlloc,
100
101      Sync,
102
103      Ext,
104      Ins,
105
106      // EXTR.W instrinsic nodes.
107      EXTP,
108      EXTPDP,
109      EXTR_S_H,
110      EXTR_W,
111      EXTR_R_W,
112      EXTR_RS_W,
113      SHILO,
114      MTHLIP,
115
116      // DPA.W intrinsic nodes.
117      MULSAQ_S_W_PH,
118      MAQ_S_W_PHL,
119      MAQ_S_W_PHR,
120      MAQ_SA_W_PHL,
121      MAQ_SA_W_PHR,
122      DPAU_H_QBL,
123      DPAU_H_QBR,
124      DPSU_H_QBL,
125      DPSU_H_QBR,
126      DPAQ_S_W_PH,
127      DPSQ_S_W_PH,
128      DPAQ_SA_L_W,
129      DPSQ_SA_L_W,
130      DPA_W_PH,
131      DPS_W_PH,
132      DPAQX_S_W_PH,
133      DPAQX_SA_W_PH,
134      DPAX_W_PH,
135      DPSX_W_PH,
136      DPSQX_S_W_PH,
137      DPSQX_SA_W_PH,
138      MULSA_W_PH,
139
140      MULT,
141      MULTU,
142      MADD_DSP,
143      MADDU_DSP,
144      MSUB_DSP,
145      MSUBU_DSP,
146
147      // DSP shift nodes.
148      SHLL_DSP,
149      SHRA_DSP,
150      SHRL_DSP,
151
152      // DSP setcc and select_cc nodes.
153      SETCC_DSP,
154      SELECT_CC_DSP,
155
156      // Vector comparisons.
157      // These take a vector and return a boolean.
158      VALL_ZERO,
159      VANY_ZERO,
160      VALL_NONZERO,
161      VANY_NONZERO,
162
163      // These take a vector and return a vector bitmask.
164      VCEQ,
165      VCLE_S,
166      VCLE_U,
167      VCLT_S,
168      VCLT_U,
169
170      // Element-wise vector max/min.
171      VSMAX,
172      VSMIN,
173      VUMAX,
174      VUMIN,
175
176      // Vector Shuffle with mask as an operand
177      VSHF,  // Generic shuffle
178      SHF,   // 4-element set shuffle.
179      ILVEV, // Interleave even elements
180      ILVOD, // Interleave odd elements
181      ILVL,  // Interleave left elements
182      ILVR,  // Interleave right elements
183      PCKEV, // Pack even elements
184      PCKOD, // Pack odd elements
185
186      // Combined (XOR (OR $a, $b), -1)
187      VNOR,
188
189      // Extended vector element extraction
190      VEXTRACT_SEXT_ELT,
191      VEXTRACT_ZEXT_ELT,
192
193      // Load/Store Left/Right nodes.
194      LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
195      LWR,
196      SWL,
197      SWR,
198      LDL,
199      LDR,
200      SDL,
201      SDR
202    };
203  }
204
205  //===--------------------------------------------------------------------===//
206  // TargetLowering Implementation
207  //===--------------------------------------------------------------------===//
208  class MipsFunctionInfo;
209
210  class MipsTargetLowering : public TargetLowering  {
211  public:
212    explicit MipsTargetLowering(MipsTargetMachine &TM);
213
214    static const MipsTargetLowering *create(MipsTargetMachine &TM);
215
216    virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
217
218    virtual void LowerOperationWrapper(SDNode *N,
219                                       SmallVectorImpl<SDValue> &Results,
220                                       SelectionDAG &DAG) const;
221
222    /// LowerOperation - Provide custom lowering hooks for some operations.
223    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
224
225    /// ReplaceNodeResults - Replace the results of node with an illegal result
226    /// type with new values built out of custom code.
227    ///
228    virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
229                                    SelectionDAG &DAG) const;
230
231    /// getTargetNodeName - This method returns the name of a target specific
232    //  DAG node.
233    virtual const char *getTargetNodeName(unsigned Opcode) const;
234
235    /// getSetCCResultType - get the ISD::SETCC result ValueType
236    EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
237
238    virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
239
240    virtual MachineBasicBlock *
241    EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
242
243    struct LTStr {
244      bool operator()(const char *S1, const char *S2) const {
245        return strcmp(S1, S2) < 0;
246      }
247    };
248
249  protected:
250    SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
251
252    // This method creates the following nodes, which are necessary for
253    // computing a local symbol's address:
254    //
255    // (add (load (wrapper $gp, %got(sym)), %lo(sym))
256    template<class NodeTy>
257    SDValue getAddrLocal(NodeTy *N, EVT Ty, SelectionDAG &DAG,
258                         bool HasMips64) const {
259      SDLoc DL(N);
260      unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
261      SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
262                                getTargetNode(N, Ty, DAG, GOTFlag));
263      SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
264                                 MachinePointerInfo::getGOT(), false, false,
265                                 false, 0);
266      unsigned LoFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
267      SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
268                               getTargetNode(N, Ty, DAG, LoFlag));
269      return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
270    }
271
272    // This method creates the following nodes, which are necessary for
273    // computing a global symbol's address:
274    //
275    // (load (wrapper $gp, %got(sym)))
276    template<class NodeTy>
277    SDValue getAddrGlobal(NodeTy *N, EVT Ty, SelectionDAG &DAG,
278                          unsigned Flag, SDValue Chain,
279                          const MachinePointerInfo &PtrInfo) const {
280      SDLoc DL(N);
281      SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
282                                getTargetNode(N, Ty, DAG, Flag));
283      return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo, false, false, false, 0);
284    }
285
286    // This method creates the following nodes, which are necessary for
287    // computing a global symbol's address in large-GOT mode:
288    //
289    // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
290    template<class NodeTy>
291    SDValue getAddrGlobalLargeGOT(NodeTy *N, EVT Ty, SelectionDAG &DAG,
292                                  unsigned HiFlag, unsigned LoFlag,
293                                  SDValue Chain,
294                                  const MachinePointerInfo &PtrInfo) const {
295      SDLoc DL(N);
296      SDValue Hi = DAG.getNode(MipsISD::Hi, DL, Ty,
297                               getTargetNode(N, Ty, DAG, HiFlag));
298      Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
299      SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
300                                    getTargetNode(N, Ty, DAG, LoFlag));
301      return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo, false, false, false,
302                         0);
303    }
304
305    // This method creates the following nodes, which are necessary for
306    // computing a symbol's address in non-PIC mode:
307    //
308    // (add %hi(sym), %lo(sym))
309    template<class NodeTy>
310    SDValue getAddrNonPIC(NodeTy *N, EVT Ty, SelectionDAG &DAG) const {
311      SDLoc DL(N);
312      SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
313      SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
314      return DAG.getNode(ISD::ADD, DL, Ty,
315                         DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
316                         DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
317    }
318
319    /// This function fills Ops, which is the list of operands that will later
320    /// be used when a function call node is created. It also generates
321    /// copyToReg nodes to set up argument registers.
322    virtual void
323    getOpndList(SmallVectorImpl<SDValue> &Ops,
324                std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
325                bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
326                CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
327
328    /// ByValArgInfo - Byval argument information.
329    struct ByValArgInfo {
330      unsigned FirstIdx; // Index of the first register used.
331      unsigned NumRegs;  // Number of registers used for this argument.
332      unsigned Address;  // Offset of the stack area used to pass this argument.
333
334      ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
335    };
336
337    /// MipsCC - This class provides methods used to analyze formal and call
338    /// arguments and inquire about calling convention information.
339    class MipsCC {
340    public:
341      enum SpecialCallingConvType {
342        Mips16RetHelperConv, NoSpecialCallingConv
343      };
344
345      MipsCC(CallingConv::ID CallConv, bool IsO32, bool IsFP64, CCState &Info,
346             SpecialCallingConvType SpecialCallingConv = NoSpecialCallingConv);
347
348
349      void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
350                               bool IsVarArg, bool IsSoftFloat,
351                               const SDNode *CallNode,
352                               std::vector<ArgListEntry> &FuncArgs);
353      void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
354                                  bool IsSoftFloat,
355                                  Function::const_arg_iterator FuncArg);
356
357      void analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
358                             bool IsSoftFloat, const SDNode *CallNode,
359                             const Type *RetTy) const;
360
361      void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
362                         bool IsSoftFloat, const Type *RetTy) const;
363
364      const CCState &getCCInfo() const { return CCInfo; }
365
366      /// hasByValArg - Returns true if function has byval arguments.
367      bool hasByValArg() const { return !ByValArgs.empty(); }
368
369      /// regSize - Size (in number of bits) of integer registers.
370      unsigned regSize() const { return IsO32 ? 4 : 8; }
371
372      /// numIntArgRegs - Number of integer registers available for calls.
373      unsigned numIntArgRegs() const;
374
375      /// reservedArgArea - The size of the area the caller reserves for
376      /// register arguments. This is 16-byte if ABI is O32.
377      unsigned reservedArgArea() const;
378
379      /// Return pointer to array of integer argument registers.
380      const uint16_t *intArgRegs() const;
381
382      typedef SmallVectorImpl<ByValArgInfo>::const_iterator byval_iterator;
383      byval_iterator byval_begin() const { return ByValArgs.begin(); }
384      byval_iterator byval_end() const { return ByValArgs.end(); }
385
386    private:
387      void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
388                          CCValAssign::LocInfo LocInfo,
389                          ISD::ArgFlagsTy ArgFlags);
390
391      /// useRegsForByval - Returns true if the calling convention allows the
392      /// use of registers to pass byval arguments.
393      bool useRegsForByval() const { return CallConv != CallingConv::Fast; }
394
395      /// Return the function that analyzes fixed argument list functions.
396      llvm::CCAssignFn *fixedArgFn() const;
397
398      /// Return the function that analyzes variable argument list functions.
399      llvm::CCAssignFn *varArgFn() const;
400
401      const uint16_t *shadowRegs() const;
402
403      void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
404                        unsigned Align);
405
406      /// Return the type of the register which is used to pass an argument or
407      /// return a value. This function returns f64 if the argument is an i64
408      /// value which has been generated as a result of softening an f128 value.
409      /// Otherwise, it just returns VT.
410      MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode,
411                   bool IsSoftFloat) const;
412
413      template<typename Ty>
414      void analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat,
415                         const SDNode *CallNode, const Type *RetTy) const;
416
417      CCState &CCInfo;
418      CallingConv::ID CallConv;
419      bool IsO32, IsFP64;
420      SpecialCallingConvType SpecialCallingConv;
421      SmallVector<ByValArgInfo, 2> ByValArgs;
422    };
423  protected:
424    SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
425    SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
426
427    // Subtarget Info
428    const MipsSubtarget *Subtarget;
429
430    bool HasMips64, IsN64, IsO32;
431
432  private:
433    // Create a TargetGlobalAddress node.
434    SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
435                          unsigned Flag) const;
436
437    // Create a TargetExternalSymbol node.
438    SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG,
439                          unsigned Flag) const;
440
441    // Create a TargetBlockAddress node.
442    SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
443                          unsigned Flag) const;
444
445    // Create a TargetJumpTable node.
446    SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
447                          unsigned Flag) const;
448
449    // Create a TargetConstantPool node.
450    SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
451                          unsigned Flag) const;
452
453    MipsCC::SpecialCallingConvType getSpecialCallingConv(SDValue Callee) const;
454    // Lower Operand helpers
455    SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
456                            CallingConv::ID CallConv, bool isVarArg,
457                            const SmallVectorImpl<ISD::InputArg> &Ins,
458                            SDLoc dl, SelectionDAG &DAG,
459                            SmallVectorImpl<SDValue> &InVals,
460                            const SDNode *CallNode, const Type *RetTy) const;
461
462    // Lower Operand specifics
463    SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
464    SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
465    SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
466    SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
467    SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
468    SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
469    SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
470    SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
471    SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
472    SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
473    SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
474    SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
475    SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
476    SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
477    SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
478    SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
479    SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
480    SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
481    SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
482                                 bool IsSRA) const;
483    SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
484    SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
485
486    /// isEligibleForTailCallOptimization - Check whether the call is eligible
487    /// for tail call optimization.
488    virtual bool
489    isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
490                                      unsigned NextStackOffset,
491                                      const MipsFunctionInfo& FI) const = 0;
492
493    /// copyByValArg - Copy argument registers which were used to pass a byval
494    /// argument to the stack. Create a stack frame object for the byval
495    /// argument.
496    void copyByValRegs(SDValue Chain, SDLoc DL,
497                       std::vector<SDValue> &OutChains, SelectionDAG &DAG,
498                       const ISD::ArgFlagsTy &Flags,
499                       SmallVectorImpl<SDValue> &InVals,
500                       const Argument *FuncArg,
501                       const MipsCC &CC, const ByValArgInfo &ByVal) const;
502
503    /// passByValArg - Pass a byval argument in registers or on stack.
504    void passByValArg(SDValue Chain, SDLoc DL,
505                      std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
506                      SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
507                      MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
508                      const MipsCC &CC, const ByValArgInfo &ByVal,
509                      const ISD::ArgFlagsTy &Flags, bool isLittle) const;
510
511    /// writeVarArgRegs - Write variable function arguments passed in registers
512    /// to the stack. Also create a stack frame object for the first variable
513    /// argument.
514    void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
515                         SDValue Chain, SDLoc DL, SelectionDAG &DAG) const;
516
517    virtual SDValue
518      LowerFormalArguments(SDValue Chain,
519                           CallingConv::ID CallConv, bool isVarArg,
520                           const SmallVectorImpl<ISD::InputArg> &Ins,
521                           SDLoc dl, SelectionDAG &DAG,
522                           SmallVectorImpl<SDValue> &InVals) const;
523
524    SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
525                           SDValue Arg, SDLoc DL, bool IsTailCall,
526                           SelectionDAG &DAG) const;
527
528    virtual SDValue
529      LowerCall(TargetLowering::CallLoweringInfo &CLI,
530                SmallVectorImpl<SDValue> &InVals) const;
531
532    virtual bool
533      CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
534                     bool isVarArg,
535                     const SmallVectorImpl<ISD::OutputArg> &Outs,
536                     LLVMContext &Context) const;
537
538    virtual SDValue
539      LowerReturn(SDValue Chain,
540                  CallingConv::ID CallConv, bool isVarArg,
541                  const SmallVectorImpl<ISD::OutputArg> &Outs,
542                  const SmallVectorImpl<SDValue> &OutVals,
543                  SDLoc dl, SelectionDAG &DAG) const;
544
545    // Inline asm support
546    ConstraintType getConstraintType(const std::string &Constraint) const;
547
548    /// Examine constraint string and operand type and determine a weight value.
549    /// The operand object must already have been set up with the operand type.
550    ConstraintWeight getSingleConstraintMatchWeight(
551      AsmOperandInfo &info, const char *constraint) const;
552
553    /// This function parses registers that appear in inline-asm constraints.
554    /// It returns pair (0, 0) on failure.
555    std::pair<unsigned, const TargetRegisterClass *>
556    parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const;
557
558    std::pair<unsigned, const TargetRegisterClass*>
559              getRegForInlineAsmConstraint(const std::string &Constraint,
560                                           MVT VT) const;
561
562    /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
563    /// vector.  If it is invalid, don't add anything to Ops. If hasMemory is
564    /// true it means one of the asm constraint of the inline asm instruction
565    /// being processed is 'm'.
566    virtual void LowerAsmOperandForConstraint(SDValue Op,
567                                              std::string &Constraint,
568                                              std::vector<SDValue> &Ops,
569                                              SelectionDAG &DAG) const;
570
571    virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
572
573    virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
574
575    virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
576                                    unsigned SrcAlign,
577                                    bool IsMemset, bool ZeroMemset,
578                                    bool MemcpyStrSrc,
579                                    MachineFunction &MF) const;
580
581    /// isFPImmLegal - Returns true if the target can instruction select the
582    /// specified FP immediate natively. If false, the legalizer will
583    /// materialize the FP immediate as a load from a constant pool.
584    virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
585
586    virtual unsigned getJumpTableEncoding() const;
587
588    MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
589                    unsigned Size, unsigned BinOpcode, bool Nand = false) const;
590    MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
591                    MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
592                    bool Nand = false) const;
593    MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
594                                  MachineBasicBlock *BB, unsigned Size) const;
595    MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
596                                  MachineBasicBlock *BB, unsigned Size) const;
597  };
598
599  /// Create MipsTargetLowering objects.
600  const MipsTargetLowering *createMips16TargetLowering(MipsTargetMachine &TM);
601  const MipsTargetLowering *createMipsSETargetLowering(MipsTargetMachine &TM);
602}
603
604#endif // MipsISELLOWERING_H
605