MipsISelLowering.h revision 7887c90a7b80b994a51a2a3b88eef3643473e67c 
1//===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that Mips uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef MipsISELLOWERING_H
16#define MipsISELLOWERING_H
17
18#include "Mips.h"
19#include "MipsSubtarget.h"
20#include "llvm/CodeGen/CallingConvLower.h"
21#include "llvm/CodeGen/SelectionDAG.h"
22#include "llvm/Target/TargetLowering.h"
23
24namespace llvm {
25  namespace MipsISD {
26    enum NodeType {
27      // Start the numbering from where ISD NodeType finishes.
28      FIRST_NUMBER = ISD::BUILTIN_OP_END,
29
30      // Jump and link (call)
31      JmpLink,
32
33      // Tail call
34      TailCall,
35
36      // Get the Higher 16 bits from a 32-bit immediate
37      // No relation with Mips Hi register
38      Hi,
39
40      // Get the Lower 16 bits from a 32-bit immediate
41      // No relation with Mips Lo register
42      Lo,
43
44      // Handle gp_rel (small data/bss sections) relocation.
45      GPRel,
46
47      // Thread Pointer
48      ThreadPointer,
49
50      // Floating Point Branch Conditional
51      FPBrcond,
52
53      // Floating Point Compare
54      FPCmp,
55
56      // Floating Point Conditional Moves
57      CMovFP_T,
58      CMovFP_F,
59
60      // Floating Point Rounding
61      FPRound,
62
63      // Return
64      Ret,
65
66      // MAdd/Sub nodes
67      MAdd,
68      MAddu,
69      MSub,
70      MSubu,
71
72      // DivRem(u)
73      DivRem,
74      DivRemU,
75
76      BuildPairF64,
77      ExtractElementF64,
78
79      Wrapper,
80
81      DynAlloc,
82
83      Sync,
84
85      Ext,
86      Ins,
87
88      // EXTR.W instrinsic nodes.
89      EXTP,
90      EXTPDP,
91      EXTR_S_H,
92      EXTR_W,
93      EXTR_R_W,
94      EXTR_RS_W,
95      SHILO,
96      MTHLIP,
97
98      // DPA.W intrinsic nodes.
99      MULSAQ_S_W_PH,
100      MAQ_S_W_PHL,
101      MAQ_S_W_PHR,
102      MAQ_SA_W_PHL,
103      MAQ_SA_W_PHR,
104      DPAU_H_QBL,
105      DPAU_H_QBR,
106      DPSU_H_QBL,
107      DPSU_H_QBR,
108      DPAQ_S_W_PH,
109      DPSQ_S_W_PH,
110      DPAQ_SA_L_W,
111      DPSQ_SA_L_W,
112      DPA_W_PH,
113      DPS_W_PH,
114      DPAQX_S_W_PH,
115      DPAQX_SA_W_PH,
116      DPAX_W_PH,
117      DPSX_W_PH,
118      DPSQX_S_W_PH,
119      DPSQX_SA_W_PH,
120      MULSA_W_PH,
121
122      MULT,
123      MULTU,
124      MADD_DSP,
125      MADDU_DSP,
126      MSUB_DSP,
127      MSUBU_DSP,
128
129      // Load/Store Left/Right nodes.
130      LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
131      LWR,
132      SWL,
133      SWR,
134      LDL,
135      LDR,
136      SDL,
137      SDR
138    };
139  }
140
141  //===--------------------------------------------------------------------===//
142  // TargetLowering Implementation
143  //===--------------------------------------------------------------------===//
144
145  class MipsTargetLowering : public TargetLowering  {
146  public:
147    explicit MipsTargetLowering(MipsTargetMachine &TM);
148
149    virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
150
151    virtual bool allowsUnalignedMemoryAccesses (EVT VT) const;
152
153    virtual void LowerOperationWrapper(SDNode *N,
154                                       SmallVectorImpl<SDValue> &Results,
155                                       SelectionDAG &DAG) const;
156
157    /// LowerOperation - Provide custom lowering hooks for some operations.
158    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
159
160    /// ReplaceNodeResults - Replace the results of node with an illegal result
161    /// type with new values built out of custom code.
162    ///
163    virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
164                                    SelectionDAG &DAG) const;
165
166    /// getTargetNodeName - This method returns the name of a target specific
167    //  DAG node.
168    virtual const char *getTargetNodeName(unsigned Opcode) const;
169
170    /// getSetCCResultType - get the ISD::SETCC result ValueType
171    EVT getSetCCResultType(EVT VT) const;
172
173    virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
174  private:
175
176    /// ByValArgInfo - Byval argument information.
177    struct ByValArgInfo {
178      unsigned FirstIdx; // Index of the first register used.
179      unsigned NumRegs;  // Number of registers used for this argument.
180      unsigned Address;  // Offset of the stack area used to pass this argument.
181
182      ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
183    };
184
185    /// MipsCC - This class provides methods used to analyze formal and call
186    /// arguments and inquire about calling convention information.
187    class MipsCC {
188    public:
189      MipsCC(CallingConv::ID CallConv, bool IsVarArg, bool IsO32,
190             CCState &Info);
191
192      void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs);
193      void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins);
194      void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
195                          CCValAssign::LocInfo LocInfo,
196                          ISD::ArgFlagsTy ArgFlags);
197
198      const CCState &getCCInfo() const { return CCInfo; }
199
200      /// hasByValArg - Returns true if function has byval arguments.
201      bool hasByValArg() const { return !ByValArgs.empty(); }
202
203      /// useRegsForByval - Returns true if the calling convention allows the
204      /// use of registers to pass byval arguments.
205      bool useRegsForByval() const { return UseRegsForByval; }
206
207      /// regSize - Size (in number of bits) of integer registers.
208      unsigned regSize() const { return RegSize; }
209
210      /// numIntArgRegs - Number of integer registers available for calls.
211      unsigned numIntArgRegs() const { return NumIntArgRegs; }
212
213      /// reservedArgArea - The size of the area the caller reserves for
214      /// register arguments. This is 16-byte if ABI is O32.
215      unsigned reservedArgArea() const { return ReservedArgArea; }
216
217      /// intArgRegs - Pointer to array of integer registers.
218      const uint16_t *intArgRegs() const { return IntArgRegs; }
219
220      typedef SmallVector<ByValArgInfo, 2>::const_iterator byval_iterator;
221      byval_iterator byval_begin() const { return ByValArgs.begin(); }
222      byval_iterator byval_end() const { return ByValArgs.end(); }
223
224    private:
225      void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
226                        unsigned Align);
227
228      CCState &CCInfo;
229      bool UseRegsForByval;
230      unsigned RegSize;
231      unsigned NumIntArgRegs;
232      unsigned ReservedArgArea;
233      const uint16_t *IntArgRegs, *ShadowRegs;
234      SmallVector<ByValArgInfo, 2> ByValArgs;
235      llvm::CCAssignFn *FixedFn, *VarFn;
236    };
237
238    // Subtarget Info
239    const MipsSubtarget *Subtarget;
240
241    bool HasMips64, IsN64, IsO32;
242
243    // Lower Operand helpers
244    SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
245                            CallingConv::ID CallConv, bool isVarArg,
246                            const SmallVectorImpl<ISD::InputArg> &Ins,
247                            DebugLoc dl, SelectionDAG &DAG,
248                            SmallVectorImpl<SDValue> &InVals) const;
249
250    // Lower Operand specifics
251    SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
252    SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
253    SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
254    SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
255    SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
256    SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
257    SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
258    SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
259    SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
260    SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
261    SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
262    SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
263    SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
264    SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
265    SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
266    SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
267    SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
268    SDValue LowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
269                                 bool IsSRA) const;
270    SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
271    SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
272    SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
273    SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
274
275    /// IsEligibleForTailCallOptimization - Check whether the call is eligible
276    /// for tail call optimization.
277    bool IsEligibleForTailCallOptimization(CallingConv::ID CalleeCC,
278                                           unsigned NextStackOffset) const;
279
280    virtual SDValue
281      LowerFormalArguments(SDValue Chain,
282                           CallingConv::ID CallConv, bool isVarArg,
283                           const SmallVectorImpl<ISD::InputArg> &Ins,
284                           DebugLoc dl, SelectionDAG &DAG,
285                           SmallVectorImpl<SDValue> &InVals) const;
286
287    virtual SDValue
288      LowerCall(TargetLowering::CallLoweringInfo &CLI,
289                SmallVectorImpl<SDValue> &InVals) const;
290
291    virtual bool
292      CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
293                     bool isVarArg,
294                     const SmallVectorImpl<ISD::OutputArg> &Outs,
295                     LLVMContext &Context) const;
296
297    virtual SDValue
298      LowerReturn(SDValue Chain,
299                  CallingConv::ID CallConv, bool isVarArg,
300                  const SmallVectorImpl<ISD::OutputArg> &Outs,
301                  const SmallVectorImpl<SDValue> &OutVals,
302                  DebugLoc dl, SelectionDAG &DAG) const;
303
304    virtual MachineBasicBlock *
305      EmitInstrWithCustomInserter(MachineInstr *MI,
306                                  MachineBasicBlock *MBB) const;
307
308    // Inline asm support
309    ConstraintType getConstraintType(const std::string &Constraint) const;
310
311    /// Examine constraint string and operand type and determine a weight value.
312    /// The operand object must already have been set up with the operand type.
313    ConstraintWeight getSingleConstraintMatchWeight(
314      AsmOperandInfo &info, const char *constraint) const;
315
316    std::pair<unsigned, const TargetRegisterClass*>
317              getRegForInlineAsmConstraint(const std::string &Constraint,
318              EVT VT) const;
319
320    /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
321    /// vector.  If it is invalid, don't add anything to Ops. If hasMemory is
322    /// true it means one of the asm constraint of the inline asm instruction
323    /// being processed is 'm'.
324    virtual void LowerAsmOperandForConstraint(SDValue Op,
325                                              std::string &Constraint,
326                                              std::vector<SDValue> &Ops,
327                                              SelectionDAG &DAG) const;
328
329    virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
330
331    virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
332                                    unsigned SrcAlign, bool IsZeroVal,
333                                    bool MemcpyStrSrc,
334                                    MachineFunction &MF) const;
335
336    /// isFPImmLegal - Returns true if the target can instruction select the
337    /// specified FP immediate natively. If false, the legalizer will
338    /// materialize the FP immediate as a load from a constant pool.
339    virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
340
341    virtual unsigned getJumpTableEncoding() const;
342
343    MachineBasicBlock *EmitBPOSGE32(MachineInstr *MI,
344                                    MachineBasicBlock *BB) const;
345    MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
346                    unsigned Size, unsigned BinOpcode, bool Nand = false) const;
347    MachineBasicBlock *EmitAtomicBinaryPartword(MachineInstr *MI,
348                    MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
349                    bool Nand = false) const;
350    MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
351                                  MachineBasicBlock *BB, unsigned Size) const;
352    MachineBasicBlock *EmitAtomicCmpSwapPartword(MachineInstr *MI,
353                                  MachineBasicBlock *BB, unsigned Size) const;
354  };
355}
356
357#endif // MipsISELLOWERING_H
358