MipsISelLowering.h revision 793803449870a661c1a09e400df9b04492772196
1//===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that Mips uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef MipsISELLOWERING_H 16#define MipsISELLOWERING_H 17 18#include "Mips.h" 19#include "MipsSubtarget.h" 20#include "llvm/CodeGen/CallingConvLower.h" 21#include "llvm/CodeGen/SelectionDAG.h" 22#include "llvm/IR/Function.h" 23#include "llvm/Target/TargetLowering.h" 24#include <deque> 25#include <string> 26 27namespace llvm { 28 namespace MipsISD { 29 enum NodeType { 30 // Start the numbering from where ISD NodeType finishes. 31 FIRST_NUMBER = ISD::BUILTIN_OP_END, 32 33 // Jump and link (call) 34 JmpLink, 35 36 // Tail call 37 TailCall, 38 39 // Get the Higher 16 bits from a 32-bit immediate 40 // No relation with Mips Hi register 41 Hi, 42 43 // Get the Lower 16 bits from a 32-bit immediate 44 // No relation with Mips Lo register 45 Lo, 46 47 // Handle gp_rel (small data/bss sections) relocation. 48 GPRel, 49 50 // Thread Pointer 51 ThreadPointer, 52 53 // Floating Point Branch Conditional 54 FPBrcond, 55 56 // Floating Point Compare 57 FPCmp, 58 59 // Floating Point Conditional Moves 60 CMovFP_T, 61 CMovFP_F, 62 63 // FP-to-int truncation node. 64 TruncIntFP, 65 66 // Return 67 Ret, 68 69 EH_RETURN, 70 71 // Node used to extract integer from accumulator. 72 ExtractLOHI, 73 74 // Node used to insert integers to accumulator. 75 InsertLOHI, 76 77 // Mult nodes. 78 Mult, 79 Multu, 80 81 // MAdd/Sub nodes 82 MAdd, 83 MAddu, 84 MSub, 85 MSubu, 86 87 // DivRem(u) 88 DivRem, 89 DivRemU, 90 DivRem16, 91 DivRemU16, 92 93 BuildPairF64, 94 ExtractElementF64, 95 96 Wrapper, 97 98 DynAlloc, 99 100 Sync, 101 102 Ext, 103 Ins, 104 105 // EXTR.W instrinsic nodes. 106 EXTP, 107 EXTPDP, 108 EXTR_S_H, 109 EXTR_W, 110 EXTR_R_W, 111 EXTR_RS_W, 112 SHILO, 113 MTHLIP, 114 115 // DPA.W intrinsic nodes. 116 MULSAQ_S_W_PH, 117 MAQ_S_W_PHL, 118 MAQ_S_W_PHR, 119 MAQ_SA_W_PHL, 120 MAQ_SA_W_PHR, 121 DPAU_H_QBL, 122 DPAU_H_QBR, 123 DPSU_H_QBL, 124 DPSU_H_QBR, 125 DPAQ_S_W_PH, 126 DPSQ_S_W_PH, 127 DPAQ_SA_L_W, 128 DPSQ_SA_L_W, 129 DPA_W_PH, 130 DPS_W_PH, 131 DPAQX_S_W_PH, 132 DPAQX_SA_W_PH, 133 DPAX_W_PH, 134 DPSX_W_PH, 135 DPSQX_S_W_PH, 136 DPSQX_SA_W_PH, 137 MULSA_W_PH, 138 139 MULT, 140 MULTU, 141 MADD_DSP, 142 MADDU_DSP, 143 MSUB_DSP, 144 MSUBU_DSP, 145 146 // DSP shift nodes. 147 SHLL_DSP, 148 SHRA_DSP, 149 SHRL_DSP, 150 151 // DSP setcc and select_cc nodes. 152 SETCC_DSP, 153 SELECT_CC_DSP, 154 155 // Vector comparisons. 156 // These take a vector and return a boolean. 157 VALL_ZERO, 158 VANY_ZERO, 159 VALL_NONZERO, 160 VANY_NONZERO, 161 162 // These take a vector and return a vector bitmask. 163 VCEQ, 164 VCLE_S, 165 VCLE_U, 166 VCLT_S, 167 VCLT_U, 168 169 // Element-wise vector max/min. 170 VSMAX, 171 VSMIN, 172 VUMAX, 173 VUMIN, 174 175 // Vector Shuffle with mask as an operand 176 VSHF, // Generic shuffle 177 SHF, // 4-element set shuffle. 178 ILVEV, // Interleave even elements 179 ILVOD, // Interleave odd elements 180 ILVL, // Interleave left elements 181 ILVR, // Interleave right elements 182 PCKEV, // Pack even elements 183 PCKOD, // Pack odd elements 184 185 // Combined (XOR (OR $a, $b), -1) 186 VNOR, 187 188 // Extended vector element extraction 189 VEXTRACT_SEXT_ELT, 190 VEXTRACT_ZEXT_ELT, 191 192 // Load/Store Left/Right nodes. 193 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE, 194 LWR, 195 SWL, 196 SWR, 197 LDL, 198 LDR, 199 SDL, 200 SDR 201 }; 202 } 203 204 //===--------------------------------------------------------------------===// 205 // TargetLowering Implementation 206 //===--------------------------------------------------------------------===// 207 class MipsFunctionInfo; 208 209 class MipsTargetLowering : public TargetLowering { 210 public: 211 explicit MipsTargetLowering(MipsTargetMachine &TM); 212 213 static const MipsTargetLowering *create(MipsTargetMachine &TM); 214 215 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; } 216 217 virtual void LowerOperationWrapper(SDNode *N, 218 SmallVectorImpl<SDValue> &Results, 219 SelectionDAG &DAG) const; 220 221 /// LowerOperation - Provide custom lowering hooks for some operations. 222 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 223 224 /// ReplaceNodeResults - Replace the results of node with an illegal result 225 /// type with new values built out of custom code. 226 /// 227 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 228 SelectionDAG &DAG) const; 229 230 /// getTargetNodeName - This method returns the name of a target specific 231 // DAG node. 232 virtual const char *getTargetNodeName(unsigned Opcode) const; 233 234 /// getSetCCResultType - get the ISD::SETCC result ValueType 235 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const; 236 237 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 238 239 virtual MachineBasicBlock * 240 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const; 241 242 struct LTStr { 243 bool operator()(const char *S1, const char *S2) const { 244 return strcmp(S1, S2) < 0; 245 } 246 }; 247 248 protected: 249 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const; 250 251 template<class NodeTy> 252 SDValue getAddrLocal(NodeTy *N, EVT Ty, SelectionDAG &DAG, 253 bool HasMips64) const; 254 255 template<class NodeTy> 256 SDValue getAddrGlobal(NodeTy *N, EVT Ty, SelectionDAG &DAG, 257 unsigned Flag) const; 258 259 template<class NodeTy> 260 SDValue getAddrGlobalLargeGOT(NodeTy *N, EVT Ty, SelectionDAG &DAG, 261 unsigned HiFlag, unsigned LoFlag) const; 262 263 /// This function fills Ops, which is the list of operands that will later 264 /// be used when a function call node is created. It also generates 265 /// copyToReg nodes to set up argument registers. 266 virtual void 267 getOpndList(SmallVectorImpl<SDValue> &Ops, 268 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 269 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 270 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const; 271 272 /// ByValArgInfo - Byval argument information. 273 struct ByValArgInfo { 274 unsigned FirstIdx; // Index of the first register used. 275 unsigned NumRegs; // Number of registers used for this argument. 276 unsigned Address; // Offset of the stack area used to pass this argument. 277 278 ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {} 279 }; 280 281 /// MipsCC - This class provides methods used to analyze formal and call 282 /// arguments and inquire about calling convention information. 283 class MipsCC { 284 public: 285 enum SpecialCallingConvType { 286 Mips16RetHelperConv, NoSpecialCallingConv 287 }; 288 289 MipsCC(CallingConv::ID CallConv, bool IsO32, bool IsFP64, CCState &Info, 290 SpecialCallingConvType SpecialCallingConv = NoSpecialCallingConv); 291 292 293 void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, 294 bool IsVarArg, bool IsSoftFloat, 295 const SDNode *CallNode, 296 std::vector<ArgListEntry> &FuncArgs); 297 void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, 298 bool IsSoftFloat, 299 Function::const_arg_iterator FuncArg); 300 301 void analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, 302 bool IsSoftFloat, const SDNode *CallNode, 303 const Type *RetTy) const; 304 305 void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, 306 bool IsSoftFloat, const Type *RetTy) const; 307 308 const CCState &getCCInfo() const { return CCInfo; } 309 310 /// hasByValArg - Returns true if function has byval arguments. 311 bool hasByValArg() const { return !ByValArgs.empty(); } 312 313 /// regSize - Size (in number of bits) of integer registers. 314 unsigned regSize() const { return IsO32 ? 4 : 8; } 315 316 /// numIntArgRegs - Number of integer registers available for calls. 317 unsigned numIntArgRegs() const; 318 319 /// reservedArgArea - The size of the area the caller reserves for 320 /// register arguments. This is 16-byte if ABI is O32. 321 unsigned reservedArgArea() const; 322 323 /// Return pointer to array of integer argument registers. 324 const uint16_t *intArgRegs() const; 325 326 typedef SmallVectorImpl<ByValArgInfo>::const_iterator byval_iterator; 327 byval_iterator byval_begin() const { return ByValArgs.begin(); } 328 byval_iterator byval_end() const { return ByValArgs.end(); } 329 330 private: 331 void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT, 332 CCValAssign::LocInfo LocInfo, 333 ISD::ArgFlagsTy ArgFlags); 334 335 /// useRegsForByval - Returns true if the calling convention allows the 336 /// use of registers to pass byval arguments. 337 bool useRegsForByval() const { return CallConv != CallingConv::Fast; } 338 339 /// Return the function that analyzes fixed argument list functions. 340 llvm::CCAssignFn *fixedArgFn() const; 341 342 /// Return the function that analyzes variable argument list functions. 343 llvm::CCAssignFn *varArgFn() const; 344 345 const uint16_t *shadowRegs() const; 346 347 void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize, 348 unsigned Align); 349 350 /// Return the type of the register which is used to pass an argument or 351 /// return a value. This function returns f64 if the argument is an i64 352 /// value which has been generated as a result of softening an f128 value. 353 /// Otherwise, it just returns VT. 354 MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode, 355 bool IsSoftFloat) const; 356 357 template<typename Ty> 358 void analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat, 359 const SDNode *CallNode, const Type *RetTy) const; 360 361 CCState &CCInfo; 362 CallingConv::ID CallConv; 363 bool IsO32, IsFP64; 364 SpecialCallingConvType SpecialCallingConv; 365 SmallVector<ByValArgInfo, 2> ByValArgs; 366 }; 367 protected: 368 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const; 369 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const; 370 371 // Subtarget Info 372 const MipsSubtarget *Subtarget; 373 374 bool HasMips64, IsN64, IsO32; 375 376 private: 377 378 MipsCC::SpecialCallingConvType getSpecialCallingConv(SDValue Callee) const; 379 // Lower Operand helpers 380 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 381 CallingConv::ID CallConv, bool isVarArg, 382 const SmallVectorImpl<ISD::InputArg> &Ins, 383 SDLoc dl, SelectionDAG &DAG, 384 SmallVectorImpl<SDValue> &InVals, 385 const SDNode *CallNode, const Type *RetTy) const; 386 387 // Lower Operand specifics 388 SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 389 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 390 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 391 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 392 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 393 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 394 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 395 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const; 396 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 397 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const; 398 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const; 399 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 400 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const; 401 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 402 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 403 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const; 404 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const; 405 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const; 406 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG, 407 bool IsSRA) const; 408 SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const; 409 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const; 410 411 /// isEligibleForTailCallOptimization - Check whether the call is eligible 412 /// for tail call optimization. 413 virtual bool 414 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo, 415 unsigned NextStackOffset, 416 const MipsFunctionInfo& FI) const = 0; 417 418 /// copyByValArg - Copy argument registers which were used to pass a byval 419 /// argument to the stack. Create a stack frame object for the byval 420 /// argument. 421 void copyByValRegs(SDValue Chain, SDLoc DL, 422 std::vector<SDValue> &OutChains, SelectionDAG &DAG, 423 const ISD::ArgFlagsTy &Flags, 424 SmallVectorImpl<SDValue> &InVals, 425 const Argument *FuncArg, 426 const MipsCC &CC, const ByValArgInfo &ByVal) const; 427 428 /// passByValArg - Pass a byval argument in registers or on stack. 429 void passByValArg(SDValue Chain, SDLoc DL, 430 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 431 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, 432 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, 433 const MipsCC &CC, const ByValArgInfo &ByVal, 434 const ISD::ArgFlagsTy &Flags, bool isLittle) const; 435 436 /// writeVarArgRegs - Write variable function arguments passed in registers 437 /// to the stack. Also create a stack frame object for the first variable 438 /// argument. 439 void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC, 440 SDValue Chain, SDLoc DL, SelectionDAG &DAG) const; 441 442 virtual SDValue 443 LowerFormalArguments(SDValue Chain, 444 CallingConv::ID CallConv, bool isVarArg, 445 const SmallVectorImpl<ISD::InputArg> &Ins, 446 SDLoc dl, SelectionDAG &DAG, 447 SmallVectorImpl<SDValue> &InVals) const; 448 449 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain, 450 SDValue Arg, SDLoc DL, bool IsTailCall, 451 SelectionDAG &DAG) const; 452 453 virtual SDValue 454 LowerCall(TargetLowering::CallLoweringInfo &CLI, 455 SmallVectorImpl<SDValue> &InVals) const; 456 457 virtual bool 458 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 459 bool isVarArg, 460 const SmallVectorImpl<ISD::OutputArg> &Outs, 461 LLVMContext &Context) const; 462 463 virtual SDValue 464 LowerReturn(SDValue Chain, 465 CallingConv::ID CallConv, bool isVarArg, 466 const SmallVectorImpl<ISD::OutputArg> &Outs, 467 const SmallVectorImpl<SDValue> &OutVals, 468 SDLoc dl, SelectionDAG &DAG) const; 469 470 // Inline asm support 471 ConstraintType getConstraintType(const std::string &Constraint) const; 472 473 /// Examine constraint string and operand type and determine a weight value. 474 /// The operand object must already have been set up with the operand type. 475 ConstraintWeight getSingleConstraintMatchWeight( 476 AsmOperandInfo &info, const char *constraint) const; 477 478 /// This function parses registers that appear in inline-asm constraints. 479 /// It returns pair (0, 0) on failure. 480 std::pair<unsigned, const TargetRegisterClass *> 481 parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const; 482 483 std::pair<unsigned, const TargetRegisterClass*> 484 getRegForInlineAsmConstraint(const std::string &Constraint, 485 MVT VT) const; 486 487 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 488 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 489 /// true it means one of the asm constraint of the inline asm instruction 490 /// being processed is 'm'. 491 virtual void LowerAsmOperandForConstraint(SDValue Op, 492 std::string &Constraint, 493 std::vector<SDValue> &Ops, 494 SelectionDAG &DAG) const; 495 496 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const; 497 498 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 499 500 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 501 unsigned SrcAlign, 502 bool IsMemset, bool ZeroMemset, 503 bool MemcpyStrSrc, 504 MachineFunction &MF) const; 505 506 /// isFPImmLegal - Returns true if the target can instruction select the 507 /// specified FP immediate natively. If false, the legalizer will 508 /// materialize the FP immediate as a load from a constant pool. 509 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; 510 511 virtual unsigned getJumpTableEncoding() const; 512 513 MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 514 unsigned Size, unsigned BinOpcode, bool Nand = false) const; 515 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI, 516 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode, 517 bool Nand = false) const; 518 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI, 519 MachineBasicBlock *BB, unsigned Size) const; 520 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI, 521 MachineBasicBlock *BB, unsigned Size) const; 522 }; 523 524 /// Create MipsTargetLowering objects. 525 const MipsTargetLowering *createMips16TargetLowering(MipsTargetMachine &TM); 526 const MipsTargetLowering *createMipsSETargetLowering(MipsTargetMachine &TM); 527} 528 529#endif // MipsISELLOWERING_H 530