MipsISelLowering.h revision 8453b3f66a3c3200ea828491ef5cf162db9ccfb2 
1//===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that Mips uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef MipsISELLOWERING_H
16#define MipsISELLOWERING_H
17
18#include "Mips.h"
19#include "MipsSubtarget.h"
20#include "llvm/CodeGen/CallingConvLower.h"
21#include "llvm/CodeGen/SelectionDAG.h"
22#include "llvm/Target/TargetLowering.h"
23#include <deque>
24#include <string>
25
26namespace llvm {
27  namespace MipsISD {
28    enum NodeType {
29      // Start the numbering from where ISD NodeType finishes.
30      FIRST_NUMBER = ISD::BUILTIN_OP_END,
31
32      // Jump and link (call)
33      JmpLink,
34
35      // Tail call
36      TailCall,
37
38      // Get the Higher 16 bits from a 32-bit immediate
39      // No relation with Mips Hi register
40      Hi,
41
42      // Get the Lower 16 bits from a 32-bit immediate
43      // No relation with Mips Lo register
44      Lo,
45
46      // Handle gp_rel (small data/bss sections) relocation.
47      GPRel,
48
49      // Thread Pointer
50      ThreadPointer,
51
52      // Floating Point Branch Conditional
53      FPBrcond,
54
55      // Floating Point Compare
56      FPCmp,
57
58      // Floating Point Conditional Moves
59      CMovFP_T,
60      CMovFP_F,
61
62      // Floating Point Rounding
63      FPRound,
64
65      // Return
66      Ret,
67
68      // MAdd/Sub nodes
69      MAdd,
70      MAddu,
71      MSub,
72      MSubu,
73
74      // DivRem(u)
75      DivRem,
76      DivRemU,
77
78      BuildPairF64,
79      ExtractElementF64,
80
81      Wrapper,
82
83      DynAlloc,
84
85      Sync,
86
87      Ext,
88      Ins,
89
90      // EXTR.W instrinsic nodes.
91      EXTP,
92      EXTPDP,
93      EXTR_S_H,
94      EXTR_W,
95      EXTR_R_W,
96      EXTR_RS_W,
97      SHILO,
98      MTHLIP,
99
100      // DPA.W intrinsic nodes.
101      MULSAQ_S_W_PH,
102      MAQ_S_W_PHL,
103      MAQ_S_W_PHR,
104      MAQ_SA_W_PHL,
105      MAQ_SA_W_PHR,
106      DPAU_H_QBL,
107      DPAU_H_QBR,
108      DPSU_H_QBL,
109      DPSU_H_QBR,
110      DPAQ_S_W_PH,
111      DPSQ_S_W_PH,
112      DPAQ_SA_L_W,
113      DPSQ_SA_L_W,
114      DPA_W_PH,
115      DPS_W_PH,
116      DPAQX_S_W_PH,
117      DPAQX_SA_W_PH,
118      DPAX_W_PH,
119      DPSX_W_PH,
120      DPSQX_S_W_PH,
121      DPSQX_SA_W_PH,
122      MULSA_W_PH,
123
124      MULT,
125      MULTU,
126      MADD_DSP,
127      MADDU_DSP,
128      MSUB_DSP,
129      MSUBU_DSP,
130
131      // Load/Store Left/Right nodes.
132      LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
133      LWR,
134      SWL,
135      SWR,
136      LDL,
137      LDR,
138      SDL,
139      SDR
140    };
141  }
142
143  //===--------------------------------------------------------------------===//
144  // TargetLowering Implementation
145  //===--------------------------------------------------------------------===//
146  class MipsFunctionInfo;
147
148  class MipsTargetLowering : public TargetLowering  {
149  public:
150    explicit MipsTargetLowering(MipsTargetMachine &TM);
151
152    virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
153
154    virtual bool allowsUnalignedMemoryAccesses (EVT VT, bool *Fast) const;
155
156    virtual void LowerOperationWrapper(SDNode *N,
157                                       SmallVectorImpl<SDValue> &Results,
158                                       SelectionDAG &DAG) const;
159
160    /// LowerOperation - Provide custom lowering hooks for some operations.
161    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
162
163    /// ReplaceNodeResults - Replace the results of node with an illegal result
164    /// type with new values built out of custom code.
165    ///
166    virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
167                                    SelectionDAG &DAG) const;
168
169    /// getTargetNodeName - This method returns the name of a target specific
170    //  DAG node.
171    virtual const char *getTargetNodeName(unsigned Opcode) const;
172
173    /// getSetCCResultType - get the ISD::SETCC result ValueType
174    EVT getSetCCResultType(EVT VT) const;
175
176    virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
177  private:
178
179    void setMips16HardFloatLibCalls();
180
181    unsigned int
182      getMips16HelperFunctionStubNumber(ArgListTy &Args) const;
183
184    const char *getMips16HelperFunction
185      (Type* RetTy, ArgListTy &Args, bool &needHelper) const;
186
187    /// ByValArgInfo - Byval argument information.
188    struct ByValArgInfo {
189      unsigned FirstIdx; // Index of the first register used.
190      unsigned NumRegs;  // Number of registers used for this argument.
191      unsigned Address;  // Offset of the stack area used to pass this argument.
192
193      ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
194    };
195
196    /// MipsCC - This class provides methods used to analyze formal and call
197    /// arguments and inquire about calling convention information.
198    class MipsCC {
199    public:
200      MipsCC(CallingConv::ID CallConv, bool IsVarArg, bool IsO32,
201             CCState &Info);
202
203      void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs);
204      void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins);
205      void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
206                          CCValAssign::LocInfo LocInfo,
207                          ISD::ArgFlagsTy ArgFlags);
208
209      const CCState &getCCInfo() const { return CCInfo; }
210
211      /// hasByValArg - Returns true if function has byval arguments.
212      bool hasByValArg() const { return !ByValArgs.empty(); }
213
214      /// useRegsForByval - Returns true if the calling convention allows the
215      /// use of registers to pass byval arguments.
216      bool useRegsForByval() const { return UseRegsForByval; }
217
218      /// regSize - Size (in number of bits) of integer registers.
219      unsigned regSize() const { return RegSize; }
220
221      /// numIntArgRegs - Number of integer registers available for calls.
222      unsigned numIntArgRegs() const { return NumIntArgRegs; }
223
224      /// reservedArgArea - The size of the area the caller reserves for
225      /// register arguments. This is 16-byte if ABI is O32.
226      unsigned reservedArgArea() const { return ReservedArgArea; }
227
228      /// intArgRegs - Pointer to array of integer registers.
229      const uint16_t *intArgRegs() const { return IntArgRegs; }
230
231      typedef SmallVector<ByValArgInfo, 2>::const_iterator byval_iterator;
232      byval_iterator byval_begin() const { return ByValArgs.begin(); }
233      byval_iterator byval_end() const { return ByValArgs.end(); }
234
235    private:
236      void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
237                        unsigned Align);
238
239      CCState &CCInfo;
240      bool UseRegsForByval;
241      unsigned RegSize;
242      unsigned NumIntArgRegs;
243      unsigned ReservedArgArea;
244      const uint16_t *IntArgRegs, *ShadowRegs;
245      SmallVector<ByValArgInfo, 2> ByValArgs;
246      llvm::CCAssignFn *FixedFn, *VarFn;
247    };
248
249    // Subtarget Info
250    const MipsSubtarget *Subtarget;
251
252    bool HasMips64, IsN64, IsO32;
253
254    // Lower Operand helpers
255    SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
256                            CallingConv::ID CallConv, bool isVarArg,
257                            const SmallVectorImpl<ISD::InputArg> &Ins,
258                            DebugLoc dl, SelectionDAG &DAG,
259                            SmallVectorImpl<SDValue> &InVals) const;
260
261    // Lower Operand specifics
262    SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
263    SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
264    SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
265    SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
266    SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
267    SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
268    SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
269    SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
270    SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
271    SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
272    SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
273    SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
274    SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
275    SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
276    SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
277    SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
278    SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
279    SDValue LowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
280                                 bool IsSRA) const;
281    SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
282    SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
283    SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
284    SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
285    SDValue LowerADD(SDValue Op, SelectionDAG &DAG) const;
286
287    /// IsEligibleForTailCallOptimization - Check whether the call is eligible
288    /// for tail call optimization.
289    bool IsEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
290                                           unsigned NextStackOffset,
291                                           const MipsFunctionInfo& FI) const;
292
293    /// copyByValArg - Copy argument registers which were used to pass a byval
294    /// argument to the stack. Create a stack frame object for the byval
295    /// argument.
296    void copyByValRegs(SDValue Chain, DebugLoc DL,
297                       std::vector<SDValue> &OutChains, SelectionDAG &DAG,
298                       const ISD::ArgFlagsTy &Flags,
299                       SmallVectorImpl<SDValue> &InVals,
300                       const Argument *FuncArg,
301                       const MipsCC &CC, const ByValArgInfo &ByVal) const;
302
303    /// passByValArg - Pass a byval argument in registers or on stack.
304    void passByValArg(SDValue Chain, DebugLoc DL,
305                      std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
306                      SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr,
307                      MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
308                      const MipsCC &CC, const ByValArgInfo &ByVal,
309                      const ISD::ArgFlagsTy &Flags, bool isLittle) const;
310
311    /// writeVarArgRegs - Write variable function arguments passed in registers
312    /// to the stack. Also create a stack frame object for the first variable
313    /// argument.
314    void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
315                         SDValue Chain, DebugLoc DL, SelectionDAG &DAG) const;
316
317    virtual SDValue
318      LowerFormalArguments(SDValue Chain,
319                           CallingConv::ID CallConv, bool isVarArg,
320                           const SmallVectorImpl<ISD::InputArg> &Ins,
321                           DebugLoc dl, SelectionDAG &DAG,
322                           SmallVectorImpl<SDValue> &InVals) const;
323
324    SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
325                           SDValue Arg, DebugLoc DL, bool IsTailCall,
326                           SelectionDAG &DAG) const;
327
328    virtual SDValue
329      LowerCall(TargetLowering::CallLoweringInfo &CLI,
330                SmallVectorImpl<SDValue> &InVals) const;
331
332    virtual bool
333      CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
334                     bool isVarArg,
335                     const SmallVectorImpl<ISD::OutputArg> &Outs,
336                     LLVMContext &Context) const;
337
338    virtual SDValue
339      LowerReturn(SDValue Chain,
340                  CallingConv::ID CallConv, bool isVarArg,
341                  const SmallVectorImpl<ISD::OutputArg> &Outs,
342                  const SmallVectorImpl<SDValue> &OutVals,
343                  DebugLoc dl, SelectionDAG &DAG) const;
344
345    virtual MachineBasicBlock *
346      EmitInstrWithCustomInserter(MachineInstr *MI,
347                                  MachineBasicBlock *MBB) const;
348
349    // Inline asm support
350    ConstraintType getConstraintType(const std::string &Constraint) const;
351
352    /// Examine constraint string and operand type and determine a weight value.
353    /// The operand object must already have been set up with the operand type.
354    ConstraintWeight getSingleConstraintMatchWeight(
355      AsmOperandInfo &info, const char *constraint) const;
356
357    std::pair<unsigned, const TargetRegisterClass*>
358              getRegForInlineAsmConstraint(const std::string &Constraint,
359              EVT VT) const;
360
361    /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
362    /// vector.  If it is invalid, don't add anything to Ops. If hasMemory is
363    /// true it means one of the asm constraint of the inline asm instruction
364    /// being processed is 'm'.
365    virtual void LowerAsmOperandForConstraint(SDValue Op,
366                                              std::string &Constraint,
367                                              std::vector<SDValue> &Ops,
368                                              SelectionDAG &DAG) const;
369
370    virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
371
372    virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
373
374    virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
375                                    unsigned SrcAlign,
376                                    bool IsMemset, bool ZeroMemset,
377                                    bool MemcpyStrSrc,
378                                    MachineFunction &MF) const;
379
380    /// isFPImmLegal - Returns true if the target can instruction select the
381    /// specified FP immediate natively. If false, the legalizer will
382    /// materialize the FP immediate as a load from a constant pool.
383    virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
384
385    virtual unsigned getJumpTableEncoding() const;
386
387    MachineBasicBlock *EmitBPOSGE32(MachineInstr *MI,
388                                    MachineBasicBlock *BB) const;
389    MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
390                    unsigned Size, unsigned BinOpcode, bool Nand = false) const;
391    MachineBasicBlock *EmitAtomicBinaryPartword(MachineInstr *MI,
392                    MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
393                    bool Nand = false) const;
394    MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
395                                  MachineBasicBlock *BB, unsigned Size) const;
396    MachineBasicBlock *EmitAtomicCmpSwapPartword(MachineInstr *MI,
397                                  MachineBasicBlock *BB, unsigned Size) const;
398  };
399}
400
401#endif // MipsISELLOWERING_H
402