MipsISelLowering.h revision 864f66085cd9543070ef01b9f7371c110ecd7898 
1//===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that Mips uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef MipsISELLOWERING_H
16#define MipsISELLOWERING_H
17
18#include "Mips.h"
19#include "MipsSubtarget.h"
20#include "llvm/CodeGen/SelectionDAG.h"
21#include "llvm/Target/TargetLowering.h"
22
23namespace llvm {
24  namespace MipsISD {
25    enum NodeType {
26      // Start the numbering from where ISD NodeType finishes.
27      FIRST_NUMBER = ISD::BUILTIN_OP_END,
28
29      // Jump and link (call)
30      JmpLink,
31
32      // Get the Higher 16 bits from a 32-bit immediate
33      // No relation with Mips Hi register
34      Hi,
35
36      // Get the Lower 16 bits from a 32-bit immediate
37      // No relation with Mips Lo register
38      Lo,
39
40      // Handle gp_rel (small data/bss sections) relocation.
41      GPRel,
42
43      // Thread Pointer
44      ThreadPointer,
45
46      // Floating Point Branch Conditional
47      FPBrcond,
48
49      // Floating Point Compare
50      FPCmp,
51
52      // Floating Point Conditional Moves
53      CMovFP_T,
54      CMovFP_F,
55
56      // Floating Point Rounding
57      FPRound,
58
59      // Return
60      Ret,
61
62      // MAdd/Sub nodes
63      MAdd,
64      MAddu,
65      MSub,
66      MSubu,
67
68      // DivRem(u)
69      DivRem,
70      DivRemU,
71
72      BuildPairF64,
73      ExtractElementF64,
74
75      Wrapper,
76
77      DynAlloc,
78
79      Sync,
80
81      Ext,
82      Ins,
83
84      // Load/Store Left/Right nodes.
85      LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
86      LWR,
87      SWL,
88      SWR,
89      LDL,
90      LDR,
91      SDL,
92      SDR
93    };
94  }
95
96  //===--------------------------------------------------------------------===//
97  // TargetLowering Implementation
98  //===--------------------------------------------------------------------===//
99
100  class MipsTargetLowering : public TargetLowering  {
101  public:
102    explicit MipsTargetLowering(MipsTargetMachine &TM);
103
104    virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
105
106    virtual bool allowsUnalignedMemoryAccesses (EVT VT) const;
107
108    /// LowerOperation - Provide custom lowering hooks for some operations.
109    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
110
111    /// getTargetNodeName - This method returns the name of a target specific
112    //  DAG node.
113    virtual const char *getTargetNodeName(unsigned Opcode) const;
114
115    /// getSetCCResultType - get the ISD::SETCC result ValueType
116    EVT getSetCCResultType(EVT VT) const;
117
118    virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
119  private:
120    // Subtarget Info
121    const MipsSubtarget *Subtarget;
122
123    bool HasMips64, IsN64, IsO32;
124
125    // Lower Operand helpers
126    SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
127                            CallingConv::ID CallConv, bool isVarArg,
128                            const SmallVectorImpl<ISD::InputArg> &Ins,
129                            DebugLoc dl, SelectionDAG &DAG,
130                            SmallVectorImpl<SDValue> &InVals) const;
131
132    // Lower Operand specifics
133    SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
134    SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
135    SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
136    SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
137    SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
138    SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
139    SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
140    SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
141    SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
142    SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
143    SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
144    SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
145    SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
146    SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
147    SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
148    SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
149    SDValue LowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
150                                 bool IsSRA) const;
151    SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
152    SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
153
154    virtual SDValue
155      LowerFormalArguments(SDValue Chain,
156                           CallingConv::ID CallConv, bool isVarArg,
157                           const SmallVectorImpl<ISD::InputArg> &Ins,
158                           DebugLoc dl, SelectionDAG &DAG,
159                           SmallVectorImpl<SDValue> &InVals) const;
160
161    virtual SDValue
162      LowerCall(TargetLowering::CallLoweringInfo &CLI,
163                SmallVectorImpl<SDValue> &InVals) const;
164
165    virtual SDValue
166      LowerReturn(SDValue Chain,
167                  CallingConv::ID CallConv, bool isVarArg,
168                  const SmallVectorImpl<ISD::OutputArg> &Outs,
169                  const SmallVectorImpl<SDValue> &OutVals,
170                  DebugLoc dl, SelectionDAG &DAG) const;
171
172    virtual MachineBasicBlock *
173      EmitInstrWithCustomInserter(MachineInstr *MI,
174                                  MachineBasicBlock *MBB) const;
175
176    // Inline asm support
177    ConstraintType getConstraintType(const std::string &Constraint) const;
178
179    /// Examine constraint string and operand type and determine a weight value.
180    /// The operand object must already have been set up with the operand type.
181    ConstraintWeight getSingleConstraintMatchWeight(
182      AsmOperandInfo &info, const char *constraint) const;
183
184    std::pair<unsigned, const TargetRegisterClass*>
185              getRegForInlineAsmConstraint(const std::string &Constraint,
186              EVT VT) const;
187
188    /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
189    /// vector.  If it is invalid, don't add anything to Ops. If hasMemory is
190    /// true it means one of the asm constraint of the inline asm instruction
191    /// being processed is 'm'.
192    virtual void LowerAsmOperandForConstraint(SDValue Op,
193                                              std::string &Constraint,
194                                              std::vector<SDValue> &Ops,
195                                              SelectionDAG &DAG) const;
196
197    virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
198
199    virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
200                                    unsigned SrcAlign, bool IsZeroVal,
201                                    bool MemcpyStrSrc,
202                                    MachineFunction &MF) const;
203
204    /// isFPImmLegal - Returns true if the target can instruction select the
205    /// specified FP immediate natively. If false, the legalizer will
206    /// materialize the FP immediate as a load from a constant pool.
207    virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
208
209    virtual unsigned getJumpTableEncoding() const;
210
211    MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
212                    unsigned Size, unsigned BinOpcode, bool Nand = false) const;
213    MachineBasicBlock *EmitAtomicBinaryPartword(MachineInstr *MI,
214                    MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
215                    bool Nand = false) const;
216    MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
217                                  MachineBasicBlock *BB, unsigned Size) const;
218    MachineBasicBlock *EmitAtomicCmpSwapPartword(MachineInstr *MI,
219                                  MachineBasicBlock *BB, unsigned Size) const;
220  };
221}
222
223#endif // MipsISELLOWERING_H
224