MipsISelLowering.h revision 915432ca1306d10453c9eb523cbc4b257642f62a 
1//===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that Mips uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef MipsISELLOWERING_H
16#define MipsISELLOWERING_H
17
18#include "Mips.h"
19#include "MipsSubtarget.h"
20#include "llvm/CodeGen/CallingConvLower.h"
21#include "llvm/CodeGen/SelectionDAG.h"
22#include "llvm/IR/Function.h"
23#include "llvm/Target/TargetLowering.h"
24#include <deque>
25#include <string>
26
27namespace llvm {
28  namespace MipsISD {
29    enum NodeType {
30      // Start the numbering from where ISD NodeType finishes.
31      FIRST_NUMBER = ISD::BUILTIN_OP_END,
32
33      // Jump and link (call)
34      JmpLink,
35
36      // Tail call
37      TailCall,
38
39      // Get the Higher 16 bits from a 32-bit immediate
40      // No relation with Mips Hi register
41      Hi,
42
43      // Get the Lower 16 bits from a 32-bit immediate
44      // No relation with Mips Lo register
45      Lo,
46
47      // Handle gp_rel (small data/bss sections) relocation.
48      GPRel,
49
50      // Thread Pointer
51      ThreadPointer,
52
53      // Floating Point Branch Conditional
54      FPBrcond,
55
56      // Floating Point Compare
57      FPCmp,
58
59      // Floating Point Conditional Moves
60      CMovFP_T,
61      CMovFP_F,
62
63      // FP-to-int truncation node.
64      TruncIntFP,
65
66      // Return
67      Ret,
68
69      EH_RETURN,
70
71      // Node used to extract integer from accumulator.
72      ExtractLOHI,
73
74      // Node used to insert integers to accumulator.
75      InsertLOHI,
76
77      // Mult nodes.
78      Mult,
79      Multu,
80
81      // MAdd/Sub nodes
82      MAdd,
83      MAddu,
84      MSub,
85      MSubu,
86
87      // DivRem(u)
88      DivRem,
89      DivRemU,
90      DivRem16,
91      DivRemU16,
92
93      BuildPairF64,
94      ExtractElementF64,
95
96      Wrapper,
97
98      DynAlloc,
99
100      Sync,
101
102      Ext,
103      Ins,
104
105      // EXTR.W instrinsic nodes.
106      EXTP,
107      EXTPDP,
108      EXTR_S_H,
109      EXTR_W,
110      EXTR_R_W,
111      EXTR_RS_W,
112      SHILO,
113      MTHLIP,
114
115      // DPA.W intrinsic nodes.
116      MULSAQ_S_W_PH,
117      MAQ_S_W_PHL,
118      MAQ_S_W_PHR,
119      MAQ_SA_W_PHL,
120      MAQ_SA_W_PHR,
121      DPAU_H_QBL,
122      DPAU_H_QBR,
123      DPSU_H_QBL,
124      DPSU_H_QBR,
125      DPAQ_S_W_PH,
126      DPSQ_S_W_PH,
127      DPAQ_SA_L_W,
128      DPSQ_SA_L_W,
129      DPA_W_PH,
130      DPS_W_PH,
131      DPAQX_S_W_PH,
132      DPAQX_SA_W_PH,
133      DPAX_W_PH,
134      DPSX_W_PH,
135      DPSQX_S_W_PH,
136      DPSQX_SA_W_PH,
137      MULSA_W_PH,
138
139      MULT,
140      MULTU,
141      MADD_DSP,
142      MADDU_DSP,
143      MSUB_DSP,
144      MSUBU_DSP,
145
146      // DSP shift nodes.
147      SHLL_DSP,
148      SHRA_DSP,
149      SHRL_DSP,
150
151      // DSP setcc and select_cc nodes.
152      SETCC_DSP,
153      SELECT_CC_DSP,
154
155      // Vector comparisons.
156      VALL_ZERO,
157      VANY_ZERO,
158      VALL_NONZERO,
159      VANY_NONZERO,
160
161      // Special case of BUILD_VECTOR where all elements are the same.
162      VSPLAT,
163      // Special case of VSPLAT where the result is v2i64, the operand is
164      // constant, and the operand fits in a signed 10-bits value.
165      VSPLATD,
166
167      // Combined (XOR (OR $a, $b), -1)
168      VNOR,
169
170      // Load/Store Left/Right nodes.
171      LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
172      LWR,
173      SWL,
174      SWR,
175      LDL,
176      LDR,
177      SDL,
178      SDR
179    };
180  }
181
182  //===--------------------------------------------------------------------===//
183  // TargetLowering Implementation
184  //===--------------------------------------------------------------------===//
185  class MipsFunctionInfo;
186
187  class MipsTargetLowering : public TargetLowering  {
188  public:
189    explicit MipsTargetLowering(MipsTargetMachine &TM);
190
191    static const MipsTargetLowering *create(MipsTargetMachine &TM);
192
193    virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
194
195    virtual void LowerOperationWrapper(SDNode *N,
196                                       SmallVectorImpl<SDValue> &Results,
197                                       SelectionDAG &DAG) const;
198
199    /// LowerOperation - Provide custom lowering hooks for some operations.
200    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
201
202    /// ReplaceNodeResults - Replace the results of node with an illegal result
203    /// type with new values built out of custom code.
204    ///
205    virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
206                                    SelectionDAG &DAG) const;
207
208    /// getTargetNodeName - This method returns the name of a target specific
209    //  DAG node.
210    virtual const char *getTargetNodeName(unsigned Opcode) const;
211
212    /// getSetCCResultType - get the ISD::SETCC result ValueType
213    EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
214
215    virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
216
217    virtual MachineBasicBlock *
218    EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
219
220    struct LTStr {
221      bool operator()(const char *S1, const char *S2) const {
222        return strcmp(S1, S2) < 0;
223      }
224    };
225
226  protected:
227    SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
228
229    SDValue getAddrLocal(SDValue Op, SelectionDAG &DAG, bool HasMips64) const;
230
231    SDValue getAddrGlobal(SDValue Op, SelectionDAG &DAG, unsigned Flag) const;
232
233    SDValue getAddrGlobalLargeGOT(SDValue Op, SelectionDAG &DAG,
234                                  unsigned HiFlag, unsigned LoFlag) const;
235
236    /// This function fills Ops, which is the list of operands that will later
237    /// be used when a function call node is created. It also generates
238    /// copyToReg nodes to set up argument registers.
239    virtual void
240    getOpndList(SmallVectorImpl<SDValue> &Ops,
241                std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
242                bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
243                CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
244
245    /// ByValArgInfo - Byval argument information.
246    struct ByValArgInfo {
247      unsigned FirstIdx; // Index of the first register used.
248      unsigned NumRegs;  // Number of registers used for this argument.
249      unsigned Address;  // Offset of the stack area used to pass this argument.
250
251      ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
252    };
253
254    /// MipsCC - This class provides methods used to analyze formal and call
255    /// arguments and inquire about calling convention information.
256    class MipsCC {
257    public:
258      enum SpecialCallingConvType {
259        Mips16RetHelperConv, NoSpecialCallingConv
260      };
261
262      MipsCC(CallingConv::ID CallConv, bool IsO32, bool IsFP64, CCState &Info,
263             SpecialCallingConvType SpecialCallingConv = NoSpecialCallingConv);
264
265
266      void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
267                               bool IsVarArg, bool IsSoftFloat,
268                               const SDNode *CallNode,
269                               std::vector<ArgListEntry> &FuncArgs);
270      void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
271                                  bool IsSoftFloat,
272                                  Function::const_arg_iterator FuncArg);
273
274      void analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
275                             bool IsSoftFloat, const SDNode *CallNode,
276                             const Type *RetTy) const;
277
278      void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
279                         bool IsSoftFloat, const Type *RetTy) const;
280
281      const CCState &getCCInfo() const { return CCInfo; }
282
283      /// hasByValArg - Returns true if function has byval arguments.
284      bool hasByValArg() const { return !ByValArgs.empty(); }
285
286      /// regSize - Size (in number of bits) of integer registers.
287      unsigned regSize() const { return IsO32 ? 4 : 8; }
288
289      /// numIntArgRegs - Number of integer registers available for calls.
290      unsigned numIntArgRegs() const;
291
292      /// reservedArgArea - The size of the area the caller reserves for
293      /// register arguments. This is 16-byte if ABI is O32.
294      unsigned reservedArgArea() const;
295
296      /// Return pointer to array of integer argument registers.
297      const uint16_t *intArgRegs() const;
298
299      typedef SmallVectorImpl<ByValArgInfo>::const_iterator byval_iterator;
300      byval_iterator byval_begin() const { return ByValArgs.begin(); }
301      byval_iterator byval_end() const { return ByValArgs.end(); }
302
303    private:
304      void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
305                          CCValAssign::LocInfo LocInfo,
306                          ISD::ArgFlagsTy ArgFlags);
307
308      /// useRegsForByval - Returns true if the calling convention allows the
309      /// use of registers to pass byval arguments.
310      bool useRegsForByval() const { return CallConv != CallingConv::Fast; }
311
312      /// Return the function that analyzes fixed argument list functions.
313      llvm::CCAssignFn *fixedArgFn() const;
314
315      /// Return the function that analyzes variable argument list functions.
316      llvm::CCAssignFn *varArgFn() const;
317
318      const uint16_t *shadowRegs() const;
319
320      void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
321                        unsigned Align);
322
323      /// Return the type of the register which is used to pass an argument or
324      /// return a value. This function returns f64 if the argument is an i64
325      /// value which has been generated as a result of softening an f128 value.
326      /// Otherwise, it just returns VT.
327      MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode,
328                   bool IsSoftFloat) const;
329
330      template<typename Ty>
331      void analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat,
332                         const SDNode *CallNode, const Type *RetTy) const;
333
334      CCState &CCInfo;
335      CallingConv::ID CallConv;
336      bool IsO32, IsFP64;
337      SpecialCallingConvType SpecialCallingConv;
338      SmallVector<ByValArgInfo, 2> ByValArgs;
339    };
340  protected:
341    SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
342    SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
343
344    // Subtarget Info
345    const MipsSubtarget *Subtarget;
346
347    bool HasMips64, IsN64, IsO32;
348
349  private:
350
351    MipsCC::SpecialCallingConvType getSpecialCallingConv(SDValue Callee) const;
352    // Lower Operand helpers
353    SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
354                            CallingConv::ID CallConv, bool isVarArg,
355                            const SmallVectorImpl<ISD::InputArg> &Ins,
356                            SDLoc dl, SelectionDAG &DAG,
357                            SmallVectorImpl<SDValue> &InVals,
358                            const SDNode *CallNode, const Type *RetTy) const;
359
360    // Lower Operand specifics
361    SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
362    SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
363    SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
364    SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
365    SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
366    SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
367    SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
368    SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
369    SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
370    SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
371    SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
372    SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
373    SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
374    SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
375    SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
376    SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
377    SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
378    SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
379    SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
380                                 bool IsSRA) const;
381    SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
382    SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
383
384    /// isEligibleForTailCallOptimization - Check whether the call is eligible
385    /// for tail call optimization.
386    virtual bool
387    isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
388                                      unsigned NextStackOffset,
389                                      const MipsFunctionInfo& FI) const = 0;
390
391    /// copyByValArg - Copy argument registers which were used to pass a byval
392    /// argument to the stack. Create a stack frame object for the byval
393    /// argument.
394    void copyByValRegs(SDValue Chain, SDLoc DL,
395                       std::vector<SDValue> &OutChains, SelectionDAG &DAG,
396                       const ISD::ArgFlagsTy &Flags,
397                       SmallVectorImpl<SDValue> &InVals,
398                       const Argument *FuncArg,
399                       const MipsCC &CC, const ByValArgInfo &ByVal) const;
400
401    /// passByValArg - Pass a byval argument in registers or on stack.
402    void passByValArg(SDValue Chain, SDLoc DL,
403                      std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
404                      SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
405                      MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
406                      const MipsCC &CC, const ByValArgInfo &ByVal,
407                      const ISD::ArgFlagsTy &Flags, bool isLittle) const;
408
409    /// writeVarArgRegs - Write variable function arguments passed in registers
410    /// to the stack. Also create a stack frame object for the first variable
411    /// argument.
412    void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
413                         SDValue Chain, SDLoc DL, SelectionDAG &DAG) const;
414
415    virtual SDValue
416      LowerFormalArguments(SDValue Chain,
417                           CallingConv::ID CallConv, bool isVarArg,
418                           const SmallVectorImpl<ISD::InputArg> &Ins,
419                           SDLoc dl, SelectionDAG &DAG,
420                           SmallVectorImpl<SDValue> &InVals) const;
421
422    SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
423                           SDValue Arg, SDLoc DL, bool IsTailCall,
424                           SelectionDAG &DAG) const;
425
426    virtual SDValue
427      LowerCall(TargetLowering::CallLoweringInfo &CLI,
428                SmallVectorImpl<SDValue> &InVals) const;
429
430    virtual bool
431      CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
432                     bool isVarArg,
433                     const SmallVectorImpl<ISD::OutputArg> &Outs,
434                     LLVMContext &Context) const;
435
436    virtual SDValue
437      LowerReturn(SDValue Chain,
438                  CallingConv::ID CallConv, bool isVarArg,
439                  const SmallVectorImpl<ISD::OutputArg> &Outs,
440                  const SmallVectorImpl<SDValue> &OutVals,
441                  SDLoc dl, SelectionDAG &DAG) const;
442
443    // Inline asm support
444    ConstraintType getConstraintType(const std::string &Constraint) const;
445
446    /// Examine constraint string and operand type and determine a weight value.
447    /// The operand object must already have been set up with the operand type.
448    ConstraintWeight getSingleConstraintMatchWeight(
449      AsmOperandInfo &info, const char *constraint) const;
450
451    /// This function parses registers that appear in inline-asm constraints.
452    /// It returns pair (0, 0) on failure.
453    std::pair<unsigned, const TargetRegisterClass *>
454    parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const;
455
456    std::pair<unsigned, const TargetRegisterClass*>
457              getRegForInlineAsmConstraint(const std::string &Constraint,
458                                           MVT VT) const;
459
460    /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
461    /// vector.  If it is invalid, don't add anything to Ops. If hasMemory is
462    /// true it means one of the asm constraint of the inline asm instruction
463    /// being processed is 'm'.
464    virtual void LowerAsmOperandForConstraint(SDValue Op,
465                                              std::string &Constraint,
466                                              std::vector<SDValue> &Ops,
467                                              SelectionDAG &DAG) const;
468
469    virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
470
471    virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
472
473    virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
474                                    unsigned SrcAlign,
475                                    bool IsMemset, bool ZeroMemset,
476                                    bool MemcpyStrSrc,
477                                    MachineFunction &MF) const;
478
479    /// isFPImmLegal - Returns true if the target can instruction select the
480    /// specified FP immediate natively. If false, the legalizer will
481    /// materialize the FP immediate as a load from a constant pool.
482    virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
483
484    virtual unsigned getJumpTableEncoding() const;
485
486    MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
487                    unsigned Size, unsigned BinOpcode, bool Nand = false) const;
488    MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
489                    MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
490                    bool Nand = false) const;
491    MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
492                                  MachineBasicBlock *BB, unsigned Size) const;
493    MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
494                                  MachineBasicBlock *BB, unsigned Size) const;
495  };
496
497  /// Create MipsTargetLowering objects.
498  const MipsTargetLowering *createMips16TargetLowering(MipsTargetMachine &TM);
499  const MipsTargetLowering *createMipsSETargetLowering(MipsTargetMachine &TM);
500}
501
502#endif // MipsISELLOWERING_H
503