MipsISelLowering.h revision 93d995719e2459a6e9ccdb2c93a8ede8fa88c899 
1//===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that Mips uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef MipsISELLOWERING_H
16#define MipsISELLOWERING_H
17
18#include "Mips.h"
19#include "MipsSubtarget.h"
20#include "llvm/CodeGen/CallingConvLower.h"
21#include "llvm/CodeGen/SelectionDAG.h"
22#include "llvm/IR/Function.h"
23#include "llvm/Target/TargetLowering.h"
24#include <deque>
25#include <string>
26
27namespace llvm {
28  namespace MipsISD {
29    enum NodeType {
30      // Start the numbering from where ISD NodeType finishes.
31      FIRST_NUMBER = ISD::BUILTIN_OP_END,
32
33      // Jump and link (call)
34      JmpLink,
35
36      // Tail call
37      TailCall,
38
39      // Get the Higher 16 bits from a 32-bit immediate
40      // No relation with Mips Hi register
41      Hi,
42
43      // Get the Lower 16 bits from a 32-bit immediate
44      // No relation with Mips Lo register
45      Lo,
46
47      // Handle gp_rel (small data/bss sections) relocation.
48      GPRel,
49
50      // Thread Pointer
51      ThreadPointer,
52
53      // Floating Point Branch Conditional
54      FPBrcond,
55
56      // Floating Point Compare
57      FPCmp,
58
59      // Floating Point Conditional Moves
60      CMovFP_T,
61      CMovFP_F,
62
63      // FP-to-int truncation node.
64      TruncIntFP,
65
66      // Return
67      Ret,
68
69      EH_RETURN,
70
71      // Node used to extract integer from accumulator.
72      ExtractLOHI,
73
74      // Node used to insert integers to accumulator.
75      InsertLOHI,
76
77      // Mult nodes.
78      Mult,
79      Multu,
80
81      // MAdd/Sub nodes
82      MAdd,
83      MAddu,
84      MSub,
85      MSubu,
86
87      // DivRem(u)
88      DivRem,
89      DivRemU,
90      DivRem16,
91      DivRemU16,
92
93      BuildPairF64,
94      ExtractElementF64,
95
96      Wrapper,
97
98      DynAlloc,
99
100      Sync,
101
102      Ext,
103      Ins,
104
105      // EXTR.W instrinsic nodes.
106      EXTP,
107      EXTPDP,
108      EXTR_S_H,
109      EXTR_W,
110      EXTR_R_W,
111      EXTR_RS_W,
112      SHILO,
113      MTHLIP,
114
115      // DPA.W intrinsic nodes.
116      MULSAQ_S_W_PH,
117      MAQ_S_W_PHL,
118      MAQ_S_W_PHR,
119      MAQ_SA_W_PHL,
120      MAQ_SA_W_PHR,
121      DPAU_H_QBL,
122      DPAU_H_QBR,
123      DPSU_H_QBL,
124      DPSU_H_QBR,
125      DPAQ_S_W_PH,
126      DPSQ_S_W_PH,
127      DPAQ_SA_L_W,
128      DPSQ_SA_L_W,
129      DPA_W_PH,
130      DPS_W_PH,
131      DPAQX_S_W_PH,
132      DPAQX_SA_W_PH,
133      DPAX_W_PH,
134      DPSX_W_PH,
135      DPSQX_S_W_PH,
136      DPSQX_SA_W_PH,
137      MULSA_W_PH,
138
139      MULT,
140      MULTU,
141      MADD_DSP,
142      MADDU_DSP,
143      MSUB_DSP,
144      MSUBU_DSP,
145
146      // DSP shift nodes.
147      SHLL_DSP,
148      SHRA_DSP,
149      SHRL_DSP,
150
151      // DSP setcc and select_cc nodes.
152      SETCC_DSP,
153      SELECT_CC_DSP,
154
155      // Vector comparisons.
156      // These take a vector and return a boolean.
157      VALL_ZERO,
158      VANY_ZERO,
159      VALL_NONZERO,
160      VANY_NONZERO,
161
162      // These take a vector and return a vector bitmask.
163      VCEQ,
164      VCLE_S,
165      VCLE_U,
166      VCLT_S,
167      VCLT_U,
168
169      // Element-wise vector max/min.
170      VSMAX,
171      VSMIN,
172      VUMAX,
173      VUMIN,
174
175      // Vector Shuffle with mask as an operand
176      VSHF,  // Generic shuffle
177      SHF,   // 4-element set shuffle.
178
179      // Combined (XOR (OR $a, $b), -1)
180      VNOR,
181
182      // Extended vector element extraction
183      VEXTRACT_SEXT_ELT,
184      VEXTRACT_ZEXT_ELT,
185
186      // Load/Store Left/Right nodes.
187      LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
188      LWR,
189      SWL,
190      SWR,
191      LDL,
192      LDR,
193      SDL,
194      SDR
195    };
196  }
197
198  //===--------------------------------------------------------------------===//
199  // TargetLowering Implementation
200  //===--------------------------------------------------------------------===//
201  class MipsFunctionInfo;
202
203  class MipsTargetLowering : public TargetLowering  {
204  public:
205    explicit MipsTargetLowering(MipsTargetMachine &TM);
206
207    static const MipsTargetLowering *create(MipsTargetMachine &TM);
208
209    virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
210
211    virtual void LowerOperationWrapper(SDNode *N,
212                                       SmallVectorImpl<SDValue> &Results,
213                                       SelectionDAG &DAG) const;
214
215    /// LowerOperation - Provide custom lowering hooks for some operations.
216    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
217
218    /// ReplaceNodeResults - Replace the results of node with an illegal result
219    /// type with new values built out of custom code.
220    ///
221    virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
222                                    SelectionDAG &DAG) const;
223
224    /// getTargetNodeName - This method returns the name of a target specific
225    //  DAG node.
226    virtual const char *getTargetNodeName(unsigned Opcode) const;
227
228    /// getSetCCResultType - get the ISD::SETCC result ValueType
229    EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
230
231    virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
232
233    virtual MachineBasicBlock *
234    EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
235
236    struct LTStr {
237      bool operator()(const char *S1, const char *S2) const {
238        return strcmp(S1, S2) < 0;
239      }
240    };
241
242  protected:
243    SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
244
245    SDValue getAddrLocal(SDValue Op, SelectionDAG &DAG, bool HasMips64) const;
246
247    SDValue getAddrGlobal(SDValue Op, SelectionDAG &DAG, unsigned Flag) const;
248
249    SDValue getAddrGlobalLargeGOT(SDValue Op, SelectionDAG &DAG,
250                                  unsigned HiFlag, unsigned LoFlag) const;
251
252    /// This function fills Ops, which is the list of operands that will later
253    /// be used when a function call node is created. It also generates
254    /// copyToReg nodes to set up argument registers.
255    virtual void
256    getOpndList(SmallVectorImpl<SDValue> &Ops,
257                std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
258                bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
259                CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
260
261    /// ByValArgInfo - Byval argument information.
262    struct ByValArgInfo {
263      unsigned FirstIdx; // Index of the first register used.
264      unsigned NumRegs;  // Number of registers used for this argument.
265      unsigned Address;  // Offset of the stack area used to pass this argument.
266
267      ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
268    };
269
270    /// MipsCC - This class provides methods used to analyze formal and call
271    /// arguments and inquire about calling convention information.
272    class MipsCC {
273    public:
274      enum SpecialCallingConvType {
275        Mips16RetHelperConv, NoSpecialCallingConv
276      };
277
278      MipsCC(CallingConv::ID CallConv, bool IsO32, bool IsFP64, CCState &Info,
279             SpecialCallingConvType SpecialCallingConv = NoSpecialCallingConv);
280
281
282      void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
283                               bool IsVarArg, bool IsSoftFloat,
284                               const SDNode *CallNode,
285                               std::vector<ArgListEntry> &FuncArgs);
286      void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
287                                  bool IsSoftFloat,
288                                  Function::const_arg_iterator FuncArg);
289
290      void analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
291                             bool IsSoftFloat, const SDNode *CallNode,
292                             const Type *RetTy) const;
293
294      void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
295                         bool IsSoftFloat, const Type *RetTy) const;
296
297      const CCState &getCCInfo() const { return CCInfo; }
298
299      /// hasByValArg - Returns true if function has byval arguments.
300      bool hasByValArg() const { return !ByValArgs.empty(); }
301
302      /// regSize - Size (in number of bits) of integer registers.
303      unsigned regSize() const { return IsO32 ? 4 : 8; }
304
305      /// numIntArgRegs - Number of integer registers available for calls.
306      unsigned numIntArgRegs() const;
307
308      /// reservedArgArea - The size of the area the caller reserves for
309      /// register arguments. This is 16-byte if ABI is O32.
310      unsigned reservedArgArea() const;
311
312      /// Return pointer to array of integer argument registers.
313      const uint16_t *intArgRegs() const;
314
315      typedef SmallVectorImpl<ByValArgInfo>::const_iterator byval_iterator;
316      byval_iterator byval_begin() const { return ByValArgs.begin(); }
317      byval_iterator byval_end() const { return ByValArgs.end(); }
318
319    private:
320      void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
321                          CCValAssign::LocInfo LocInfo,
322                          ISD::ArgFlagsTy ArgFlags);
323
324      /// useRegsForByval - Returns true if the calling convention allows the
325      /// use of registers to pass byval arguments.
326      bool useRegsForByval() const { return CallConv != CallingConv::Fast; }
327
328      /// Return the function that analyzes fixed argument list functions.
329      llvm::CCAssignFn *fixedArgFn() const;
330
331      /// Return the function that analyzes variable argument list functions.
332      llvm::CCAssignFn *varArgFn() const;
333
334      const uint16_t *shadowRegs() const;
335
336      void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
337                        unsigned Align);
338
339      /// Return the type of the register which is used to pass an argument or
340      /// return a value. This function returns f64 if the argument is an i64
341      /// value which has been generated as a result of softening an f128 value.
342      /// Otherwise, it just returns VT.
343      MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode,
344                   bool IsSoftFloat) const;
345
346      template<typename Ty>
347      void analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat,
348                         const SDNode *CallNode, const Type *RetTy) const;
349
350      CCState &CCInfo;
351      CallingConv::ID CallConv;
352      bool IsO32, IsFP64;
353      SpecialCallingConvType SpecialCallingConv;
354      SmallVector<ByValArgInfo, 2> ByValArgs;
355    };
356  protected:
357    SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
358    SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
359
360    // Subtarget Info
361    const MipsSubtarget *Subtarget;
362
363    bool HasMips64, IsN64, IsO32;
364
365  private:
366
367    MipsCC::SpecialCallingConvType getSpecialCallingConv(SDValue Callee) const;
368    // Lower Operand helpers
369    SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
370                            CallingConv::ID CallConv, bool isVarArg,
371                            const SmallVectorImpl<ISD::InputArg> &Ins,
372                            SDLoc dl, SelectionDAG &DAG,
373                            SmallVectorImpl<SDValue> &InVals,
374                            const SDNode *CallNode, const Type *RetTy) const;
375
376    // Lower Operand specifics
377    SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
378    SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
379    SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
380    SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
381    SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
382    SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
383    SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
384    SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
385    SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
386    SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
387    SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
388    SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
389    SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
390    SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
391    SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
392    SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
393    SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
394    SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
395    SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
396                                 bool IsSRA) const;
397    SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
398    SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
399
400    /// isEligibleForTailCallOptimization - Check whether the call is eligible
401    /// for tail call optimization.
402    virtual bool
403    isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
404                                      unsigned NextStackOffset,
405                                      const MipsFunctionInfo& FI) const = 0;
406
407    /// copyByValArg - Copy argument registers which were used to pass a byval
408    /// argument to the stack. Create a stack frame object for the byval
409    /// argument.
410    void copyByValRegs(SDValue Chain, SDLoc DL,
411                       std::vector<SDValue> &OutChains, SelectionDAG &DAG,
412                       const ISD::ArgFlagsTy &Flags,
413                       SmallVectorImpl<SDValue> &InVals,
414                       const Argument *FuncArg,
415                       const MipsCC &CC, const ByValArgInfo &ByVal) const;
416
417    /// passByValArg - Pass a byval argument in registers or on stack.
418    void passByValArg(SDValue Chain, SDLoc DL,
419                      std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
420                      SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
421                      MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
422                      const MipsCC &CC, const ByValArgInfo &ByVal,
423                      const ISD::ArgFlagsTy &Flags, bool isLittle) const;
424
425    /// writeVarArgRegs - Write variable function arguments passed in registers
426    /// to the stack. Also create a stack frame object for the first variable
427    /// argument.
428    void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
429                         SDValue Chain, SDLoc DL, SelectionDAG &DAG) const;
430
431    virtual SDValue
432      LowerFormalArguments(SDValue Chain,
433                           CallingConv::ID CallConv, bool isVarArg,
434                           const SmallVectorImpl<ISD::InputArg> &Ins,
435                           SDLoc dl, SelectionDAG &DAG,
436                           SmallVectorImpl<SDValue> &InVals) const;
437
438    SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
439                           SDValue Arg, SDLoc DL, bool IsTailCall,
440                           SelectionDAG &DAG) const;
441
442    virtual SDValue
443      LowerCall(TargetLowering::CallLoweringInfo &CLI,
444                SmallVectorImpl<SDValue> &InVals) const;
445
446    virtual bool
447      CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
448                     bool isVarArg,
449                     const SmallVectorImpl<ISD::OutputArg> &Outs,
450                     LLVMContext &Context) const;
451
452    virtual SDValue
453      LowerReturn(SDValue Chain,
454                  CallingConv::ID CallConv, bool isVarArg,
455                  const SmallVectorImpl<ISD::OutputArg> &Outs,
456                  const SmallVectorImpl<SDValue> &OutVals,
457                  SDLoc dl, SelectionDAG &DAG) const;
458
459    // Inline asm support
460    ConstraintType getConstraintType(const std::string &Constraint) const;
461
462    /// Examine constraint string and operand type and determine a weight value.
463    /// The operand object must already have been set up with the operand type.
464    ConstraintWeight getSingleConstraintMatchWeight(
465      AsmOperandInfo &info, const char *constraint) const;
466
467    /// This function parses registers that appear in inline-asm constraints.
468    /// It returns pair (0, 0) on failure.
469    std::pair<unsigned, const TargetRegisterClass *>
470    parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const;
471
472    std::pair<unsigned, const TargetRegisterClass*>
473              getRegForInlineAsmConstraint(const std::string &Constraint,
474                                           MVT VT) const;
475
476    /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
477    /// vector.  If it is invalid, don't add anything to Ops. If hasMemory is
478    /// true it means one of the asm constraint of the inline asm instruction
479    /// being processed is 'm'.
480    virtual void LowerAsmOperandForConstraint(SDValue Op,
481                                              std::string &Constraint,
482                                              std::vector<SDValue> &Ops,
483                                              SelectionDAG &DAG) const;
484
485    virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
486
487    virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
488
489    virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
490                                    unsigned SrcAlign,
491                                    bool IsMemset, bool ZeroMemset,
492                                    bool MemcpyStrSrc,
493                                    MachineFunction &MF) const;
494
495    /// isFPImmLegal - Returns true if the target can instruction select the
496    /// specified FP immediate natively. If false, the legalizer will
497    /// materialize the FP immediate as a load from a constant pool.
498    virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
499
500    virtual unsigned getJumpTableEncoding() const;
501
502    MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
503                    unsigned Size, unsigned BinOpcode, bool Nand = false) const;
504    MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
505                    MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
506                    bool Nand = false) const;
507    MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
508                                  MachineBasicBlock *BB, unsigned Size) const;
509    MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
510                                  MachineBasicBlock *BB, unsigned Size) const;
511  };
512
513  /// Create MipsTargetLowering objects.
514  const MipsTargetLowering *createMips16TargetLowering(MipsTargetMachine &TM);
515  const MipsTargetLowering *createMipsSETargetLowering(MipsTargetMachine &TM);
516}
517
518#endif // MipsISELLOWERING_H
519