MipsISelLowering.h revision 94e472832f30320d273f5630044c6bbd626e9949 
1bc8d3f97eb5c958007f2713238472e0c1c8fe02Howard Hinnant//===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
2bc8d3f97eb5c958007f2713238472e0c1c8fe02Howard Hinnant//
3f5256e16dfc425c1d466f6308d4026d529ce9e0bHoward Hinnant//                     The LLVM Compiler Infrastructure
4bc8d3f97eb5c958007f2713238472e0c1c8fe02Howard Hinnant//
5b64f8b07c104c6cc986570ac8ee0ed16a9f23976Howard Hinnant// This file is distributed under the University of Illinois Open Source
6b64f8b07c104c6cc986570ac8ee0ed16a9f23976Howard Hinnant// License. See LICENSE.TXT for details.
7bc8d3f97eb5c958007f2713238472e0c1c8fe02Howard Hinnant//
8bc8d3f97eb5c958007f2713238472e0c1c8fe02Howard Hinnant//===----------------------------------------------------------------------===//
9bc8d3f97eb5c958007f2713238472e0c1c8fe02Howard Hinnant//
10bc8d3f97eb5c958007f2713238472e0c1c8fe02Howard Hinnant// This file defines the interfaces that Mips uses to lower LLVM code into a
11bc8d3f97eb5c958007f2713238472e0c1c8fe02Howard Hinnant// selection DAG.
12bc8d3f97eb5c958007f2713238472e0c1c8fe02Howard Hinnant//
13//===----------------------------------------------------------------------===//
14
15#ifndef MipsISELLOWERING_H
16#define MipsISELLOWERING_H
17
18#include "Mips.h"
19#include "MipsSubtarget.h"
20#include "llvm/CodeGen/CallingConvLower.h"
21#include "llvm/CodeGen/SelectionDAG.h"
22#include "llvm/Target/TargetLowering.h"
23
24namespace llvm {
25  namespace MipsISD {
26    enum NodeType {
27      // Start the numbering from where ISD NodeType finishes.
28      FIRST_NUMBER = ISD::BUILTIN_OP_END,
29
30      // Jump and link (call)
31      JmpLink,
32
33      // Tail call
34      TailCall,
35
36      // Get the Higher 16 bits from a 32-bit immediate
37      // No relation with Mips Hi register
38      Hi,
39
40      // Get the Lower 16 bits from a 32-bit immediate
41      // No relation with Mips Lo register
42      Lo,
43
44      // Handle gp_rel (small data/bss sections) relocation.
45      GPRel,
46
47      // Thread Pointer
48      ThreadPointer,
49
50      // Floating Point Branch Conditional
51      FPBrcond,
52
53      // Floating Point Compare
54      FPCmp,
55
56      // Floating Point Conditional Moves
57      CMovFP_T,
58      CMovFP_F,
59
60      // Floating Point Rounding
61      FPRound,
62
63      // Return
64      Ret,
65
66      // MAdd/Sub nodes
67      MAdd,
68      MAddu,
69      MSub,
70      MSubu,
71
72      // DivRem(u)
73      DivRem,
74      DivRemU,
75
76      BuildPairF64,
77      ExtractElementF64,
78
79      Wrapper,
80
81      DynAlloc,
82
83      Sync,
84
85      Ext,
86      Ins,
87
88      // EXTR.W instrinsic nodes.
89      EXTP,
90      EXTPDP,
91      EXTR_S_H,
92      EXTR_W,
93      EXTR_R_W,
94      EXTR_RS_W,
95      SHILO,
96      MTHLIP,
97
98      // DPA.W intrinsic nodes.
99      MULSAQ_S_W_PH,
100      MAQ_S_W_PHL,
101      MAQ_S_W_PHR,
102      MAQ_SA_W_PHL,
103      MAQ_SA_W_PHR,
104      DPAU_H_QBL,
105      DPAU_H_QBR,
106      DPSU_H_QBL,
107      DPSU_H_QBR,
108      DPAQ_S_W_PH,
109      DPSQ_S_W_PH,
110      DPAQ_SA_L_W,
111      DPSQ_SA_L_W,
112      DPA_W_PH,
113      DPS_W_PH,
114      DPAQX_S_W_PH,
115      DPAQX_SA_W_PH,
116      DPAX_W_PH,
117      DPSX_W_PH,
118      DPSQX_S_W_PH,
119      DPSQX_SA_W_PH,
120      MULSA_W_PH,
121
122      MULT,
123      MULTU,
124      MADD_DSP,
125      MADDU_DSP,
126      MSUB_DSP,
127      MSUBU_DSP,
128
129      // Load/Store Left/Right nodes.
130      LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
131      LWR,
132      SWL,
133      SWR,
134      LDL,
135      LDR,
136      SDL,
137      SDR
138    };
139  }
140
141  //===--------------------------------------------------------------------===//
142  // TargetLowering Implementation
143  //===--------------------------------------------------------------------===//
144  class MipsFunctionInfo;
145
146  class MipsTargetLowering : public TargetLowering  {
147  public:
148    explicit MipsTargetLowering(MipsTargetMachine &TM);
149
150    virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
151
152    virtual bool allowsUnalignedMemoryAccesses (EVT VT) const;
153
154    virtual void LowerOperationWrapper(SDNode *N,
155                                       SmallVectorImpl<SDValue> &Results,
156                                       SelectionDAG &DAG) const;
157
158    /// LowerOperation - Provide custom lowering hooks for some operations.
159    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
160
161    /// ReplaceNodeResults - Replace the results of node with an illegal result
162    /// type with new values built out of custom code.
163    ///
164    virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
165                                    SelectionDAG &DAG) const;
166
167    /// getTargetNodeName - This method returns the name of a target specific
168    //  DAG node.
169    virtual const char *getTargetNodeName(unsigned Opcode) const;
170
171    /// getSetCCResultType - get the ISD::SETCC result ValueType
172    EVT getSetCCResultType(EVT VT) const;
173
174    virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
175  private:
176
177    /// ByValArgInfo - Byval argument information.
178    struct ByValArgInfo {
179      unsigned FirstIdx; // Index of the first register used.
180      unsigned NumRegs;  // Number of registers used for this argument.
181      unsigned Address;  // Offset of the stack area used to pass this argument.
182
183      ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
184    };
185
186    /// MipsCC - This class provides methods used to analyze formal and call
187    /// arguments and inquire about calling convention information.
188    class MipsCC {
189    public:
190      MipsCC(CallingConv::ID CallConv, bool IsVarArg, bool IsO32,
191             CCState &Info);
192
193      void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs);
194      void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins);
195      void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
196                          CCValAssign::LocInfo LocInfo,
197                          ISD::ArgFlagsTy ArgFlags);
198
199      const CCState &getCCInfo() const { return CCInfo; }
200
201      /// hasByValArg - Returns true if function has byval arguments.
202      bool hasByValArg() const { return !ByValArgs.empty(); }
203
204      /// useRegsForByval - Returns true if the calling convention allows the
205      /// use of registers to pass byval arguments.
206      bool useRegsForByval() const { return UseRegsForByval; }
207
208      /// regSize - Size (in number of bits) of integer registers.
209      unsigned regSize() const { return RegSize; }
210
211      /// numIntArgRegs - Number of integer registers available for calls.
212      unsigned numIntArgRegs() const { return NumIntArgRegs; }
213
214      /// reservedArgArea - The size of the area the caller reserves for
215      /// register arguments. This is 16-byte if ABI is O32.
216      unsigned reservedArgArea() const { return ReservedArgArea; }
217
218      /// intArgRegs - Pointer to array of integer registers.
219      const uint16_t *intArgRegs() const { return IntArgRegs; }
220
221      typedef SmallVector<ByValArgInfo, 2>::const_iterator byval_iterator;
222      byval_iterator byval_begin() const { return ByValArgs.begin(); }
223      byval_iterator byval_end() const { return ByValArgs.end(); }
224
225    private:
226      void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
227                        unsigned Align);
228
229      CCState &CCInfo;
230      bool UseRegsForByval;
231      unsigned RegSize;
232      unsigned NumIntArgRegs;
233      unsigned ReservedArgArea;
234      const uint16_t *IntArgRegs, *ShadowRegs;
235      SmallVector<ByValArgInfo, 2> ByValArgs;
236      llvm::CCAssignFn *FixedFn, *VarFn;
237    };
238
239    // Subtarget Info
240    const MipsSubtarget *Subtarget;
241
242    bool HasMips64, IsN64, IsO32;
243
244    // Lower Operand helpers
245    SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
246                            CallingConv::ID CallConv, bool isVarArg,
247                            const SmallVectorImpl<ISD::InputArg> &Ins,
248                            DebugLoc dl, SelectionDAG &DAG,
249                            SmallVectorImpl<SDValue> &InVals) const;
250
251    // Lower Operand specifics
252    SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
253    SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
254    SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
255    SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
256    SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
257    SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
258    SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
259    SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
260    SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
261    SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
262    SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
263    SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
264    SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
265    SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
266    SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
267    SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
268    SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
269    SDValue LowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
270                                 bool IsSRA) const;
271    SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
272    SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
273    SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
274    SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
275    SDValue LowerADD(SDValue Op, SelectionDAG &DAG) const;
276
277    /// IsEligibleForTailCallOptimization - Check whether the call is eligible
278    /// for tail call optimization.
279    bool IsEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
280                                           unsigned NextStackOffset,
281                                           const MipsFunctionInfo& FI) const;
282
283    /// copyByValArg - Copy argument registers which were used to pass a byval
284    /// argument to the stack. Create a stack frame object for the byval
285    /// argument.
286    void copyByValRegs(SDValue Chain, DebugLoc DL,
287                       std::vector<SDValue> &OutChains, SelectionDAG &DAG,
288                       const ISD::ArgFlagsTy &Flags,
289                       SmallVectorImpl<SDValue> &InVals,
290                       const Argument *FuncArg,
291                       const MipsCC &CC, const ByValArgInfo &ByVal) const;
292
293    /// passByValArg - Pass a byval argument in registers or on stack.
294    void passByValArg(SDValue Chain, DebugLoc DL,
295                      SmallVector<std::pair<unsigned, SDValue>, 16> &RegsToPass,
296                      SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr,
297                      MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
298                      const MipsCC &CC, const ByValArgInfo &ByVal,
299                      const ISD::ArgFlagsTy &Flags, bool isLittle) const;
300
301    /// writeVarArgRegs - Write variable function arguments passed in registers
302    /// to the stack. Also create a stack frame object for the first variable
303    /// argument.
304    void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
305                         SDValue Chain, DebugLoc DL, SelectionDAG &DAG) const;
306
307    virtual SDValue
308      LowerFormalArguments(SDValue Chain,
309                           CallingConv::ID CallConv, bool isVarArg,
310                           const SmallVectorImpl<ISD::InputArg> &Ins,
311                           DebugLoc dl, SelectionDAG &DAG,
312                           SmallVectorImpl<SDValue> &InVals) const;
313
314    SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
315                           SDValue Arg, DebugLoc DL, bool IsTailCall,
316                           SelectionDAG &DAG) const;
317
318    virtual SDValue
319      LowerCall(TargetLowering::CallLoweringInfo &CLI,
320                SmallVectorImpl<SDValue> &InVals) const;
321
322    virtual bool
323      CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
324                     bool isVarArg,
325                     const SmallVectorImpl<ISD::OutputArg> &Outs,
326                     LLVMContext &Context) const;
327
328    virtual SDValue
329      LowerReturn(SDValue Chain,
330                  CallingConv::ID CallConv, bool isVarArg,
331                  const SmallVectorImpl<ISD::OutputArg> &Outs,
332                  const SmallVectorImpl<SDValue> &OutVals,
333                  DebugLoc dl, SelectionDAG &DAG) const;
334
335    virtual MachineBasicBlock *
336      EmitInstrWithCustomInserter(MachineInstr *MI,
337                                  MachineBasicBlock *MBB) const;
338
339    // Inline asm support
340    ConstraintType getConstraintType(const std::string &Constraint) const;
341
342    /// Examine constraint string and operand type and determine a weight value.
343    /// The operand object must already have been set up with the operand type.
344    ConstraintWeight getSingleConstraintMatchWeight(
345      AsmOperandInfo &info, const char *constraint) const;
346
347    std::pair<unsigned, const TargetRegisterClass*>
348              getRegForInlineAsmConstraint(const std::string &Constraint,
349              EVT VT) const;
350
351    /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
352    /// vector.  If it is invalid, don't add anything to Ops. If hasMemory is
353    /// true it means one of the asm constraint of the inline asm instruction
354    /// being processed is 'm'.
355    virtual void LowerAsmOperandForConstraint(SDValue Op,
356                                              std::string &Constraint,
357                                              std::vector<SDValue> &Ops,
358                                              SelectionDAG &DAG) const;
359
360    virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
361
362    virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
363
364    virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
365                                    unsigned SrcAlign, bool IsZeroVal,
366                                    bool MemcpyStrSrc,
367                                    MachineFunction &MF) const;
368
369    /// isFPImmLegal - Returns true if the target can instruction select the
370    /// specified FP immediate natively. If false, the legalizer will
371    /// materialize the FP immediate as a load from a constant pool.
372    virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
373
374    virtual unsigned getJumpTableEncoding() const;
375
376    MachineBasicBlock *EmitBPOSGE32(MachineInstr *MI,
377                                    MachineBasicBlock *BB) const;
378    MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
379                    unsigned Size, unsigned BinOpcode, bool Nand = false) const;
380    MachineBasicBlock *EmitAtomicBinaryPartword(MachineInstr *MI,
381                    MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
382                    bool Nand = false) const;
383    MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
384                                  MachineBasicBlock *BB, unsigned Size) const;
385    MachineBasicBlock *EmitAtomicCmpSwapPartword(MachineInstr *MI,
386                                  MachineBasicBlock *BB, unsigned Size) const;
387  };
388}
389
390#endif // MipsISELLOWERING_H
391