MipsISelLowering.h revision a284acb8a79468f378452826b2426b4bcdc27e94 
1//===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that Mips uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef MipsISELLOWERING_H
16#define MipsISELLOWERING_H
17
18#include "Mips.h"
19#include "MipsSubtarget.h"
20#include "llvm/CodeGen/SelectionDAG.h"
21#include "llvm/Target/TargetLowering.h"
22
23namespace llvm {
24  namespace MipsISD {
25    enum NodeType {
26      // Start the numbering from where ISD NodeType finishes.
27      FIRST_NUMBER = ISD::BUILTIN_OP_END,
28
29      // Jump and link (call)
30      JmpLink,
31
32      // Get the Higher 16 bits from a 32-bit immediate
33      // No relation with Mips Hi register
34      Hi,
35
36      // Get the Lower 16 bits from a 32-bit immediate
37      // No relation with Mips Lo register
38      Lo,
39
40      // Handle gp_rel (small data/bss sections) relocation.
41      GPRel,
42
43      // Thread Pointer
44      ThreadPointer,
45
46      // Floating Point Branch Conditional
47      FPBrcond,
48
49      // Floating Point Compare
50      FPCmp,
51
52      // Floating Point Conditional Moves
53      CMovFP_T,
54      CMovFP_F,
55
56      // Floating Point Rounding
57      FPRound,
58
59      // Return
60      Ret,
61
62      // MAdd/Sub nodes
63      MAdd,
64      MAddu,
65      MSub,
66      MSubu,
67
68      // DivRem(u)
69      DivRem,
70      DivRemU,
71
72      BuildPairF64,
73      ExtractElementF64,
74
75      Wrapper,
76
77      DynAlloc,
78
79      Sync,
80
81      Ext,
82      Ins
83    };
84  }
85
86  //===--------------------------------------------------------------------===//
87  // TargetLowering Implementation
88  //===--------------------------------------------------------------------===//
89
90  class MipsTargetLowering : public TargetLowering  {
91  public:
92    explicit MipsTargetLowering(MipsTargetMachine &TM);
93
94    virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
95
96    virtual bool allowsUnalignedMemoryAccesses (EVT VT) const;
97
98    /// LowerOperation - Provide custom lowering hooks for some operations.
99    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
100
101    /// getTargetNodeName - This method returns the name of a target specific
102    //  DAG node.
103    virtual const char *getTargetNodeName(unsigned Opcode) const;
104
105    /// getSetCCResultType - get the ISD::SETCC result ValueType
106    EVT getSetCCResultType(EVT VT) const;
107
108    virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
109  private:
110    // Subtarget Info
111    const MipsSubtarget *Subtarget;
112
113    bool HasMips64, IsN64, IsO32;
114
115    // Lower Operand helpers
116    SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
117                            CallingConv::ID CallConv, bool isVarArg,
118                            const SmallVectorImpl<ISD::InputArg> &Ins,
119                            DebugLoc dl, SelectionDAG &DAG,
120                            SmallVectorImpl<SDValue> &InVals) const;
121
122    // Lower Operand specifics
123    SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
124    SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
125    SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
126    SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
127    SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
128    SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
129    SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
130    SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
131    SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
132    SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
133    SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
134    SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
135    SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
136    SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
137    SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
138    SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
139    SDValue LowerShiftRightParts(SDValue Op, SelectionDAG& DAG, bool IsSRA) const;
140
141    virtual SDValue
142      LowerFormalArguments(SDValue Chain,
143                           CallingConv::ID CallConv, bool isVarArg,
144                           const SmallVectorImpl<ISD::InputArg> &Ins,
145                           DebugLoc dl, SelectionDAG &DAG,
146                           SmallVectorImpl<SDValue> &InVals) const;
147
148    virtual SDValue
149      LowerCall(SDValue Chain, SDValue Callee,
150                CallingConv::ID CallConv, bool isVarArg,
151                bool doesNotRet, bool &isTailCall,
152                const SmallVectorImpl<ISD::OutputArg> &Outs,
153                const SmallVectorImpl<SDValue> &OutVals,
154                const SmallVectorImpl<ISD::InputArg> &Ins,
155                DebugLoc dl, SelectionDAG &DAG,
156                SmallVectorImpl<SDValue> &InVals) const;
157
158    virtual SDValue
159      LowerReturn(SDValue Chain,
160                  CallingConv::ID CallConv, bool isVarArg,
161                  const SmallVectorImpl<ISD::OutputArg> &Outs,
162                  const SmallVectorImpl<SDValue> &OutVals,
163                  DebugLoc dl, SelectionDAG &DAG) const;
164
165    virtual MachineBasicBlock *
166      EmitInstrWithCustomInserter(MachineInstr *MI,
167                                  MachineBasicBlock *MBB) const;
168
169    // Inline asm support
170    ConstraintType getConstraintType(const std::string &Constraint) const;
171
172    /// Examine constraint string and operand type and determine a weight value.
173    /// The operand object must already have been set up with the operand type.
174    ConstraintWeight getSingleConstraintMatchWeight(
175      AsmOperandInfo &info, const char *constraint) const;
176
177    std::pair<unsigned, const TargetRegisterClass*>
178              getRegForInlineAsmConstraint(const std::string &Constraint,
179              EVT VT) const;
180
181    /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
182    /// vector.  If it is invalid, don't add anything to Ops. If hasMemory is
183    /// true it means one of the asm constraint of the inline asm instruction
184    /// being processed is 'm'.
185    virtual void LowerAsmOperandForConstraint(SDValue Op,
186                                              std::string &Constraint,
187                                              std::vector<SDValue> &Ops,
188                                              SelectionDAG &DAG) const;
189
190    virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
191
192    /// isFPImmLegal - Returns true if the target can instruction select the
193    /// specified FP immediate natively. If false, the legalizer will
194    /// materialize the FP immediate as a load from a constant pool.
195    virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
196
197    virtual unsigned getJumpTableEncoding() const;
198
199    MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
200                    unsigned Size, unsigned BinOpcode, bool Nand = false) const;
201    MachineBasicBlock *EmitAtomicBinaryPartword(MachineInstr *MI,
202                    MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
203                    bool Nand = false) const;
204    MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
205                                  MachineBasicBlock *BB, unsigned Size) const;
206    MachineBasicBlock *EmitAtomicCmpSwapPartword(MachineInstr *MI,
207                                  MachineBasicBlock *BB, unsigned Size) const;
208  };
209}
210
211#endif // MipsISELLOWERING_H
212