MipsISelLowering.h revision a6b20ced765b67a85d9219d0c8547fc9c133e14f 
1//===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that Mips uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef MipsISELLOWERING_H
16#define MipsISELLOWERING_H
17
18#include "Mips.h"
19#include "MipsSubtarget.h"
20#include "llvm/CodeGen/CallingConvLower.h"
21#include "llvm/CodeGen/SelectionDAG.h"
22#include "llvm/Target/TargetLowering.h"
23#include <deque>
24#include <string>
25
26namespace llvm {
27  namespace MipsISD {
28    enum NodeType {
29      // Start the numbering from where ISD NodeType finishes.
30      FIRST_NUMBER = ISD::BUILTIN_OP_END,
31
32      // Jump and link (call)
33      JmpLink,
34
35      // Tail call
36      TailCall,
37
38      // Get the Higher 16 bits from a 32-bit immediate
39      // No relation with Mips Hi register
40      Hi,
41
42      // Get the Lower 16 bits from a 32-bit immediate
43      // No relation with Mips Lo register
44      Lo,
45
46      // Handle gp_rel (small data/bss sections) relocation.
47      GPRel,
48
49      // Thread Pointer
50      ThreadPointer,
51
52      // Floating Point Branch Conditional
53      FPBrcond,
54
55      // Floating Point Compare
56      FPCmp,
57
58      // Floating Point Conditional Moves
59      CMovFP_T,
60      CMovFP_F,
61
62      // Floating Point Rounding
63      FPRound,
64
65      // Return
66      Ret,
67
68      EH_RETURN,
69
70      // MAdd/Sub nodes
71      MAdd,
72      MAddu,
73      MSub,
74      MSubu,
75
76      // DivRem(u)
77      DivRem,
78      DivRemU,
79
80      BuildPairF64,
81      ExtractElementF64,
82
83      Wrapper,
84
85      DynAlloc,
86
87      Sync,
88
89      Ext,
90      Ins,
91
92      // EXTR.W instrinsic nodes.
93      EXTP,
94      EXTPDP,
95      EXTR_S_H,
96      EXTR_W,
97      EXTR_R_W,
98      EXTR_RS_W,
99      SHILO,
100      MTHLIP,
101
102      // DPA.W intrinsic nodes.
103      MULSAQ_S_W_PH,
104      MAQ_S_W_PHL,
105      MAQ_S_W_PHR,
106      MAQ_SA_W_PHL,
107      MAQ_SA_W_PHR,
108      DPAU_H_QBL,
109      DPAU_H_QBR,
110      DPSU_H_QBL,
111      DPSU_H_QBR,
112      DPAQ_S_W_PH,
113      DPSQ_S_W_PH,
114      DPAQ_SA_L_W,
115      DPSQ_SA_L_W,
116      DPA_W_PH,
117      DPS_W_PH,
118      DPAQX_S_W_PH,
119      DPAQX_SA_W_PH,
120      DPAX_W_PH,
121      DPSX_W_PH,
122      DPSQX_S_W_PH,
123      DPSQX_SA_W_PH,
124      MULSA_W_PH,
125
126      MULT,
127      MULTU,
128      MADD_DSP,
129      MADDU_DSP,
130      MSUB_DSP,
131      MSUBU_DSP,
132
133      // Load/Store Left/Right nodes.
134      LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
135      LWR,
136      SWL,
137      SWR,
138      LDL,
139      LDR,
140      SDL,
141      SDR
142    };
143  }
144
145  //===--------------------------------------------------------------------===//
146  // TargetLowering Implementation
147  //===--------------------------------------------------------------------===//
148  class MipsFunctionInfo;
149
150  class MipsTargetLowering : public TargetLowering  {
151  public:
152    explicit MipsTargetLowering(MipsTargetMachine &TM);
153
154    virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
155
156    virtual bool allowsUnalignedMemoryAccesses (EVT VT, bool *Fast) const;
157
158    virtual void LowerOperationWrapper(SDNode *N,
159                                       SmallVectorImpl<SDValue> &Results,
160                                       SelectionDAG &DAG) const;
161
162    /// LowerOperation - Provide custom lowering hooks for some operations.
163    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
164
165    /// ReplaceNodeResults - Replace the results of node with an illegal result
166    /// type with new values built out of custom code.
167    ///
168    virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
169                                    SelectionDAG &DAG) const;
170
171    /// getTargetNodeName - This method returns the name of a target specific
172    //  DAG node.
173    virtual const char *getTargetNodeName(unsigned Opcode) const;
174
175    /// getSetCCResultType - get the ISD::SETCC result ValueType
176    EVT getSetCCResultType(EVT VT) const;
177
178    virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
179  private:
180
181    void SetMips16LibcallName(RTLIB::Libcall, const char *Name);
182
183    void setMips16HardFloatLibCalls();
184
185    unsigned int
186      getMips16HelperFunctionStubNumber(ArgListTy &Args) const;
187
188    const char *getMips16HelperFunction
189      (Type* RetTy, ArgListTy &Args, bool &needHelper) const;
190
191    /// ByValArgInfo - Byval argument information.
192    struct ByValArgInfo {
193      unsigned FirstIdx; // Index of the first register used.
194      unsigned NumRegs;  // Number of registers used for this argument.
195      unsigned Address;  // Offset of the stack area used to pass this argument.
196
197      ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
198    };
199
200    /// MipsCC - This class provides methods used to analyze formal and call
201    /// arguments and inquire about calling convention information.
202    class MipsCC {
203    public:
204      MipsCC(CallingConv::ID CallConv, bool IsO32, CCState &Info);
205
206      void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
207                               bool IsVarArg);
208      void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins);
209      const CCState &getCCInfo() const { return CCInfo; }
210
211      /// hasByValArg - Returns true if function has byval arguments.
212      bool hasByValArg() const { return !ByValArgs.empty(); }
213
214      /// regSize - Size (in number of bits) of integer registers.
215      unsigned regSize() const { return IsO32 ? 4 : 8; }
216
217      /// numIntArgRegs - Number of integer registers available for calls.
218      unsigned numIntArgRegs() const;
219
220      /// reservedArgArea - The size of the area the caller reserves for
221      /// register arguments. This is 16-byte if ABI is O32.
222      unsigned reservedArgArea() const;
223
224      /// Return pointer to array of integer argument registers.
225      const uint16_t *intArgRegs() const;
226
227      typedef SmallVector<ByValArgInfo, 2>::const_iterator byval_iterator;
228      byval_iterator byval_begin() const { return ByValArgs.begin(); }
229      byval_iterator byval_end() const { return ByValArgs.end(); }
230
231    private:
232      void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
233                          CCValAssign::LocInfo LocInfo,
234                          ISD::ArgFlagsTy ArgFlags);
235
236      /// useRegsForByval - Returns true if the calling convention allows the
237      /// use of registers to pass byval arguments.
238      bool useRegsForByval() const { return CallConv != CallingConv::Fast; }
239
240      /// Return the function that analyzes fixed argument list functions.
241      llvm::CCAssignFn *fixedArgFn() const;
242
243      /// Return the function that analyzes variable argument list functions.
244      llvm::CCAssignFn *varArgFn() const;
245
246      const uint16_t *shadowRegs() const;
247
248      void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
249                        unsigned Align);
250
251      CCState &CCInfo;
252      CallingConv::ID CallConv;
253      bool IsO32;
254      SmallVector<ByValArgInfo, 2> ByValArgs;
255    };
256
257    // Subtarget Info
258    const MipsSubtarget *Subtarget;
259
260    bool HasMips64, IsN64, IsO32;
261
262    // Lower Operand helpers
263    SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
264                            CallingConv::ID CallConv, bool isVarArg,
265                            const SmallVectorImpl<ISD::InputArg> &Ins,
266                            DebugLoc dl, SelectionDAG &DAG,
267                            SmallVectorImpl<SDValue> &InVals) const;
268
269    // Lower Operand specifics
270    SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
271    SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
272    SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
273    SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
274    SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
275    SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
276    SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
277    SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
278    SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
279    SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
280    SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
281    SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
282    SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
283    SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
284    SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
285    SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
286    SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
287    SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
288    SDValue LowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
289                                 bool IsSRA) const;
290    SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
291    SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
292    SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
293    SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
294    SDValue LowerADD(SDValue Op, SelectionDAG &DAG) const;
295
296    /// IsEligibleForTailCallOptimization - Check whether the call is eligible
297    /// for tail call optimization.
298    bool IsEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
299                                           unsigned NextStackOffset,
300                                           const MipsFunctionInfo& FI) const;
301
302    /// copyByValArg - Copy argument registers which were used to pass a byval
303    /// argument to the stack. Create a stack frame object for the byval
304    /// argument.
305    void copyByValRegs(SDValue Chain, DebugLoc DL,
306                       std::vector<SDValue> &OutChains, SelectionDAG &DAG,
307                       const ISD::ArgFlagsTy &Flags,
308                       SmallVectorImpl<SDValue> &InVals,
309                       const Argument *FuncArg,
310                       const MipsCC &CC, const ByValArgInfo &ByVal) const;
311
312    /// passByValArg - Pass a byval argument in registers or on stack.
313    void passByValArg(SDValue Chain, DebugLoc DL,
314                      std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
315                      SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr,
316                      MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
317                      const MipsCC &CC, const ByValArgInfo &ByVal,
318                      const ISD::ArgFlagsTy &Flags, bool isLittle) const;
319
320    /// writeVarArgRegs - Write variable function arguments passed in registers
321    /// to the stack. Also create a stack frame object for the first variable
322    /// argument.
323    void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
324                         SDValue Chain, DebugLoc DL, SelectionDAG &DAG) const;
325
326    virtual SDValue
327      LowerFormalArguments(SDValue Chain,
328                           CallingConv::ID CallConv, bool isVarArg,
329                           const SmallVectorImpl<ISD::InputArg> &Ins,
330                           DebugLoc dl, SelectionDAG &DAG,
331                           SmallVectorImpl<SDValue> &InVals) const;
332
333    SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
334                           SDValue Arg, DebugLoc DL, bool IsTailCall,
335                           SelectionDAG &DAG) const;
336
337    virtual SDValue
338      LowerCall(TargetLowering::CallLoweringInfo &CLI,
339                SmallVectorImpl<SDValue> &InVals) const;
340
341    virtual bool
342      CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
343                     bool isVarArg,
344                     const SmallVectorImpl<ISD::OutputArg> &Outs,
345                     LLVMContext &Context) const;
346
347    virtual SDValue
348      LowerReturn(SDValue Chain,
349                  CallingConv::ID CallConv, bool isVarArg,
350                  const SmallVectorImpl<ISD::OutputArg> &Outs,
351                  const SmallVectorImpl<SDValue> &OutVals,
352                  DebugLoc dl, SelectionDAG &DAG) const;
353
354    virtual MachineBasicBlock *
355      EmitInstrWithCustomInserter(MachineInstr *MI,
356                                  MachineBasicBlock *MBB) const;
357
358    // Inline asm support
359    ConstraintType getConstraintType(const std::string &Constraint) const;
360
361    /// Examine constraint string and operand type and determine a weight value.
362    /// The operand object must already have been set up with the operand type.
363    ConstraintWeight getSingleConstraintMatchWeight(
364      AsmOperandInfo &info, const char *constraint) const;
365
366    std::pair<unsigned, const TargetRegisterClass*>
367              getRegForInlineAsmConstraint(const std::string &Constraint,
368              EVT VT) const;
369
370    /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
371    /// vector.  If it is invalid, don't add anything to Ops. If hasMemory is
372    /// true it means one of the asm constraint of the inline asm instruction
373    /// being processed is 'm'.
374    virtual void LowerAsmOperandForConstraint(SDValue Op,
375                                              std::string &Constraint,
376                                              std::vector<SDValue> &Ops,
377                                              SelectionDAG &DAG) const;
378
379    virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
380
381    virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
382
383    virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
384                                    unsigned SrcAlign,
385                                    bool IsMemset, bool ZeroMemset,
386                                    bool MemcpyStrSrc,
387                                    MachineFunction &MF) const;
388
389    /// isFPImmLegal - Returns true if the target can instruction select the
390    /// specified FP immediate natively. If false, the legalizer will
391    /// materialize the FP immediate as a load from a constant pool.
392    virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
393
394    virtual unsigned getJumpTableEncoding() const;
395
396    MachineBasicBlock *EmitBPOSGE32(MachineInstr *MI,
397                                    MachineBasicBlock *BB) const;
398    MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
399                    unsigned Size, unsigned BinOpcode, bool Nand = false) const;
400    MachineBasicBlock *EmitAtomicBinaryPartword(MachineInstr *MI,
401                    MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
402                    bool Nand = false) const;
403    MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
404                                  MachineBasicBlock *BB, unsigned Size) const;
405    MachineBasicBlock *EmitAtomicCmpSwapPartword(MachineInstr *MI,
406                                  MachineBasicBlock *BB, unsigned Size) const;
407    MachineBasicBlock *EmitSel16(unsigned Opc, MachineInstr *MI,
408                                 MachineBasicBlock *BB) const;
409    MachineBasicBlock *EmitSeliT16(unsigned Opc1, unsigned Opc2,
410                                  MachineInstr *MI,
411                                  MachineBasicBlock *BB) const;
412
413    MachineBasicBlock *EmitSelT16(unsigned Opc1, unsigned Opc2,
414                                  MachineInstr *MI,
415                                  MachineBasicBlock *BB) const;
416    MachineBasicBlock *EmitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc,
417                               MachineInstr *MI,
418                               MachineBasicBlock *BB) const;
419    MachineBasicBlock *EmitFEXT_T8I8I16_ins(
420      unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc,
421      MachineInstr *MI,  MachineBasicBlock *BB) const;
422    MachineBasicBlock *EmitFEXT_CCRX16_ins(
423      unsigned SltOpc,
424      MachineInstr *MI,  MachineBasicBlock *BB) const;
425    MachineBasicBlock *EmitFEXT_CCRXI16_ins(
426      unsigned SltiOpc, unsigned SltiXOpc,
427      MachineInstr *MI,  MachineBasicBlock *BB )const;
428
429  };
430}
431
432#endif // MipsISELLOWERING_H
433