MipsISelLowering.h revision cb2eafdfa358ae8a1e1f9ae39d8c72cd4d446da1 
1//===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that Mips uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef MipsISELLOWERING_H
16#define MipsISELLOWERING_H
17
18#include "Mips.h"
19#include "MipsSubtarget.h"
20#include "llvm/CodeGen/CallingConvLower.h"
21#include "llvm/CodeGen/SelectionDAG.h"
22#include "llvm/IR/Function.h"
23#include "llvm/Target/TargetLowering.h"
24#include <deque>
25#include <string>
26
27namespace llvm {
28  namespace MipsISD {
29    enum NodeType {
30      // Start the numbering from where ISD NodeType finishes.
31      FIRST_NUMBER = ISD::BUILTIN_OP_END,
32
33      // Jump and link (call)
34      JmpLink,
35
36      // Tail call
37      TailCall,
38
39      // Get the Higher 16 bits from a 32-bit immediate
40      // No relation with Mips Hi register
41      Hi,
42
43      // Get the Lower 16 bits from a 32-bit immediate
44      // No relation with Mips Lo register
45      Lo,
46
47      // Handle gp_rel (small data/bss sections) relocation.
48      GPRel,
49
50      // Thread Pointer
51      ThreadPointer,
52
53      // Floating Point Branch Conditional
54      FPBrcond,
55
56      // Floating Point Compare
57      FPCmp,
58
59      // Floating Point Conditional Moves
60      CMovFP_T,
61      CMovFP_F,
62
63      // Floating Point Rounding
64      FPRound,
65
66      // Return
67      Ret,
68
69      EH_RETURN,
70
71      // MAdd/Sub nodes
72      MAdd,
73      MAddu,
74      MSub,
75      MSubu,
76
77      // DivRem(u)
78      DivRem,
79      DivRemU,
80
81      BuildPairF64,
82      ExtractElementF64,
83
84      Wrapper,
85
86      DynAlloc,
87
88      Sync,
89
90      Ext,
91      Ins,
92
93      // EXTR.W instrinsic nodes.
94      EXTP,
95      EXTPDP,
96      EXTR_S_H,
97      EXTR_W,
98      EXTR_R_W,
99      EXTR_RS_W,
100      SHILO,
101      MTHLIP,
102
103      // DPA.W intrinsic nodes.
104      MULSAQ_S_W_PH,
105      MAQ_S_W_PHL,
106      MAQ_S_W_PHR,
107      MAQ_SA_W_PHL,
108      MAQ_SA_W_PHR,
109      DPAU_H_QBL,
110      DPAU_H_QBR,
111      DPSU_H_QBL,
112      DPSU_H_QBR,
113      DPAQ_S_W_PH,
114      DPSQ_S_W_PH,
115      DPAQ_SA_L_W,
116      DPSQ_SA_L_W,
117      DPA_W_PH,
118      DPS_W_PH,
119      DPAQX_S_W_PH,
120      DPAQX_SA_W_PH,
121      DPAX_W_PH,
122      DPSX_W_PH,
123      DPSQX_S_W_PH,
124      DPSQX_SA_W_PH,
125      MULSA_W_PH,
126
127      MULT,
128      MULTU,
129      MADD_DSP,
130      MADDU_DSP,
131      MSUB_DSP,
132      MSUBU_DSP,
133
134      // Load/Store Left/Right nodes.
135      LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
136      LWR,
137      SWL,
138      SWR,
139      LDL,
140      LDR,
141      SDL,
142      SDR
143    };
144  }
145
146  //===--------------------------------------------------------------------===//
147  // TargetLowering Implementation
148  //===--------------------------------------------------------------------===//
149  class MipsFunctionInfo;
150
151  class MipsTargetLowering : public TargetLowering  {
152  public:
153    explicit MipsTargetLowering(MipsTargetMachine &TM);
154
155    virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
156
157    virtual bool allowsUnalignedMemoryAccesses (EVT VT, bool *Fast) const;
158
159    virtual void LowerOperationWrapper(SDNode *N,
160                                       SmallVectorImpl<SDValue> &Results,
161                                       SelectionDAG &DAG) const;
162
163    /// LowerOperation - Provide custom lowering hooks for some operations.
164    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
165
166    /// ReplaceNodeResults - Replace the results of node with an illegal result
167    /// type with new values built out of custom code.
168    ///
169    virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
170                                    SelectionDAG &DAG) const;
171
172    /// getTargetNodeName - This method returns the name of a target specific
173    //  DAG node.
174    virtual const char *getTargetNodeName(unsigned Opcode) const;
175
176    /// getSetCCResultType - get the ISD::SETCC result ValueType
177    EVT getSetCCResultType(EVT VT) const;
178
179    virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
180  private:
181
182    void SetMips16LibcallName(RTLIB::Libcall, const char *Name);
183
184    void setMips16HardFloatLibCalls();
185
186    unsigned int
187      getMips16HelperFunctionStubNumber(ArgListTy &Args) const;
188
189    const char *getMips16HelperFunction
190      (Type* RetTy, ArgListTy &Args, bool &needHelper) const;
191
192    /// ByValArgInfo - Byval argument information.
193    struct ByValArgInfo {
194      unsigned FirstIdx; // Index of the first register used.
195      unsigned NumRegs;  // Number of registers used for this argument.
196      unsigned Address;  // Offset of the stack area used to pass this argument.
197
198      ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
199    };
200
201    /// MipsCC - This class provides methods used to analyze formal and call
202    /// arguments and inquire about calling convention information.
203    class MipsCC {
204    public:
205      MipsCC(CallingConv::ID CallConv, bool IsO32, CCState &Info);
206
207      void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
208                               bool IsVarArg, bool IsSoftFloat,
209                               const SDNode *CallNode,
210                               std::vector<ArgListEntry> &FuncArgs);
211      void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
212                                  bool IsSoftFloat,
213                                  Function::const_arg_iterator FuncArg);
214      const CCState &getCCInfo() const { return CCInfo; }
215
216      /// hasByValArg - Returns true if function has byval arguments.
217      bool hasByValArg() const { return !ByValArgs.empty(); }
218
219      /// regSize - Size (in number of bits) of integer registers.
220      unsigned regSize() const { return IsO32 ? 4 : 8; }
221
222      /// numIntArgRegs - Number of integer registers available for calls.
223      unsigned numIntArgRegs() const;
224
225      /// reservedArgArea - The size of the area the caller reserves for
226      /// register arguments. This is 16-byte if ABI is O32.
227      unsigned reservedArgArea() const;
228
229      /// Return pointer to array of integer argument registers.
230      const uint16_t *intArgRegs() const;
231
232      typedef SmallVector<ByValArgInfo, 2>::const_iterator byval_iterator;
233      byval_iterator byval_begin() const { return ByValArgs.begin(); }
234      byval_iterator byval_end() const { return ByValArgs.end(); }
235
236    private:
237      void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
238                          CCValAssign::LocInfo LocInfo,
239                          ISD::ArgFlagsTy ArgFlags);
240
241      /// useRegsForByval - Returns true if the calling convention allows the
242      /// use of registers to pass byval arguments.
243      bool useRegsForByval() const { return CallConv != CallingConv::Fast; }
244
245      /// Return the function that analyzes fixed argument list functions.
246      llvm::CCAssignFn *fixedArgFn() const;
247
248      /// Return the function that analyzes variable argument list functions.
249      llvm::CCAssignFn *varArgFn() const;
250
251      const uint16_t *shadowRegs() const;
252
253      void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
254                        unsigned Align);
255
256      /// Return the type of the register which is used to pass an argument or
257      /// return a value. This function returns f64 if the argument is an i64
258      /// value which has been generated as a result of softening an f128 value.
259      /// Otherwise, it just returns VT.
260      MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode,
261                   bool IsSoftFloat) const;
262
263      CCState &CCInfo;
264      CallingConv::ID CallConv;
265      bool IsO32;
266      SmallVector<ByValArgInfo, 2> ByValArgs;
267    };
268
269    // Subtarget Info
270    const MipsSubtarget *Subtarget;
271
272    bool HasMips64, IsN64, IsO32;
273
274    // Lower Operand helpers
275    SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
276                            CallingConv::ID CallConv, bool isVarArg,
277                            const SmallVectorImpl<ISD::InputArg> &Ins,
278                            DebugLoc dl, SelectionDAG &DAG,
279                            SmallVectorImpl<SDValue> &InVals) const;
280
281    // Lower Operand specifics
282    SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
283    SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
284    SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
285    SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
286    SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
287    SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
288    SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
289    SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
290    SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
291    SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
292    SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
293    SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
294    SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
295    SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
296    SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
297    SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
298    SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
299    SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
300    SDValue LowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
301                                 bool IsSRA) const;
302    SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
303    SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
304    SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
305    SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
306    SDValue LowerADD(SDValue Op, SelectionDAG &DAG) const;
307
308    /// IsEligibleForTailCallOptimization - Check whether the call is eligible
309    /// for tail call optimization.
310    bool IsEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
311                                           unsigned NextStackOffset,
312                                           const MipsFunctionInfo& FI) const;
313
314    /// copyByValArg - Copy argument registers which were used to pass a byval
315    /// argument to the stack. Create a stack frame object for the byval
316    /// argument.
317    void copyByValRegs(SDValue Chain, DebugLoc DL,
318                       std::vector<SDValue> &OutChains, SelectionDAG &DAG,
319                       const ISD::ArgFlagsTy &Flags,
320                       SmallVectorImpl<SDValue> &InVals,
321                       const Argument *FuncArg,
322                       const MipsCC &CC, const ByValArgInfo &ByVal) const;
323
324    /// passByValArg - Pass a byval argument in registers or on stack.
325    void passByValArg(SDValue Chain, DebugLoc DL,
326                      std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
327                      SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr,
328                      MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
329                      const MipsCC &CC, const ByValArgInfo &ByVal,
330                      const ISD::ArgFlagsTy &Flags, bool isLittle) const;
331
332    /// writeVarArgRegs - Write variable function arguments passed in registers
333    /// to the stack. Also create a stack frame object for the first variable
334    /// argument.
335    void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
336                         SDValue Chain, DebugLoc DL, SelectionDAG &DAG) const;
337
338    virtual SDValue
339      LowerFormalArguments(SDValue Chain,
340                           CallingConv::ID CallConv, bool isVarArg,
341                           const SmallVectorImpl<ISD::InputArg> &Ins,
342                           DebugLoc dl, SelectionDAG &DAG,
343                           SmallVectorImpl<SDValue> &InVals) const;
344
345    SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
346                           SDValue Arg, DebugLoc DL, bool IsTailCall,
347                           SelectionDAG &DAG) const;
348
349    virtual SDValue
350      LowerCall(TargetLowering::CallLoweringInfo &CLI,
351                SmallVectorImpl<SDValue> &InVals) const;
352
353    virtual bool
354      CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
355                     bool isVarArg,
356                     const SmallVectorImpl<ISD::OutputArg> &Outs,
357                     LLVMContext &Context) const;
358
359    virtual SDValue
360      LowerReturn(SDValue Chain,
361                  CallingConv::ID CallConv, bool isVarArg,
362                  const SmallVectorImpl<ISD::OutputArg> &Outs,
363                  const SmallVectorImpl<SDValue> &OutVals,
364                  DebugLoc dl, SelectionDAG &DAG) const;
365
366    virtual MachineBasicBlock *
367      EmitInstrWithCustomInserter(MachineInstr *MI,
368                                  MachineBasicBlock *MBB) const;
369
370    // Inline asm support
371    ConstraintType getConstraintType(const std::string &Constraint) const;
372
373    /// Examine constraint string and operand type and determine a weight value.
374    /// The operand object must already have been set up with the operand type.
375    ConstraintWeight getSingleConstraintMatchWeight(
376      AsmOperandInfo &info, const char *constraint) const;
377
378    std::pair<unsigned, const TargetRegisterClass*>
379              getRegForInlineAsmConstraint(const std::string &Constraint,
380              EVT VT) const;
381
382    /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
383    /// vector.  If it is invalid, don't add anything to Ops. If hasMemory is
384    /// true it means one of the asm constraint of the inline asm instruction
385    /// being processed is 'm'.
386    virtual void LowerAsmOperandForConstraint(SDValue Op,
387                                              std::string &Constraint,
388                                              std::vector<SDValue> &Ops,
389                                              SelectionDAG &DAG) const;
390
391    virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
392
393    virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
394
395    virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
396                                    unsigned SrcAlign,
397                                    bool IsMemset, bool ZeroMemset,
398                                    bool MemcpyStrSrc,
399                                    MachineFunction &MF) const;
400
401    /// isFPImmLegal - Returns true if the target can instruction select the
402    /// specified FP immediate natively. If false, the legalizer will
403    /// materialize the FP immediate as a load from a constant pool.
404    virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
405
406    virtual unsigned getJumpTableEncoding() const;
407
408    MachineBasicBlock *EmitBPOSGE32(MachineInstr *MI,
409                                    MachineBasicBlock *BB) const;
410    MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
411                    unsigned Size, unsigned BinOpcode, bool Nand = false) const;
412    MachineBasicBlock *EmitAtomicBinaryPartword(MachineInstr *MI,
413                    MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
414                    bool Nand = false) const;
415    MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
416                                  MachineBasicBlock *BB, unsigned Size) const;
417    MachineBasicBlock *EmitAtomicCmpSwapPartword(MachineInstr *MI,
418                                  MachineBasicBlock *BB, unsigned Size) const;
419    MachineBasicBlock *EmitSel16(unsigned Opc, MachineInstr *MI,
420                                 MachineBasicBlock *BB) const;
421    MachineBasicBlock *EmitSeliT16(unsigned Opc1, unsigned Opc2,
422                                  MachineInstr *MI,
423                                  MachineBasicBlock *BB) const;
424
425    MachineBasicBlock *EmitSelT16(unsigned Opc1, unsigned Opc2,
426                                  MachineInstr *MI,
427                                  MachineBasicBlock *BB) const;
428    MachineBasicBlock *EmitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc,
429                               MachineInstr *MI,
430                               MachineBasicBlock *BB) const;
431    MachineBasicBlock *EmitFEXT_T8I8I16_ins(
432      unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc,
433      MachineInstr *MI,  MachineBasicBlock *BB) const;
434    MachineBasicBlock *EmitFEXT_CCRX16_ins(
435      unsigned SltOpc,
436      MachineInstr *MI,  MachineBasicBlock *BB) const;
437    MachineBasicBlock *EmitFEXT_CCRXI16_ins(
438      unsigned SltiOpc, unsigned SltiXOpc,
439      MachineInstr *MI,  MachineBasicBlock *BB )const;
440
441  };
442}
443
444#endif // MipsISELLOWERING_H
445