MipsISelLowering.h revision cd6c57917db22a3913a2cdbadfa79fed3547bdec 
1//===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that Mips uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef MipsISELLOWERING_H
16#define MipsISELLOWERING_H
17
18#include "Mips.h"
19#include "MipsSubtarget.h"
20#include "llvm/CodeGen/CallingConvLower.h"
21#include "llvm/CodeGen/SelectionDAG.h"
22#include "llvm/IR/Function.h"
23#include "llvm/Target/TargetLowering.h"
24#include <deque>
25#include <string>
26
27namespace llvm {
28  namespace MipsISD {
29    enum NodeType {
30      // Start the numbering from where ISD NodeType finishes.
31      FIRST_NUMBER = ISD::BUILTIN_OP_END,
32
33      // Jump and link (call)
34      JmpLink,
35
36      // Tail call
37      TailCall,
38
39      // Get the Higher 16 bits from a 32-bit immediate
40      // No relation with Mips Hi register
41      Hi,
42
43      // Get the Lower 16 bits from a 32-bit immediate
44      // No relation with Mips Lo register
45      Lo,
46
47      // Handle gp_rel (small data/bss sections) relocation.
48      GPRel,
49
50      // Thread Pointer
51      ThreadPointer,
52
53      // Floating Point Branch Conditional
54      FPBrcond,
55
56      // Floating Point Compare
57      FPCmp,
58
59      // Floating Point Conditional Moves
60      CMovFP_T,
61      CMovFP_F,
62
63      // Floating Point Rounding
64      FPRound,
65
66      // Return
67      Ret,
68
69      EH_RETURN,
70
71      // Node used to extract integer from accumulator.
72      ExtractLOHI,
73
74      // Node used to insert integers to accumulator.
75      InsertLOHI,
76
77      // Mult nodes.
78      Mult,
79      Multu,
80
81      // MAdd/Sub nodes
82      MAdd,
83      MAddu,
84      MSub,
85      MSubu,
86
87      // DivRem(u)
88      DivRem,
89      DivRemU,
90      DivRem16,
91      DivRemU16,
92
93      BuildPairF64,
94      ExtractElementF64,
95
96      Wrapper,
97
98      DynAlloc,
99
100      Sync,
101
102      Ext,
103      Ins,
104
105      // EXTR.W instrinsic nodes.
106      EXTP,
107      EXTPDP,
108      EXTR_S_H,
109      EXTR_W,
110      EXTR_R_W,
111      EXTR_RS_W,
112      SHILO,
113      MTHLIP,
114
115      // DPA.W intrinsic nodes.
116      MULSAQ_S_W_PH,
117      MAQ_S_W_PHL,
118      MAQ_S_W_PHR,
119      MAQ_SA_W_PHL,
120      MAQ_SA_W_PHR,
121      DPAU_H_QBL,
122      DPAU_H_QBR,
123      DPSU_H_QBL,
124      DPSU_H_QBR,
125      DPAQ_S_W_PH,
126      DPSQ_S_W_PH,
127      DPAQ_SA_L_W,
128      DPSQ_SA_L_W,
129      DPA_W_PH,
130      DPS_W_PH,
131      DPAQX_S_W_PH,
132      DPAQX_SA_W_PH,
133      DPAX_W_PH,
134      DPSX_W_PH,
135      DPSQX_S_W_PH,
136      DPSQX_SA_W_PH,
137      MULSA_W_PH,
138
139      MULT,
140      MULTU,
141      MADD_DSP,
142      MADDU_DSP,
143      MSUB_DSP,
144      MSUBU_DSP,
145
146      // DSP shift nodes.
147      SHLL_DSP,
148      SHRA_DSP,
149      SHRL_DSP,
150
151      // DSP setcc and select_cc nodes.
152      SETCC_DSP,
153      SELECT_CC_DSP,
154
155      // Load/Store Left/Right nodes.
156      LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
157      LWR,
158      SWL,
159      SWR,
160      LDL,
161      LDR,
162      SDL,
163      SDR
164    };
165  }
166
167  //===--------------------------------------------------------------------===//
168  // TargetLowering Implementation
169  //===--------------------------------------------------------------------===//
170  class MipsFunctionInfo;
171
172  class MipsTargetLowering : public TargetLowering  {
173  public:
174    explicit MipsTargetLowering(MipsTargetMachine &TM);
175
176    static const MipsTargetLowering *create(MipsTargetMachine &TM);
177
178    virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
179
180    virtual void LowerOperationWrapper(SDNode *N,
181                                       SmallVectorImpl<SDValue> &Results,
182                                       SelectionDAG &DAG) const;
183
184    /// LowerOperation - Provide custom lowering hooks for some operations.
185    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
186
187    /// ReplaceNodeResults - Replace the results of node with an illegal result
188    /// type with new values built out of custom code.
189    ///
190    virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
191                                    SelectionDAG &DAG) const;
192
193    /// getTargetNodeName - This method returns the name of a target specific
194    //  DAG node.
195    virtual const char *getTargetNodeName(unsigned Opcode) const;
196
197    /// getSetCCResultType - get the ISD::SETCC result ValueType
198    EVT getSetCCResultType(EVT VT) const;
199
200    virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
201
202    virtual MachineBasicBlock *
203    EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
204
205    struct LTStr {
206      bool operator()(const char *S1, const char *S2) const {
207        return strcmp(S1, S2) < 0;
208      }
209    };
210
211  protected:
212    SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
213
214    SDValue getAddrLocal(SDValue Op, SelectionDAG &DAG, bool HasMips64) const;
215
216    SDValue getAddrGlobal(SDValue Op, SelectionDAG &DAG, unsigned Flag) const;
217
218    SDValue getAddrGlobalLargeGOT(SDValue Op, SelectionDAG &DAG,
219                                  unsigned HiFlag, unsigned LoFlag) const;
220
221    /// This function fills Ops, which is the list of operands that will later
222    /// be used when a function call node is created. It also generates
223    /// copyToReg nodes to set up argument registers.
224    virtual void
225    getOpndList(SmallVectorImpl<SDValue> &Ops,
226                std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
227                bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
228                CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
229
230    /// ByValArgInfo - Byval argument information.
231    struct ByValArgInfo {
232      unsigned FirstIdx; // Index of the first register used.
233      unsigned NumRegs;  // Number of registers used for this argument.
234      unsigned Address;  // Offset of the stack area used to pass this argument.
235
236      ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
237    };
238
239    /// MipsCC - This class provides methods used to analyze formal and call
240    /// arguments and inquire about calling convention information.
241    class MipsCC {
242    public:
243      MipsCC(CallingConv::ID CallConv, bool IsO32, CCState &Info);
244
245      void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
246                               bool IsVarArg, bool IsSoftFloat,
247                               const SDNode *CallNode,
248                               std::vector<ArgListEntry> &FuncArgs);
249      void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
250                                  bool IsSoftFloat,
251                                  Function::const_arg_iterator FuncArg);
252
253      void analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
254                             bool IsSoftFloat, const SDNode *CallNode,
255                             const Type *RetTy) const;
256
257      void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
258                         bool IsSoftFloat, const Type *RetTy) const;
259
260      const CCState &getCCInfo() const { return CCInfo; }
261
262      /// hasByValArg - Returns true if function has byval arguments.
263      bool hasByValArg() const { return !ByValArgs.empty(); }
264
265      /// regSize - Size (in number of bits) of integer registers.
266      unsigned regSize() const { return IsO32 ? 4 : 8; }
267
268      /// numIntArgRegs - Number of integer registers available for calls.
269      unsigned numIntArgRegs() const;
270
271      /// reservedArgArea - The size of the area the caller reserves for
272      /// register arguments. This is 16-byte if ABI is O32.
273      unsigned reservedArgArea() const;
274
275      /// Return pointer to array of integer argument registers.
276      const uint16_t *intArgRegs() const;
277
278      typedef SmallVector<ByValArgInfo, 2>::const_iterator byval_iterator;
279      byval_iterator byval_begin() const { return ByValArgs.begin(); }
280      byval_iterator byval_end() const { return ByValArgs.end(); }
281
282    private:
283      void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
284                          CCValAssign::LocInfo LocInfo,
285                          ISD::ArgFlagsTy ArgFlags);
286
287      /// useRegsForByval - Returns true if the calling convention allows the
288      /// use of registers to pass byval arguments.
289      bool useRegsForByval() const { return CallConv != CallingConv::Fast; }
290
291      /// Return the function that analyzes fixed argument list functions.
292      llvm::CCAssignFn *fixedArgFn() const;
293
294      /// Return the function that analyzes variable argument list functions.
295      llvm::CCAssignFn *varArgFn() const;
296
297      const uint16_t *shadowRegs() const;
298
299      void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
300                        unsigned Align);
301
302      /// Return the type of the register which is used to pass an argument or
303      /// return a value. This function returns f64 if the argument is an i64
304      /// value which has been generated as a result of softening an f128 value.
305      /// Otherwise, it just returns VT.
306      MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode,
307                   bool IsSoftFloat) const;
308
309      template<typename Ty>
310      void analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat,
311                         const SDNode *CallNode, const Type *RetTy) const;
312
313      CCState &CCInfo;
314      CallingConv::ID CallConv;
315      bool IsO32;
316      SmallVector<ByValArgInfo, 2> ByValArgs;
317    };
318
319    // Subtarget Info
320    const MipsSubtarget *Subtarget;
321
322    bool HasMips64, IsN64, IsO32;
323
324  private:
325    // Lower Operand helpers
326    SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
327                            CallingConv::ID CallConv, bool isVarArg,
328                            const SmallVectorImpl<ISD::InputArg> &Ins,
329                            DebugLoc dl, SelectionDAG &DAG,
330                            SmallVectorImpl<SDValue> &InVals,
331                            const SDNode *CallNode, const Type *RetTy) const;
332
333    // Lower Operand specifics
334    SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
335    SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
336    SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
337    SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
338    SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
339    SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
340    SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
341    SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
342    SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
343    SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
344    SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
345    SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
346    SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
347    SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
348    SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
349    SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
350    SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
351    SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
352    SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
353                                 bool IsSRA) const;
354    SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
355    SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
356    SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
357
358    /// isEligibleForTailCallOptimization - Check whether the call is eligible
359    /// for tail call optimization.
360    virtual bool
361    isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
362                                      unsigned NextStackOffset,
363                                      const MipsFunctionInfo& FI) const = 0;
364
365    /// copyByValArg - Copy argument registers which were used to pass a byval
366    /// argument to the stack. Create a stack frame object for the byval
367    /// argument.
368    void copyByValRegs(SDValue Chain, DebugLoc DL,
369                       std::vector<SDValue> &OutChains, SelectionDAG &DAG,
370                       const ISD::ArgFlagsTy &Flags,
371                       SmallVectorImpl<SDValue> &InVals,
372                       const Argument *FuncArg,
373                       const MipsCC &CC, const ByValArgInfo &ByVal) const;
374
375    /// passByValArg - Pass a byval argument in registers or on stack.
376    void passByValArg(SDValue Chain, DebugLoc DL,
377                      std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
378                      SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr,
379                      MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
380                      const MipsCC &CC, const ByValArgInfo &ByVal,
381                      const ISD::ArgFlagsTy &Flags, bool isLittle) const;
382
383    /// writeVarArgRegs - Write variable function arguments passed in registers
384    /// to the stack. Also create a stack frame object for the first variable
385    /// argument.
386    void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
387                         SDValue Chain, DebugLoc DL, SelectionDAG &DAG) const;
388
389    virtual SDValue
390      LowerFormalArguments(SDValue Chain,
391                           CallingConv::ID CallConv, bool isVarArg,
392                           const SmallVectorImpl<ISD::InputArg> &Ins,
393                           DebugLoc dl, SelectionDAG &DAG,
394                           SmallVectorImpl<SDValue> &InVals) const;
395
396    SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
397                           SDValue Arg, DebugLoc DL, bool IsTailCall,
398                           SelectionDAG &DAG) const;
399
400    virtual SDValue
401      LowerCall(TargetLowering::CallLoweringInfo &CLI,
402                SmallVectorImpl<SDValue> &InVals) const;
403
404    virtual bool
405      CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
406                     bool isVarArg,
407                     const SmallVectorImpl<ISD::OutputArg> &Outs,
408                     LLVMContext &Context) const;
409
410    virtual SDValue
411      LowerReturn(SDValue Chain,
412                  CallingConv::ID CallConv, bool isVarArg,
413                  const SmallVectorImpl<ISD::OutputArg> &Outs,
414                  const SmallVectorImpl<SDValue> &OutVals,
415                  DebugLoc dl, SelectionDAG &DAG) const;
416
417    // Inline asm support
418    ConstraintType getConstraintType(const std::string &Constraint) const;
419
420    /// Examine constraint string and operand type and determine a weight value.
421    /// The operand object must already have been set up with the operand type.
422    ConstraintWeight getSingleConstraintMatchWeight(
423      AsmOperandInfo &info, const char *constraint) const;
424
425    std::pair<unsigned, const TargetRegisterClass*>
426              getRegForInlineAsmConstraint(const std::string &Constraint,
427              EVT VT) const;
428
429    /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
430    /// vector.  If it is invalid, don't add anything to Ops. If hasMemory is
431    /// true it means one of the asm constraint of the inline asm instruction
432    /// being processed is 'm'.
433    virtual void LowerAsmOperandForConstraint(SDValue Op,
434                                              std::string &Constraint,
435                                              std::vector<SDValue> &Ops,
436                                              SelectionDAG &DAG) const;
437
438    virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
439
440    virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
441
442    virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
443                                    unsigned SrcAlign,
444                                    bool IsMemset, bool ZeroMemset,
445                                    bool MemcpyStrSrc,
446                                    MachineFunction &MF) const;
447
448    /// isFPImmLegal - Returns true if the target can instruction select the
449    /// specified FP immediate natively. If false, the legalizer will
450    /// materialize the FP immediate as a load from a constant pool.
451    virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
452
453    virtual unsigned getJumpTableEncoding() const;
454
455    MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
456                    unsigned Size, unsigned BinOpcode, bool Nand = false) const;
457    MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
458                    MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
459                    bool Nand = false) const;
460    MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
461                                  MachineBasicBlock *BB, unsigned Size) const;
462    MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
463                                  MachineBasicBlock *BB, unsigned Size) const;
464  };
465
466  /// Create MipsTargetLowering objects.
467  const MipsTargetLowering *createMips16TargetLowering(MipsTargetMachine &TM);
468  const MipsTargetLowering *createMipsSETargetLowering(MipsTargetMachine &TM);
469}
470
471#endif // MipsISELLOWERING_H
472