MipsISelLowering.h revision da521cc1cc733ee1c27b00e4c0e365c8b702e2e0 
1//===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that Mips uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef MipsISELLOWERING_H
16#define MipsISELLOWERING_H
17
18#include "Mips.h"
19#include "MipsSubtarget.h"
20#include "llvm/CodeGen/CallingConvLower.h"
21#include "llvm/CodeGen/SelectionDAG.h"
22#include "llvm/IR/Function.h"
23#include "llvm/Target/TargetLowering.h"
24#include <deque>
25#include <string>
26
27namespace llvm {
28  namespace MipsISD {
29    enum NodeType {
30      // Start the numbering from where ISD NodeType finishes.
31      FIRST_NUMBER = ISD::BUILTIN_OP_END,
32
33      // Jump and link (call)
34      JmpLink,
35
36      // Tail call
37      TailCall,
38
39      // Get the Higher 16 bits from a 32-bit immediate
40      // No relation with Mips Hi register
41      Hi,
42
43      // Get the Lower 16 bits from a 32-bit immediate
44      // No relation with Mips Lo register
45      Lo,
46
47      // Handle gp_rel (small data/bss sections) relocation.
48      GPRel,
49
50      // Thread Pointer
51      ThreadPointer,
52
53      // Floating Point Branch Conditional
54      FPBrcond,
55
56      // Floating Point Compare
57      FPCmp,
58
59      // Floating Point Conditional Moves
60      CMovFP_T,
61      CMovFP_F,
62
63      // FP-to-int truncation node.
64      TruncIntFP,
65
66      // Return
67      Ret,
68
69      EH_RETURN,
70
71      // Node used to extract integer from accumulator.
72      ExtractLOHI,
73
74      // Node used to insert integers to accumulator.
75      InsertLOHI,
76
77      // Mult nodes.
78      Mult,
79      Multu,
80
81      // MAdd/Sub nodes
82      MAdd,
83      MAddu,
84      MSub,
85      MSubu,
86
87      // DivRem(u)
88      DivRem,
89      DivRemU,
90      DivRem16,
91      DivRemU16,
92
93      BuildPairF64,
94      ExtractElementF64,
95
96      Wrapper,
97
98      DynAlloc,
99
100      Sync,
101
102      Ext,
103      Ins,
104
105      // EXTR.W instrinsic nodes.
106      EXTP,
107      EXTPDP,
108      EXTR_S_H,
109      EXTR_W,
110      EXTR_R_W,
111      EXTR_RS_W,
112      SHILO,
113      MTHLIP,
114
115      // DPA.W intrinsic nodes.
116      MULSAQ_S_W_PH,
117      MAQ_S_W_PHL,
118      MAQ_S_W_PHR,
119      MAQ_SA_W_PHL,
120      MAQ_SA_W_PHR,
121      DPAU_H_QBL,
122      DPAU_H_QBR,
123      DPSU_H_QBL,
124      DPSU_H_QBR,
125      DPAQ_S_W_PH,
126      DPSQ_S_W_PH,
127      DPAQ_SA_L_W,
128      DPSQ_SA_L_W,
129      DPA_W_PH,
130      DPS_W_PH,
131      DPAQX_S_W_PH,
132      DPAQX_SA_W_PH,
133      DPAX_W_PH,
134      DPSX_W_PH,
135      DPSQX_S_W_PH,
136      DPSQX_SA_W_PH,
137      MULSA_W_PH,
138
139      MULT,
140      MULTU,
141      MADD_DSP,
142      MADDU_DSP,
143      MSUB_DSP,
144      MSUBU_DSP,
145
146      // DSP shift nodes.
147      SHLL_DSP,
148      SHRA_DSP,
149      SHRL_DSP,
150
151      // DSP setcc and select_cc nodes.
152      SETCC_DSP,
153      SELECT_CC_DSP,
154
155      // Vector comparisons.
156      VALL_ZERO,
157      VANY_ZERO,
158      VALL_NONZERO,
159      VANY_NONZERO,
160
161      // Special case of BUILD_VECTOR where all elements are the same.
162      VSPLAT,
163      // Special case of VSPLAT where the result is v2i64, the operand is
164      // constant, and the operand fits in a signed 10-bits value.
165      VSPLATD,
166
167      // Load/Store Left/Right nodes.
168      LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
169      LWR,
170      SWL,
171      SWR,
172      LDL,
173      LDR,
174      SDL,
175      SDR
176    };
177  }
178
179  //===--------------------------------------------------------------------===//
180  // TargetLowering Implementation
181  //===--------------------------------------------------------------------===//
182  class MipsFunctionInfo;
183
184  class MipsTargetLowering : public TargetLowering  {
185  public:
186    explicit MipsTargetLowering(MipsTargetMachine &TM);
187
188    static const MipsTargetLowering *create(MipsTargetMachine &TM);
189
190    virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
191
192    virtual void LowerOperationWrapper(SDNode *N,
193                                       SmallVectorImpl<SDValue> &Results,
194                                       SelectionDAG &DAG) const;
195
196    /// LowerOperation - Provide custom lowering hooks for some operations.
197    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
198
199    /// ReplaceNodeResults - Replace the results of node with an illegal result
200    /// type with new values built out of custom code.
201    ///
202    virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
203                                    SelectionDAG &DAG) const;
204
205    /// getTargetNodeName - This method returns the name of a target specific
206    //  DAG node.
207    virtual const char *getTargetNodeName(unsigned Opcode) const;
208
209    /// getSetCCResultType - get the ISD::SETCC result ValueType
210    EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
211
212    virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
213
214    virtual MachineBasicBlock *
215    EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
216
217    struct LTStr {
218      bool operator()(const char *S1, const char *S2) const {
219        return strcmp(S1, S2) < 0;
220      }
221    };
222
223  protected:
224    SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
225
226    SDValue getAddrLocal(SDValue Op, SelectionDAG &DAG, bool HasMips64) const;
227
228    SDValue getAddrGlobal(SDValue Op, SelectionDAG &DAG, unsigned Flag) const;
229
230    SDValue getAddrGlobalLargeGOT(SDValue Op, SelectionDAG &DAG,
231                                  unsigned HiFlag, unsigned LoFlag) const;
232
233    /// This function fills Ops, which is the list of operands that will later
234    /// be used when a function call node is created. It also generates
235    /// copyToReg nodes to set up argument registers.
236    virtual void
237    getOpndList(SmallVectorImpl<SDValue> &Ops,
238                std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
239                bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
240                CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
241
242    /// ByValArgInfo - Byval argument information.
243    struct ByValArgInfo {
244      unsigned FirstIdx; // Index of the first register used.
245      unsigned NumRegs;  // Number of registers used for this argument.
246      unsigned Address;  // Offset of the stack area used to pass this argument.
247
248      ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
249    };
250
251    /// MipsCC - This class provides methods used to analyze formal and call
252    /// arguments and inquire about calling convention information.
253    class MipsCC {
254    public:
255      enum SpecialCallingConvType {
256        Mips16RetHelperConv, NoSpecialCallingConv
257      };
258
259      MipsCC(CallingConv::ID CallConv, bool IsO32, bool IsFP64, CCState &Info,
260             SpecialCallingConvType SpecialCallingConv = NoSpecialCallingConv);
261
262
263      void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
264                               bool IsVarArg, bool IsSoftFloat,
265                               const SDNode *CallNode,
266                               std::vector<ArgListEntry> &FuncArgs);
267      void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
268                                  bool IsSoftFloat,
269                                  Function::const_arg_iterator FuncArg);
270
271      void analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
272                             bool IsSoftFloat, const SDNode *CallNode,
273                             const Type *RetTy) const;
274
275      void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
276                         bool IsSoftFloat, const Type *RetTy) const;
277
278      const CCState &getCCInfo() const { return CCInfo; }
279
280      /// hasByValArg - Returns true if function has byval arguments.
281      bool hasByValArg() const { return !ByValArgs.empty(); }
282
283      /// regSize - Size (in number of bits) of integer registers.
284      unsigned regSize() const { return IsO32 ? 4 : 8; }
285
286      /// numIntArgRegs - Number of integer registers available for calls.
287      unsigned numIntArgRegs() const;
288
289      /// reservedArgArea - The size of the area the caller reserves for
290      /// register arguments. This is 16-byte if ABI is O32.
291      unsigned reservedArgArea() const;
292
293      /// Return pointer to array of integer argument registers.
294      const uint16_t *intArgRegs() const;
295
296      typedef SmallVectorImpl<ByValArgInfo>::const_iterator byval_iterator;
297      byval_iterator byval_begin() const { return ByValArgs.begin(); }
298      byval_iterator byval_end() const { return ByValArgs.end(); }
299
300    private:
301      void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
302                          CCValAssign::LocInfo LocInfo,
303                          ISD::ArgFlagsTy ArgFlags);
304
305      /// useRegsForByval - Returns true if the calling convention allows the
306      /// use of registers to pass byval arguments.
307      bool useRegsForByval() const { return CallConv != CallingConv::Fast; }
308
309      /// Return the function that analyzes fixed argument list functions.
310      llvm::CCAssignFn *fixedArgFn() const;
311
312      /// Return the function that analyzes variable argument list functions.
313      llvm::CCAssignFn *varArgFn() const;
314
315      const uint16_t *shadowRegs() const;
316
317      void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
318                        unsigned Align);
319
320      /// Return the type of the register which is used to pass an argument or
321      /// return a value. This function returns f64 if the argument is an i64
322      /// value which has been generated as a result of softening an f128 value.
323      /// Otherwise, it just returns VT.
324      MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode,
325                   bool IsSoftFloat) const;
326
327      template<typename Ty>
328      void analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat,
329                         const SDNode *CallNode, const Type *RetTy) const;
330
331      CCState &CCInfo;
332      CallingConv::ID CallConv;
333      bool IsO32, IsFP64;
334      SpecialCallingConvType SpecialCallingConv;
335      SmallVector<ByValArgInfo, 2> ByValArgs;
336    };
337  protected:
338    SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
339    SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
340
341    // Subtarget Info
342    const MipsSubtarget *Subtarget;
343
344    bool HasMips64, IsN64, IsO32;
345
346  private:
347
348    MipsCC::SpecialCallingConvType getSpecialCallingConv(SDValue Callee) const;
349    // Lower Operand helpers
350    SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
351                            CallingConv::ID CallConv, bool isVarArg,
352                            const SmallVectorImpl<ISD::InputArg> &Ins,
353                            SDLoc dl, SelectionDAG &DAG,
354                            SmallVectorImpl<SDValue> &InVals,
355                            const SDNode *CallNode, const Type *RetTy) const;
356
357    // Lower Operand specifics
358    SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
359    SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
360    SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
361    SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
362    SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
363    SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
364    SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
365    SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
366    SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
367    SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
368    SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
369    SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
370    SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
371    SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
372    SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
373    SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
374    SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
375    SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
376    SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
377                                 bool IsSRA) const;
378    SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
379    SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
380
381    /// isEligibleForTailCallOptimization - Check whether the call is eligible
382    /// for tail call optimization.
383    virtual bool
384    isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
385                                      unsigned NextStackOffset,
386                                      const MipsFunctionInfo& FI) const = 0;
387
388    /// copyByValArg - Copy argument registers which were used to pass a byval
389    /// argument to the stack. Create a stack frame object for the byval
390    /// argument.
391    void copyByValRegs(SDValue Chain, SDLoc DL,
392                       std::vector<SDValue> &OutChains, SelectionDAG &DAG,
393                       const ISD::ArgFlagsTy &Flags,
394                       SmallVectorImpl<SDValue> &InVals,
395                       const Argument *FuncArg,
396                       const MipsCC &CC, const ByValArgInfo &ByVal) const;
397
398    /// passByValArg - Pass a byval argument in registers or on stack.
399    void passByValArg(SDValue Chain, SDLoc DL,
400                      std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
401                      SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
402                      MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
403                      const MipsCC &CC, const ByValArgInfo &ByVal,
404                      const ISD::ArgFlagsTy &Flags, bool isLittle) const;
405
406    /// writeVarArgRegs - Write variable function arguments passed in registers
407    /// to the stack. Also create a stack frame object for the first variable
408    /// argument.
409    void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
410                         SDValue Chain, SDLoc DL, SelectionDAG &DAG) const;
411
412    virtual SDValue
413      LowerFormalArguments(SDValue Chain,
414                           CallingConv::ID CallConv, bool isVarArg,
415                           const SmallVectorImpl<ISD::InputArg> &Ins,
416                           SDLoc dl, SelectionDAG &DAG,
417                           SmallVectorImpl<SDValue> &InVals) const;
418
419    SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
420                           SDValue Arg, SDLoc DL, bool IsTailCall,
421                           SelectionDAG &DAG) const;
422
423    virtual SDValue
424      LowerCall(TargetLowering::CallLoweringInfo &CLI,
425                SmallVectorImpl<SDValue> &InVals) const;
426
427    virtual bool
428      CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
429                     bool isVarArg,
430                     const SmallVectorImpl<ISD::OutputArg> &Outs,
431                     LLVMContext &Context) const;
432
433    virtual SDValue
434      LowerReturn(SDValue Chain,
435                  CallingConv::ID CallConv, bool isVarArg,
436                  const SmallVectorImpl<ISD::OutputArg> &Outs,
437                  const SmallVectorImpl<SDValue> &OutVals,
438                  SDLoc dl, SelectionDAG &DAG) const;
439
440    // Inline asm support
441    ConstraintType getConstraintType(const std::string &Constraint) const;
442
443    /// Examine constraint string and operand type and determine a weight value.
444    /// The operand object must already have been set up with the operand type.
445    ConstraintWeight getSingleConstraintMatchWeight(
446      AsmOperandInfo &info, const char *constraint) const;
447
448    /// This function parses registers that appear in inline-asm constraints.
449    /// It returns pair (0, 0) on failure.
450    std::pair<unsigned, const TargetRegisterClass *>
451    parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const;
452
453    std::pair<unsigned, const TargetRegisterClass*>
454              getRegForInlineAsmConstraint(const std::string &Constraint,
455                                           MVT VT) const;
456
457    /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
458    /// vector.  If it is invalid, don't add anything to Ops. If hasMemory is
459    /// true it means one of the asm constraint of the inline asm instruction
460    /// being processed is 'm'.
461    virtual void LowerAsmOperandForConstraint(SDValue Op,
462                                              std::string &Constraint,
463                                              std::vector<SDValue> &Ops,
464                                              SelectionDAG &DAG) const;
465
466    virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
467
468    virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
469
470    virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
471                                    unsigned SrcAlign,
472                                    bool IsMemset, bool ZeroMemset,
473                                    bool MemcpyStrSrc,
474                                    MachineFunction &MF) const;
475
476    /// isFPImmLegal - Returns true if the target can instruction select the
477    /// specified FP immediate natively. If false, the legalizer will
478    /// materialize the FP immediate as a load from a constant pool.
479    virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
480
481    virtual unsigned getJumpTableEncoding() const;
482
483    MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
484                    unsigned Size, unsigned BinOpcode, bool Nand = false) const;
485    MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
486                    MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
487                    bool Nand = false) const;
488    MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
489                                  MachineBasicBlock *BB, unsigned Size) const;
490    MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
491                                  MachineBasicBlock *BB, unsigned Size) const;
492  };
493
494  /// Create MipsTargetLowering objects.
495  const MipsTargetLowering *createMips16TargetLowering(MipsTargetMachine &TM);
496  const MipsTargetLowering *createMipsSETargetLowering(MipsTargetMachine &TM);
497}
498
499#endif // MipsISELLOWERING_H
500