MipsISelLowering.h revision db40edeb11f4f97c8de5428a84346834deaa2a47
1//===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that Mips uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef MipsISELLOWERING_H 16#define MipsISELLOWERING_H 17 18#include "Mips.h" 19#include "MipsSubtarget.h" 20#include "llvm/CodeGen/CallingConvLower.h" 21#include "llvm/CodeGen/SelectionDAG.h" 22#include "llvm/Target/TargetLowering.h" 23 24namespace llvm { 25 namespace MipsISD { 26 enum NodeType { 27 // Start the numbering from where ISD NodeType finishes. 28 FIRST_NUMBER = ISD::BUILTIN_OP_END, 29 30 // Jump and link (call) 31 JmpLink, 32 33 // Tail call 34 TailCall, 35 36 // Get the Higher 16 bits from a 32-bit immediate 37 // No relation with Mips Hi register 38 Hi, 39 40 // Get the Lower 16 bits from a 32-bit immediate 41 // No relation with Mips Lo register 42 Lo, 43 44 // Handle gp_rel (small data/bss sections) relocation. 45 GPRel, 46 47 // Thread Pointer 48 ThreadPointer, 49 50 // Floating Point Branch Conditional 51 FPBrcond, 52 53 // Floating Point Compare 54 FPCmp, 55 56 // Floating Point Conditional Moves 57 CMovFP_T, 58 CMovFP_F, 59 60 // Floating Point Rounding 61 FPRound, 62 63 // Return 64 Ret, 65 66 // MAdd/Sub nodes 67 MAdd, 68 MAddu, 69 MSub, 70 MSubu, 71 72 // DivRem(u) 73 DivRem, 74 DivRemU, 75 76 BuildPairF64, 77 ExtractElementF64, 78 79 Wrapper, 80 81 DynAlloc, 82 83 Sync, 84 85 Ext, 86 Ins, 87 88 // EXTR.W instrinsic nodes. 89 EXTP, 90 EXTPDP, 91 EXTR_S_H, 92 EXTR_W, 93 EXTR_R_W, 94 EXTR_RS_W, 95 SHILO, 96 MTHLIP, 97 98 // DPA.W intrinsic nodes. 99 MULSAQ_S_W_PH, 100 MAQ_S_W_PHL, 101 MAQ_S_W_PHR, 102 MAQ_SA_W_PHL, 103 MAQ_SA_W_PHR, 104 DPAU_H_QBL, 105 DPAU_H_QBR, 106 DPSU_H_QBL, 107 DPSU_H_QBR, 108 DPAQ_S_W_PH, 109 DPSQ_S_W_PH, 110 DPAQ_SA_L_W, 111 DPSQ_SA_L_W, 112 DPA_W_PH, 113 DPS_W_PH, 114 DPAQX_S_W_PH, 115 DPAQX_SA_W_PH, 116 DPAX_W_PH, 117 DPSX_W_PH, 118 DPSQX_S_W_PH, 119 DPSQX_SA_W_PH, 120 MULSA_W_PH, 121 122 MULT, 123 MULTU, 124 MADD_DSP, 125 MADDU_DSP, 126 MSUB_DSP, 127 MSUBU_DSP, 128 129 // Load/Store Left/Right nodes. 130 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE, 131 LWR, 132 SWL, 133 SWR, 134 LDL, 135 LDR, 136 SDL, 137 SDR 138 }; 139 } 140 141 //===--------------------------------------------------------------------===// 142 // TargetLowering Implementation 143 //===--------------------------------------------------------------------===// 144 145 class MipsTargetLowering : public TargetLowering { 146 public: 147 explicit MipsTargetLowering(MipsTargetMachine &TM); 148 149 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; } 150 151 virtual bool allowsUnalignedMemoryAccesses (EVT VT) const; 152 153 virtual void LowerOperationWrapper(SDNode *N, 154 SmallVectorImpl<SDValue> &Results, 155 SelectionDAG &DAG) const; 156 157 /// LowerOperation - Provide custom lowering hooks for some operations. 158 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 159 160 /// ReplaceNodeResults - Replace the results of node with an illegal result 161 /// type with new values built out of custom code. 162 /// 163 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 164 SelectionDAG &DAG) const; 165 166 /// getTargetNodeName - This method returns the name of a target specific 167 // DAG node. 168 virtual const char *getTargetNodeName(unsigned Opcode) const; 169 170 /// getSetCCResultType - get the ISD::SETCC result ValueType 171 EVT getSetCCResultType(EVT VT) const; 172 173 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 174 private: 175 176 /// ByValArgInfo - Byval argument information. 177 struct ByValArgInfo { 178 unsigned FirstIdx; // Index of the first register used. 179 unsigned NumRegs; // Number of registers used for this argument. 180 unsigned Address; // Offset of the stack area used to pass this argument. 181 182 ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {} 183 }; 184 185 /// MipsCC - This class provides methods used to analyze formal and call 186 /// arguments and inquire about calling convention information. 187 class MipsCC { 188 public: 189 MipsCC(CallingConv::ID CallConv, bool IsVarArg, bool IsO32, 190 CCState &Info); 191 192 void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs); 193 void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins); 194 void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT, 195 CCValAssign::LocInfo LocInfo, 196 ISD::ArgFlagsTy ArgFlags); 197 198 const CCState &getCCInfo() const { return CCInfo; } 199 200 /// hasByValArg - Returns true if function has byval arguments. 201 bool hasByValArg() const { return !ByValArgs.empty(); } 202 203 /// useRegsForByval - Returns true if the calling convention allows the 204 /// use of registers to pass byval arguments. 205 bool useRegsForByval() const { return UseRegsForByval; } 206 207 /// regSize - Size (in number of bits) of integer registers. 208 unsigned regSize() const { return RegSize; } 209 210 /// numIntArgRegs - Number of integer registers available for calls. 211 unsigned numIntArgRegs() const { return NumIntArgRegs; } 212 213 /// reservedArgArea - The size of the area the caller reserves for 214 /// register arguments. This is 16-byte if ABI is O32. 215 unsigned reservedArgArea() const { return ReservedArgArea; } 216 217 /// intArgRegs - Pointer to array of integer registers. 218 const uint16_t *intArgRegs() const { return IntArgRegs; } 219 220 typedef SmallVector<ByValArgInfo, 2>::const_iterator byval_iterator; 221 byval_iterator byval_begin() const { return ByValArgs.begin(); } 222 byval_iterator byval_end() const { return ByValArgs.end(); } 223 224 private: 225 void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize, 226 unsigned Align); 227 228 CCState &CCInfo; 229 bool UseRegsForByval; 230 unsigned RegSize; 231 unsigned NumIntArgRegs; 232 unsigned ReservedArgArea; 233 const uint16_t *IntArgRegs, *ShadowRegs; 234 SmallVector<ByValArgInfo, 2> ByValArgs; 235 llvm::CCAssignFn *FixedFn, *VarFn; 236 }; 237 238 // Subtarget Info 239 const MipsSubtarget *Subtarget; 240 241 bool HasMips64, IsN64, IsO32; 242 243 // Lower Operand helpers 244 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 245 CallingConv::ID CallConv, bool isVarArg, 246 const SmallVectorImpl<ISD::InputArg> &Ins, 247 DebugLoc dl, SelectionDAG &DAG, 248 SmallVectorImpl<SDValue> &InVals) const; 249 250 // Lower Operand specifics 251 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 252 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 253 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 254 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 255 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 256 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 257 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 258 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 259 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 260 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; 261 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 262 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const; 263 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 264 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 265 SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const; 266 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const; 267 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const; 268 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG& DAG, 269 bool IsSRA) const; 270 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 271 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 272 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 273 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 274 275 /// IsEligibleForTailCallOptimization - Check whether the call is eligible 276 /// for tail call optimization. 277 bool IsEligibleForTailCallOptimization(CallingConv::ID CalleeCC, 278 unsigned NextStackOffset) const; 279 280 /// copyByValArg - Copy argument registers which were used to pass a byval 281 /// argument to the stack. Create a stack frame object for the byval 282 /// argument. 283 void copyByValRegs(SDValue Chain, DebugLoc DL, 284 std::vector<SDValue> &OutChains, SelectionDAG &DAG, 285 const ISD::ArgFlagsTy &Flags, 286 SmallVectorImpl<SDValue> &InVals, 287 const Argument *FuncArg, 288 const MipsCC &CC, const ByValArgInfo &ByVal) const; 289 290 /// passByValArg - Pass a byval argument in registers or on stack. 291 void passByValArg(SDValue Chain, DebugLoc DL, 292 SmallVector<std::pair<unsigned, SDValue>, 16> &RegsToPass, 293 SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr, 294 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, 295 const MipsCC &CC, const ByValArgInfo &ByVal, 296 const ISD::ArgFlagsTy &Flags, bool isLittle) const; 297 298 virtual SDValue 299 LowerFormalArguments(SDValue Chain, 300 CallingConv::ID CallConv, bool isVarArg, 301 const SmallVectorImpl<ISD::InputArg> &Ins, 302 DebugLoc dl, SelectionDAG &DAG, 303 SmallVectorImpl<SDValue> &InVals) const; 304 305 virtual SDValue 306 LowerCall(TargetLowering::CallLoweringInfo &CLI, 307 SmallVectorImpl<SDValue> &InVals) const; 308 309 virtual bool 310 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 311 bool isVarArg, 312 const SmallVectorImpl<ISD::OutputArg> &Outs, 313 LLVMContext &Context) const; 314 315 virtual SDValue 316 LowerReturn(SDValue Chain, 317 CallingConv::ID CallConv, bool isVarArg, 318 const SmallVectorImpl<ISD::OutputArg> &Outs, 319 const SmallVectorImpl<SDValue> &OutVals, 320 DebugLoc dl, SelectionDAG &DAG) const; 321 322 virtual MachineBasicBlock * 323 EmitInstrWithCustomInserter(MachineInstr *MI, 324 MachineBasicBlock *MBB) const; 325 326 // Inline asm support 327 ConstraintType getConstraintType(const std::string &Constraint) const; 328 329 /// Examine constraint string and operand type and determine a weight value. 330 /// The operand object must already have been set up with the operand type. 331 ConstraintWeight getSingleConstraintMatchWeight( 332 AsmOperandInfo &info, const char *constraint) const; 333 334 std::pair<unsigned, const TargetRegisterClass*> 335 getRegForInlineAsmConstraint(const std::string &Constraint, 336 EVT VT) const; 337 338 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 339 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 340 /// true it means one of the asm constraint of the inline asm instruction 341 /// being processed is 'm'. 342 virtual void LowerAsmOperandForConstraint(SDValue Op, 343 std::string &Constraint, 344 std::vector<SDValue> &Ops, 345 SelectionDAG &DAG) const; 346 347 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 348 349 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 350 unsigned SrcAlign, bool IsZeroVal, 351 bool MemcpyStrSrc, 352 MachineFunction &MF) const; 353 354 /// isFPImmLegal - Returns true if the target can instruction select the 355 /// specified FP immediate natively. If false, the legalizer will 356 /// materialize the FP immediate as a load from a constant pool. 357 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; 358 359 virtual unsigned getJumpTableEncoding() const; 360 361 MachineBasicBlock *EmitBPOSGE32(MachineInstr *MI, 362 MachineBasicBlock *BB) const; 363 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 364 unsigned Size, unsigned BinOpcode, bool Nand = false) const; 365 MachineBasicBlock *EmitAtomicBinaryPartword(MachineInstr *MI, 366 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode, 367 bool Nand = false) const; 368 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI, 369 MachineBasicBlock *BB, unsigned Size) const; 370 MachineBasicBlock *EmitAtomicCmpSwapPartword(MachineInstr *MI, 371 MachineBasicBlock *BB, unsigned Size) const; 372 }; 373} 374 375#endif // MipsISELLOWERING_H 376