MipsISelLowering.h revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f 
1//===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that Mips uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef MipsISELLOWERING_H
16#define MipsISELLOWERING_H
17
18#include "MCTargetDesc/MipsBaseInfo.h"
19#include "Mips.h"
20#include "MipsSubtarget.h"
21#include "llvm/CodeGen/CallingConvLower.h"
22#include "llvm/CodeGen/SelectionDAG.h"
23#include "llvm/IR/Function.h"
24#include "llvm/Target/TargetLowering.h"
25#include <deque>
26#include <string>
27
28namespace llvm {
29  namespace MipsISD {
30    enum NodeType {
31      // Start the numbering from where ISD NodeType finishes.
32      FIRST_NUMBER = ISD::BUILTIN_OP_END,
33
34      // Jump and link (call)
35      JmpLink,
36
37      // Tail call
38      TailCall,
39
40      // Get the Higher 16 bits from a 32-bit immediate
41      // No relation with Mips Hi register
42      Hi,
43
44      // Get the Lower 16 bits from a 32-bit immediate
45      // No relation with Mips Lo register
46      Lo,
47
48      // Handle gp_rel (small data/bss sections) relocation.
49      GPRel,
50
51      // Thread Pointer
52      ThreadPointer,
53
54      // Floating Point Branch Conditional
55      FPBrcond,
56
57      // Floating Point Compare
58      FPCmp,
59
60      // Floating Point Conditional Moves
61      CMovFP_T,
62      CMovFP_F,
63
64      // FP-to-int truncation node.
65      TruncIntFP,
66
67      // Return
68      Ret,
69
70      EH_RETURN,
71
72      // Node used to extract integer from accumulator.
73      MFHI,
74      MFLO,
75
76      // Node used to insert integers to accumulator.
77      MTLOHI,
78
79      // Mult nodes.
80      Mult,
81      Multu,
82
83      // MAdd/Sub nodes
84      MAdd,
85      MAddu,
86      MSub,
87      MSubu,
88
89      // DivRem(u)
90      DivRem,
91      DivRemU,
92      DivRem16,
93      DivRemU16,
94
95      BuildPairF64,
96      ExtractElementF64,
97
98      Wrapper,
99
100      DynAlloc,
101
102      Sync,
103
104      Ext,
105      Ins,
106
107      // EXTR.W instrinsic nodes.
108      EXTP,
109      EXTPDP,
110      EXTR_S_H,
111      EXTR_W,
112      EXTR_R_W,
113      EXTR_RS_W,
114      SHILO,
115      MTHLIP,
116
117      // DPA.W intrinsic nodes.
118      MULSAQ_S_W_PH,
119      MAQ_S_W_PHL,
120      MAQ_S_W_PHR,
121      MAQ_SA_W_PHL,
122      MAQ_SA_W_PHR,
123      DPAU_H_QBL,
124      DPAU_H_QBR,
125      DPSU_H_QBL,
126      DPSU_H_QBR,
127      DPAQ_S_W_PH,
128      DPSQ_S_W_PH,
129      DPAQ_SA_L_W,
130      DPSQ_SA_L_W,
131      DPA_W_PH,
132      DPS_W_PH,
133      DPAQX_S_W_PH,
134      DPAQX_SA_W_PH,
135      DPAX_W_PH,
136      DPSX_W_PH,
137      DPSQX_S_W_PH,
138      DPSQX_SA_W_PH,
139      MULSA_W_PH,
140
141      MULT,
142      MULTU,
143      MADD_DSP,
144      MADDU_DSP,
145      MSUB_DSP,
146      MSUBU_DSP,
147
148      // DSP shift nodes.
149      SHLL_DSP,
150      SHRA_DSP,
151      SHRL_DSP,
152
153      // DSP setcc and select_cc nodes.
154      SETCC_DSP,
155      SELECT_CC_DSP,
156
157      // Vector comparisons.
158      // These take a vector and return a boolean.
159      VALL_ZERO,
160      VANY_ZERO,
161      VALL_NONZERO,
162      VANY_NONZERO,
163
164      // These take a vector and return a vector bitmask.
165      VCEQ,
166      VCLE_S,
167      VCLE_U,
168      VCLT_S,
169      VCLT_U,
170
171      // Element-wise vector max/min.
172      VSMAX,
173      VSMIN,
174      VUMAX,
175      VUMIN,
176
177      // Vector Shuffle with mask as an operand
178      VSHF,  // Generic shuffle
179      SHF,   // 4-element set shuffle.
180      ILVEV, // Interleave even elements
181      ILVOD, // Interleave odd elements
182      ILVL,  // Interleave left elements
183      ILVR,  // Interleave right elements
184      PCKEV, // Pack even elements
185      PCKOD, // Pack odd elements
186
187      // Vector Lane Copy
188      INSVE, // Copy element from one vector to another
189
190      // Combined (XOR (OR $a, $b), -1)
191      VNOR,
192
193      // Extended vector element extraction
194      VEXTRACT_SEXT_ELT,
195      VEXTRACT_ZEXT_ELT,
196
197      // Load/Store Left/Right nodes.
198      LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
199      LWR,
200      SWL,
201      SWR,
202      LDL,
203      LDR,
204      SDL,
205      SDR
206    };
207  }
208
209  //===--------------------------------------------------------------------===//
210  // TargetLowering Implementation
211  //===--------------------------------------------------------------------===//
212  class MipsFunctionInfo;
213
214  class MipsTargetLowering : public TargetLowering  {
215    bool isMicroMips;
216  public:
217    explicit MipsTargetLowering(MipsTargetMachine &TM);
218
219    static const MipsTargetLowering *create(MipsTargetMachine &TM);
220
221    /// createFastISel - This method returns a target specific FastISel object,
222    /// or null if the target does not support "fast" ISel.
223    FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
224                             const TargetLibraryInfo *libInfo) const override;
225
226    MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; }
227
228    void LowerOperationWrapper(SDNode *N,
229                               SmallVectorImpl<SDValue> &Results,
230                               SelectionDAG &DAG) const override;
231
232    /// LowerOperation - Provide custom lowering hooks for some operations.
233    SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
234
235    /// ReplaceNodeResults - Replace the results of node with an illegal result
236    /// type with new values built out of custom code.
237    ///
238    void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
239                            SelectionDAG &DAG) const override;
240
241    /// getTargetNodeName - This method returns the name of a target specific
242    //  DAG node.
243    const char *getTargetNodeName(unsigned Opcode) const override;
244
245    /// getSetCCResultType - get the ISD::SETCC result ValueType
246    EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
247
248    SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
249
250    MachineBasicBlock *
251    EmitInstrWithCustomInserter(MachineInstr *MI,
252                                MachineBasicBlock *MBB) const override;
253
254    struct LTStr {
255      bool operator()(const char *S1, const char *S2) const {
256        return strcmp(S1, S2) < 0;
257      }
258    };
259
260  protected:
261    SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
262
263    // This method creates the following nodes, which are necessary for
264    // computing a local symbol's address:
265    //
266    // (add (load (wrapper $gp, %got(sym)), %lo(sym))
267    template <class NodeTy>
268    SDValue getAddrLocal(NodeTy *N, EVT Ty, SelectionDAG &DAG,
269                         bool IsN32OrN64) const {
270      SDLoc DL(N);
271      unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
272      SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
273                                getTargetNode(N, Ty, DAG, GOTFlag));
274      SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
275                                 MachinePointerInfo::getGOT(), false, false,
276                                 false, 0);
277      unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
278      SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
279                               getTargetNode(N, Ty, DAG, LoFlag));
280      return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
281    }
282
283    // This method creates the following nodes, which are necessary for
284    // computing a global symbol's address:
285    //
286    // (load (wrapper $gp, %got(sym)))
287    template<class NodeTy>
288    SDValue getAddrGlobal(NodeTy *N, EVT Ty, SelectionDAG &DAG,
289                          unsigned Flag, SDValue Chain,
290                          const MachinePointerInfo &PtrInfo) const {
291      SDLoc DL(N);
292      SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
293                                getTargetNode(N, Ty, DAG, Flag));
294      return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo, false, false, false, 0);
295    }
296
297    // This method creates the following nodes, which are necessary for
298    // computing a global symbol's address in large-GOT mode:
299    //
300    // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
301    template<class NodeTy>
302    SDValue getAddrGlobalLargeGOT(NodeTy *N, EVT Ty, SelectionDAG &DAG,
303                                  unsigned HiFlag, unsigned LoFlag,
304                                  SDValue Chain,
305                                  const MachinePointerInfo &PtrInfo) const {
306      SDLoc DL(N);
307      SDValue Hi = DAG.getNode(MipsISD::Hi, DL, Ty,
308                               getTargetNode(N, Ty, DAG, HiFlag));
309      Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
310      SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
311                                    getTargetNode(N, Ty, DAG, LoFlag));
312      return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo, false, false, false,
313                         0);
314    }
315
316    // This method creates the following nodes, which are necessary for
317    // computing a symbol's address in non-PIC mode:
318    //
319    // (add %hi(sym), %lo(sym))
320    template<class NodeTy>
321    SDValue getAddrNonPIC(NodeTy *N, EVT Ty, SelectionDAG &DAG) const {
322      SDLoc DL(N);
323      SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
324      SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
325      return DAG.getNode(ISD::ADD, DL, Ty,
326                         DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
327                         DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
328    }
329
330    /// This function fills Ops, which is the list of operands that will later
331    /// be used when a function call node is created. It also generates
332    /// copyToReg nodes to set up argument registers.
333    virtual void
334    getOpndList(SmallVectorImpl<SDValue> &Ops,
335                std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
336                bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
337                CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
338
339    /// ByValArgInfo - Byval argument information.
340    struct ByValArgInfo {
341      unsigned FirstIdx; // Index of the first register used.
342      unsigned NumRegs;  // Number of registers used for this argument.
343      unsigned Address;  // Offset of the stack area used to pass this argument.
344
345      ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
346    };
347
348    /// MipsCC - This class provides methods used to analyze formal and call
349    /// arguments and inquire about calling convention information.
350    class MipsCC {
351    public:
352      enum SpecialCallingConvType {
353        Mips16RetHelperConv, NoSpecialCallingConv
354      };
355
356      MipsCC(CallingConv::ID CallConv, bool IsO32, bool IsFP64, CCState &Info,
357             SpecialCallingConvType SpecialCallingConv = NoSpecialCallingConv);
358
359
360      void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
361                               bool IsVarArg, bool IsSoftFloat,
362                               const SDNode *CallNode,
363                               std::vector<ArgListEntry> &FuncArgs);
364      void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
365                                  bool IsSoftFloat,
366                                  Function::const_arg_iterator FuncArg);
367
368      void analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
369                             bool IsSoftFloat, const SDNode *CallNode,
370                             const Type *RetTy) const;
371
372      void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
373                         bool IsSoftFloat, const Type *RetTy) const;
374
375      const CCState &getCCInfo() const { return CCInfo; }
376
377      /// hasByValArg - Returns true if function has byval arguments.
378      bool hasByValArg() const { return !ByValArgs.empty(); }
379
380      /// regSize - Size (in number of bits) of integer registers.
381      unsigned regSize() const { return IsO32 ? 4 : 8; }
382
383      /// numIntArgRegs - Number of integer registers available for calls.
384      unsigned numIntArgRegs() const;
385
386      /// reservedArgArea - The size of the area the caller reserves for
387      /// register arguments. This is 16-byte if ABI is O32.
388      unsigned reservedArgArea() const;
389
390      /// Return pointer to array of integer argument registers.
391      const MCPhysReg *intArgRegs() const;
392
393      typedef SmallVectorImpl<ByValArgInfo>::const_iterator byval_iterator;
394      byval_iterator byval_begin() const { return ByValArgs.begin(); }
395      byval_iterator byval_end() const { return ByValArgs.end(); }
396
397    private:
398      void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
399                          CCValAssign::LocInfo LocInfo,
400                          ISD::ArgFlagsTy ArgFlags);
401
402      /// useRegsForByval - Returns true if the calling convention allows the
403      /// use of registers to pass byval arguments.
404      bool useRegsForByval() const { return CallConv != CallingConv::Fast; }
405
406      /// Return the function that analyzes fixed argument list functions.
407      llvm::CCAssignFn *fixedArgFn() const;
408
409      /// Return the function that analyzes variable argument list functions.
410      llvm::CCAssignFn *varArgFn() const;
411
412      const MCPhysReg *shadowRegs() const;
413
414      void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
415                        unsigned Align);
416
417      /// Return the type of the register which is used to pass an argument or
418      /// return a value. This function returns f64 if the argument is an i64
419      /// value which has been generated as a result of softening an f128 value.
420      /// Otherwise, it just returns VT.
421      MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode,
422                   bool IsSoftFloat) const;
423
424      template<typename Ty>
425      void analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat,
426                         const SDNode *CallNode, const Type *RetTy) const;
427
428      CCState &CCInfo;
429      CallingConv::ID CallConv;
430      bool IsO32, IsFP64;
431      SpecialCallingConvType SpecialCallingConv;
432      SmallVector<ByValArgInfo, 2> ByValArgs;
433    };
434  protected:
435    SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
436    SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
437
438    // Subtarget Info
439    const MipsSubtarget *Subtarget;
440
441    bool hasMips64() const { return Subtarget->hasMips64(); }
442    bool isGP64bit() const { return Subtarget->isGP64bit(); }
443    bool isO32() const { return Subtarget->isABI_O32(); }
444    bool isN32() const { return Subtarget->isABI_N32(); }
445    bool isN64() const { return Subtarget->isABI_N64(); }
446
447  private:
448    // Create a TargetGlobalAddress node.
449    SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
450                          unsigned Flag) const;
451
452    // Create a TargetExternalSymbol node.
453    SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG,
454                          unsigned Flag) const;
455
456    // Create a TargetBlockAddress node.
457    SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
458                          unsigned Flag) const;
459
460    // Create a TargetJumpTable node.
461    SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
462                          unsigned Flag) const;
463
464    // Create a TargetConstantPool node.
465    SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
466                          unsigned Flag) const;
467
468    MipsCC::SpecialCallingConvType getSpecialCallingConv(SDValue Callee) const;
469    // Lower Operand helpers
470    SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
471                            CallingConv::ID CallConv, bool isVarArg,
472                            const SmallVectorImpl<ISD::InputArg> &Ins,
473                            SDLoc dl, SelectionDAG &DAG,
474                            SmallVectorImpl<SDValue> &InVals,
475                            const SDNode *CallNode, const Type *RetTy) const;
476
477    // Lower Operand specifics
478    SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
479    SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
480    SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
481    SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
482    SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
483    SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
484    SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
485    SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
486    SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
487    SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
488    SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
489    SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
490    SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
491    SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
492    SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
493    SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
494    SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
495    SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
496    SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
497                                 bool IsSRA) const;
498    SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
499    SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
500
501    /// isEligibleForTailCallOptimization - Check whether the call is eligible
502    /// for tail call optimization.
503    virtual bool
504    isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
505                                      unsigned NextStackOffset,
506                                      const MipsFunctionInfo& FI) const = 0;
507
508    /// copyByValArg - Copy argument registers which were used to pass a byval
509    /// argument to the stack. Create a stack frame object for the byval
510    /// argument.
511    void copyByValRegs(SDValue Chain, SDLoc DL,
512                       std::vector<SDValue> &OutChains, SelectionDAG &DAG,
513                       const ISD::ArgFlagsTy &Flags,
514                       SmallVectorImpl<SDValue> &InVals,
515                       const Argument *FuncArg,
516                       const MipsCC &CC, const ByValArgInfo &ByVal) const;
517
518    /// passByValArg - Pass a byval argument in registers or on stack.
519    void passByValArg(SDValue Chain, SDLoc DL,
520                      std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
521                      SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
522                      MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
523                      const MipsCC &CC, const ByValArgInfo &ByVal,
524                      const ISD::ArgFlagsTy &Flags, bool isLittle) const;
525
526    /// writeVarArgRegs - Write variable function arguments passed in registers
527    /// to the stack. Also create a stack frame object for the first variable
528    /// argument.
529    void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
530                         SDValue Chain, SDLoc DL, SelectionDAG &DAG) const;
531
532    SDValue
533      LowerFormalArguments(SDValue Chain,
534                           CallingConv::ID CallConv, bool isVarArg,
535                           const SmallVectorImpl<ISD::InputArg> &Ins,
536                           SDLoc dl, SelectionDAG &DAG,
537                           SmallVectorImpl<SDValue> &InVals) const override;
538
539    SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
540                           SDValue Arg, SDLoc DL, bool IsTailCall,
541                           SelectionDAG &DAG) const;
542
543    SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
544                      SmallVectorImpl<SDValue> &InVals) const override;
545
546    bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
547                        bool isVarArg,
548                        const SmallVectorImpl<ISD::OutputArg> &Outs,
549                        LLVMContext &Context) const override;
550
551    SDValue LowerReturn(SDValue Chain,
552                        CallingConv::ID CallConv, bool isVarArg,
553                        const SmallVectorImpl<ISD::OutputArg> &Outs,
554                        const SmallVectorImpl<SDValue> &OutVals,
555                        SDLoc dl, SelectionDAG &DAG) const override;
556
557    // Inline asm support
558    ConstraintType
559      getConstraintType(const std::string &Constraint) const override;
560
561    /// Examine constraint string and operand type and determine a weight value.
562    /// The operand object must already have been set up with the operand type.
563    ConstraintWeight getSingleConstraintMatchWeight(
564      AsmOperandInfo &info, const char *constraint) const override;
565
566    /// This function parses registers that appear in inline-asm constraints.
567    /// It returns pair (0, 0) on failure.
568    std::pair<unsigned, const TargetRegisterClass *>
569    parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const;
570
571    std::pair<unsigned, const TargetRegisterClass*>
572              getRegForInlineAsmConstraint(const std::string &Constraint,
573                                           MVT VT) const override;
574
575    /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
576    /// vector.  If it is invalid, don't add anything to Ops. If hasMemory is
577    /// true it means one of the asm constraint of the inline asm instruction
578    /// being processed is 'm'.
579    void LowerAsmOperandForConstraint(SDValue Op,
580                                      std::string &Constraint,
581                                      std::vector<SDValue> &Ops,
582                                      SelectionDAG &DAG) const override;
583
584    bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
585
586    bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
587
588    EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
589                            unsigned SrcAlign,
590                            bool IsMemset, bool ZeroMemset,
591                            bool MemcpyStrSrc,
592                            MachineFunction &MF) const override;
593
594    /// isFPImmLegal - Returns true if the target can instruction select the
595    /// specified FP immediate natively. If false, the legalizer will
596    /// materialize the FP immediate as a load from a constant pool.
597    bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
598
599    unsigned getJumpTableEncoding() const override;
600
601    MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
602                    unsigned Size, unsigned BinOpcode, bool Nand = false) const;
603    MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
604                    MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
605                    bool Nand = false) const;
606    MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
607                                  MachineBasicBlock *BB, unsigned Size) const;
608    MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
609                                  MachineBasicBlock *BB, unsigned Size) const;
610  };
611
612  /// Create MipsTargetLowering objects.
613  const MipsTargetLowering *createMips16TargetLowering(MipsTargetMachine &TM);
614  const MipsTargetLowering *createMipsSETargetLowering(MipsTargetMachine &TM);
615
616  namespace Mips {
617    FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
618                             const TargetLibraryInfo *libInfo);
619  }
620}
621
622#endif // MipsISELLOWERING_H
623