MipsISelLowering.h revision f635ef401786c84df32090251a8cf45981ecca33
1//===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that Mips uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef MipsISELLOWERING_H 16#define MipsISELLOWERING_H 17 18#include "Mips.h" 19#include "MipsSubtarget.h" 20#include "llvm/CodeGen/CallingConvLower.h" 21#include "llvm/CodeGen/SelectionDAG.h" 22#include "llvm/IR/Function.h" 23#include "llvm/Target/TargetLowering.h" 24#include <deque> 25#include <string> 26 27namespace llvm { 28 namespace MipsISD { 29 enum NodeType { 30 // Start the numbering from where ISD NodeType finishes. 31 FIRST_NUMBER = ISD::BUILTIN_OP_END, 32 33 // Jump and link (call) 34 JmpLink, 35 36 // Tail call 37 TailCall, 38 39 // Get the Higher 16 bits from a 32-bit immediate 40 // No relation with Mips Hi register 41 Hi, 42 43 // Get the Lower 16 bits from a 32-bit immediate 44 // No relation with Mips Lo register 45 Lo, 46 47 // Handle gp_rel (small data/bss sections) relocation. 48 GPRel, 49 50 // Thread Pointer 51 ThreadPointer, 52 53 // Floating Point Branch Conditional 54 FPBrcond, 55 56 // Floating Point Compare 57 FPCmp, 58 59 // Floating Point Conditional Moves 60 CMovFP_T, 61 CMovFP_F, 62 63 // Floating Point Rounding 64 FPRound, 65 66 // Return 67 Ret, 68 69 EH_RETURN, 70 71 // MAdd/Sub nodes 72 MAdd, 73 MAddu, 74 MSub, 75 MSubu, 76 77 // DivRem(u) 78 DivRem, 79 DivRemU, 80 81 BuildPairF64, 82 ExtractElementF64, 83 84 Wrapper, 85 86 DynAlloc, 87 88 Sync, 89 90 Ext, 91 Ins, 92 93 // EXTR.W instrinsic nodes. 94 EXTP, 95 EXTPDP, 96 EXTR_S_H, 97 EXTR_W, 98 EXTR_R_W, 99 EXTR_RS_W, 100 SHILO, 101 MTHLIP, 102 103 // DPA.W intrinsic nodes. 104 MULSAQ_S_W_PH, 105 MAQ_S_W_PHL, 106 MAQ_S_W_PHR, 107 MAQ_SA_W_PHL, 108 MAQ_SA_W_PHR, 109 DPAU_H_QBL, 110 DPAU_H_QBR, 111 DPSU_H_QBL, 112 DPSU_H_QBR, 113 DPAQ_S_W_PH, 114 DPSQ_S_W_PH, 115 DPAQ_SA_L_W, 116 DPSQ_SA_L_W, 117 DPA_W_PH, 118 DPS_W_PH, 119 DPAQX_S_W_PH, 120 DPAQX_SA_W_PH, 121 DPAX_W_PH, 122 DPSX_W_PH, 123 DPSQX_S_W_PH, 124 DPSQX_SA_W_PH, 125 MULSA_W_PH, 126 127 MULT, 128 MULTU, 129 MADD_DSP, 130 MADDU_DSP, 131 MSUB_DSP, 132 MSUBU_DSP, 133 134 // Load/Store Left/Right nodes. 135 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE, 136 LWR, 137 SWL, 138 SWR, 139 LDL, 140 LDR, 141 SDL, 142 SDR 143 }; 144 } 145 146 //===--------------------------------------------------------------------===// 147 // TargetLowering Implementation 148 //===--------------------------------------------------------------------===// 149 class MipsFunctionInfo; 150 151 class MipsTargetLowering : public TargetLowering { 152 public: 153 explicit MipsTargetLowering(MipsTargetMachine &TM); 154 155 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; } 156 157 virtual bool allowsUnalignedMemoryAccesses (EVT VT, bool *Fast) const; 158 159 virtual void LowerOperationWrapper(SDNode *N, 160 SmallVectorImpl<SDValue> &Results, 161 SelectionDAG &DAG) const; 162 163 /// LowerOperation - Provide custom lowering hooks for some operations. 164 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 165 166 /// ReplaceNodeResults - Replace the results of node with an illegal result 167 /// type with new values built out of custom code. 168 /// 169 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 170 SelectionDAG &DAG) const; 171 172 /// getTargetNodeName - This method returns the name of a target specific 173 // DAG node. 174 virtual const char *getTargetNodeName(unsigned Opcode) const; 175 176 /// getSetCCResultType - get the ISD::SETCC result ValueType 177 EVT getSetCCResultType(EVT VT) const; 178 179 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 180 private: 181 182 void setMips16LibcallName(RTLIB::Libcall, const char *Name); 183 184 void setMips16HardFloatLibCalls(); 185 186 unsigned int 187 getMips16HelperFunctionStubNumber(ArgListTy &Args) const; 188 189 const char *getMips16HelperFunction 190 (Type* RetTy, ArgListTy &Args, bool &needHelper) const; 191 192 /// ByValArgInfo - Byval argument information. 193 struct ByValArgInfo { 194 unsigned FirstIdx; // Index of the first register used. 195 unsigned NumRegs; // Number of registers used for this argument. 196 unsigned Address; // Offset of the stack area used to pass this argument. 197 198 ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {} 199 }; 200 201 /// MipsCC - This class provides methods used to analyze formal and call 202 /// arguments and inquire about calling convention information. 203 class MipsCC { 204 public: 205 MipsCC(CallingConv::ID CallConv, bool IsO32, CCState &Info); 206 207 void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, 208 bool IsVarArg, bool IsSoftFloat, 209 const SDNode *CallNode, 210 std::vector<ArgListEntry> &FuncArgs); 211 void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, 212 bool IsSoftFloat, 213 Function::const_arg_iterator FuncArg); 214 215 void analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, 216 bool IsSoftFloat, const SDNode *CallNode, 217 const Type *RetTy) const; 218 219 void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, 220 bool IsSoftFloat, const Type *RetTy) const; 221 222 const CCState &getCCInfo() const { return CCInfo; } 223 224 /// hasByValArg - Returns true if function has byval arguments. 225 bool hasByValArg() const { return !ByValArgs.empty(); } 226 227 /// regSize - Size (in number of bits) of integer registers. 228 unsigned regSize() const { return IsO32 ? 4 : 8; } 229 230 /// numIntArgRegs - Number of integer registers available for calls. 231 unsigned numIntArgRegs() const; 232 233 /// reservedArgArea - The size of the area the caller reserves for 234 /// register arguments. This is 16-byte if ABI is O32. 235 unsigned reservedArgArea() const; 236 237 /// Return pointer to array of integer argument registers. 238 const uint16_t *intArgRegs() const; 239 240 typedef SmallVector<ByValArgInfo, 2>::const_iterator byval_iterator; 241 byval_iterator byval_begin() const { return ByValArgs.begin(); } 242 byval_iterator byval_end() const { return ByValArgs.end(); } 243 244 private: 245 void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT, 246 CCValAssign::LocInfo LocInfo, 247 ISD::ArgFlagsTy ArgFlags); 248 249 /// useRegsForByval - Returns true if the calling convention allows the 250 /// use of registers to pass byval arguments. 251 bool useRegsForByval() const { return CallConv != CallingConv::Fast; } 252 253 /// Return the function that analyzes fixed argument list functions. 254 llvm::CCAssignFn *fixedArgFn() const; 255 256 /// Return the function that analyzes variable argument list functions. 257 llvm::CCAssignFn *varArgFn() const; 258 259 const uint16_t *shadowRegs() const; 260 261 void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize, 262 unsigned Align); 263 264 /// Return the type of the register which is used to pass an argument or 265 /// return a value. This function returns f64 if the argument is an i64 266 /// value which has been generated as a result of softening an f128 value. 267 /// Otherwise, it just returns VT. 268 MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode, 269 bool IsSoftFloat) const; 270 271 template<typename Ty> 272 void analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat, 273 const SDNode *CallNode, const Type *RetTy) const; 274 275 CCState &CCInfo; 276 CallingConv::ID CallConv; 277 bool IsO32; 278 SmallVector<ByValArgInfo, 2> ByValArgs; 279 }; 280 281 // Subtarget Info 282 const MipsSubtarget *Subtarget; 283 284 bool HasMips64, IsN64, IsO32; 285 286 // Lower Operand helpers 287 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 288 CallingConv::ID CallConv, bool isVarArg, 289 const SmallVectorImpl<ISD::InputArg> &Ins, 290 DebugLoc dl, SelectionDAG &DAG, 291 SmallVectorImpl<SDValue> &InVals, 292 const SDNode *CallNode, const Type *RetTy) const; 293 294 // Lower Operand specifics 295 SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 296 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 297 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 298 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 299 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 300 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 301 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 302 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const; 303 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 304 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const; 305 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const; 306 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 307 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const; 308 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 309 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 310 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const; 311 SDValue lowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const; 312 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const; 313 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const; 314 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG, 315 bool IsSRA) const; 316 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const; 317 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const; 318 SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 319 SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 320 SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const; 321 322 /// isEligibleForTailCallOptimization - Check whether the call is eligible 323 /// for tail call optimization. 324 bool isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo, 325 unsigned NextStackOffset, 326 const MipsFunctionInfo& FI) const; 327 328 /// copyByValArg - Copy argument registers which were used to pass a byval 329 /// argument to the stack. Create a stack frame object for the byval 330 /// argument. 331 void copyByValRegs(SDValue Chain, DebugLoc DL, 332 std::vector<SDValue> &OutChains, SelectionDAG &DAG, 333 const ISD::ArgFlagsTy &Flags, 334 SmallVectorImpl<SDValue> &InVals, 335 const Argument *FuncArg, 336 const MipsCC &CC, const ByValArgInfo &ByVal) const; 337 338 /// passByValArg - Pass a byval argument in registers or on stack. 339 void passByValArg(SDValue Chain, DebugLoc DL, 340 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 341 SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr, 342 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, 343 const MipsCC &CC, const ByValArgInfo &ByVal, 344 const ISD::ArgFlagsTy &Flags, bool isLittle) const; 345 346 /// writeVarArgRegs - Write variable function arguments passed in registers 347 /// to the stack. Also create a stack frame object for the first variable 348 /// argument. 349 void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC, 350 SDValue Chain, DebugLoc DL, SelectionDAG &DAG) const; 351 352 virtual SDValue 353 LowerFormalArguments(SDValue Chain, 354 CallingConv::ID CallConv, bool isVarArg, 355 const SmallVectorImpl<ISD::InputArg> &Ins, 356 DebugLoc dl, SelectionDAG &DAG, 357 SmallVectorImpl<SDValue> &InVals) const; 358 359 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain, 360 SDValue Arg, DebugLoc DL, bool IsTailCall, 361 SelectionDAG &DAG) const; 362 363 virtual SDValue 364 LowerCall(TargetLowering::CallLoweringInfo &CLI, 365 SmallVectorImpl<SDValue> &InVals) const; 366 367 virtual bool 368 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 369 bool isVarArg, 370 const SmallVectorImpl<ISD::OutputArg> &Outs, 371 LLVMContext &Context) const; 372 373 virtual SDValue 374 LowerReturn(SDValue Chain, 375 CallingConv::ID CallConv, bool isVarArg, 376 const SmallVectorImpl<ISD::OutputArg> &Outs, 377 const SmallVectorImpl<SDValue> &OutVals, 378 DebugLoc dl, SelectionDAG &DAG) const; 379 380 virtual MachineBasicBlock * 381 EmitInstrWithCustomInserter(MachineInstr *MI, 382 MachineBasicBlock *MBB) const; 383 384 // Inline asm support 385 ConstraintType getConstraintType(const std::string &Constraint) const; 386 387 /// Examine constraint string and operand type and determine a weight value. 388 /// The operand object must already have been set up with the operand type. 389 ConstraintWeight getSingleConstraintMatchWeight( 390 AsmOperandInfo &info, const char *constraint) const; 391 392 std::pair<unsigned, const TargetRegisterClass*> 393 getRegForInlineAsmConstraint(const std::string &Constraint, 394 EVT VT) const; 395 396 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 397 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 398 /// true it means one of the asm constraint of the inline asm instruction 399 /// being processed is 'm'. 400 virtual void LowerAsmOperandForConstraint(SDValue Op, 401 std::string &Constraint, 402 std::vector<SDValue> &Ops, 403 SelectionDAG &DAG) const; 404 405 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const; 406 407 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 408 409 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 410 unsigned SrcAlign, 411 bool IsMemset, bool ZeroMemset, 412 bool MemcpyStrSrc, 413 MachineFunction &MF) const; 414 415 /// isFPImmLegal - Returns true if the target can instruction select the 416 /// specified FP immediate natively. If false, the legalizer will 417 /// materialize the FP immediate as a load from a constant pool. 418 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; 419 420 virtual unsigned getJumpTableEncoding() const; 421 422 MachineBasicBlock *emitBPOSGE32(MachineInstr *MI, 423 MachineBasicBlock *BB) const; 424 MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 425 unsigned Size, unsigned BinOpcode, bool Nand = false) const; 426 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI, 427 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode, 428 bool Nand = false) const; 429 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI, 430 MachineBasicBlock *BB, unsigned Size) const; 431 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI, 432 MachineBasicBlock *BB, unsigned Size) const; 433 MachineBasicBlock *emitSel16(unsigned Opc, MachineInstr *MI, 434 MachineBasicBlock *BB) const; 435 MachineBasicBlock *emitSeliT16(unsigned Opc1, unsigned Opc2, 436 MachineInstr *MI, 437 MachineBasicBlock *BB) const; 438 439 MachineBasicBlock *emitSelT16(unsigned Opc1, unsigned Opc2, 440 MachineInstr *MI, 441 MachineBasicBlock *BB) const; 442 MachineBasicBlock *emitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc, 443 MachineInstr *MI, 444 MachineBasicBlock *BB) const; 445 MachineBasicBlock *emitFEXT_T8I8I16_ins( 446 unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc, 447 MachineInstr *MI, MachineBasicBlock *BB) const; 448 MachineBasicBlock *emitFEXT_CCRX16_ins( 449 unsigned SltOpc, 450 MachineInstr *MI, MachineBasicBlock *BB) const; 451 MachineBasicBlock *emitFEXT_CCRXI16_ins( 452 unsigned SltiOpc, unsigned SltiXOpc, 453 MachineInstr *MI, MachineBasicBlock *BB )const; 454 455 }; 456} 457 458#endif // MipsISELLOWERING_H 459