MipsInstrFPU.td revision 088483627720acb58c96951b7b634f67312c7272
1607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com//===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===// 2607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com// 3607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com// The LLVM Compiler Infrastructure 4607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com// 5607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com// This file is distributed under the University of Illinois Open Source 6607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com// License. See LICENSE.TXT for details. 7607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com// 8607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com//===----------------------------------------------------------------------===// 9607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com// 10607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com// This file describes the Mips FPU instruction set. 11607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com// 12607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com//===----------------------------------------------------------------------===// 13607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com 14607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com//===----------------------------------------------------------------------===// 158a1cdaece7e1d009befb84f21bb82370025bf4d6robertphillips@google.com// Floating Point Instructions 16607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com// ------------------------ 172d9dbd4f78314b4b36f67d6ebbf3e0f2d9a163e3borenet@google.com// * 64bit fp: 182d9dbd4f78314b4b36f67d6ebbf3e0f2d9a163e3borenet@google.com// - 32 64-bit registers (default mode) 19607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com// - 16 even 32-bit registers (32-bit compatible mode) for 20607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com// single and double access. 21607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com// * 32bit fp: 22607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com// - 16 even 32-bit registers - single and double (aliased) 23607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com// - 32 32-bit registers (within single-only mode) 24607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com//===----------------------------------------------------------------------===// 25607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com 26607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com// Floating Point Compare and Branch 27607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.comdef SDT_MipsFPBrcond : SDTypeProfile<0, 2, [SDTCisInt<0>, 28607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com SDTCisVT<1, OtherVT>]>; 29607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.comdef SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>, 30607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com SDTCisVT<2, i32>]>; 31607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.comdef SDT_MipsCMovFP : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, 32607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com SDTCisSameAs<1, 2>]>; 33607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.comdef SDT_MipsTruncIntFP : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>; 34607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.comdef SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, 35607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com SDTCisVT<1, i32>, 36607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com SDTCisSameAs<1, 2>]>; 37607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.comdef SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, 38607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com SDTCisVT<1, f64>, 39607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com SDTCisVT<2, i32>]>; 40607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com 41607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.comdef MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>; 42607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.comdef MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>; 43607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.comdef MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>; 44607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.comdef MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond, 45607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com [SDNPHasChain, SDNPOptInGlue]>; 46607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.comdef MipsTruncIntFP : SDNode<"MipsISD::TruncIntFP", SDT_MipsTruncIntFP>; 478a1cdaece7e1d009befb84f21bb82370025bf4d6robertphillips@google.comdef MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>; 48607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.comdef MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64", 49607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com SDT_MipsExtractElementF64>; 50607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com 518a1cdaece7e1d009befb84f21bb82370025bf4d6robertphillips@google.com// Operand for printing out a condition code. 528a1cdaece7e1d009befb84f21bb82370025bf4d6robertphillips@google.comlet PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in 538a1cdaece7e1d009befb84f21bb82370025bf4d6robertphillips@google.com def condcode : Operand<i32>; 548a1cdaece7e1d009befb84f21bb82370025bf4d6robertphillips@google.com 55607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com//===----------------------------------------------------------------------===// 56607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com// Feature predicates. 57607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com//===----------------------------------------------------------------------===// 58607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com 59607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.comdef IsFP64bit : Predicate<"Subtarget.isFP64bit()">, 60607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com AssemblerPredicate<"FeatureFP64Bit">; 61607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.comdef NotFP64bit : Predicate<"!Subtarget.isFP64bit()">, 62607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com AssemblerPredicate<"!FeatureFP64Bit">; 63607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.comdef IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">, 64607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com AssemblerPredicate<"FeatureSingleFloat">; 6525bc2f86c2b94ee1f0921d90e6629d8cb22f69b7robertphillips@google.comdef IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">, 66607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com AssemblerPredicate<"!FeatureSingleFloat">; 67607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com 68607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com// FP immediate patterns. 69607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.comdef fpimm0 : PatLeaf<(fpimm), [{ 70607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com return N->isExactlyValue(+0.0); 71e8cc6e8071935339a06548b13a0668b56a7540f5bungeman@google.com}]>; 72607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com 73e8cc6e8071935339a06548b13a0668b56a7540f5bungeman@google.comdef fpimm0neg : PatLeaf<(fpimm), [{ 74607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com return N->isExactlyValue(-0.0); 75607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com}]>; 76607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com 77607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com//===----------------------------------------------------------------------===// 78607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com// Instruction Class Templates 79607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com// 8097cee9735350cb472249ce1a827ba1aa6b2a5f59chudy@google.com// A set of multiclasses is used to address the register usage. 81607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com// 82607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com// S32 - single precision in 16 32bit even fp registers 83607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com// single precision in 32 32bit fp registers in SingleOnly mode 84607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com// S64 - single precision in 32 64bit fp registers (In64BitMode) 85607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com// D32 - double precision in 16 32bit even fp registers 86607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com// D64 - double precision in 32 64bit fp registers (In64BitMode) 87607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com// 88607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com// Only S32 and D32 are supported right now. 89607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com//===----------------------------------------------------------------------===// 90607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com 91607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.comclass ADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, bit IsComm, 92607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com SDPatternOperator OpNode= null_frag> : 93607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft), 94607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com !strconcat(opstr, "\t$fd, $fs, $ft"), 95607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR> { 96607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com let isCommutable = IsComm; 97607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com} 98607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com 99607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.commulticlass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm, 100607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com SDPatternOperator OpNode = null_frag> { 101607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com def _D32 : ADDS_FT<opstr, AFGR64RegsOpnd, Itin, IsComm, OpNode>, 102607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com Requires<[NotFP64bit, HasStdEnc]>; 103607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com def _D64 : ADDS_FT<opstr, FGR64RegsOpnd, Itin, IsComm, OpNode>, 104f4741c1322944e194ca34a8f5cf8188fe2c0efe2robertphillips@google.com Requires<[IsFP64bit, HasStdEnc]> { 105f4741c1322944e194ca34a8f5cf8188fe2c0efe2robertphillips@google.com string DecoderNamespace = "Mips64"; 106f4741c1322944e194ca34a8f5cf8188fe2c0efe2robertphillips@google.com } 107f4741c1322944e194ca34a8f5cf8188fe2c0efe2robertphillips@google.com} 108f4741c1322944e194ca34a8f5cf8188fe2c0efe2robertphillips@google.com 109f4741c1322944e194ca34a8f5cf8188fe2c0efe2robertphillips@google.comclass ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 110e428f9b1132c12299c204a333192495d7e748511robertphillips@google.com InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 111e428f9b1132c12299c204a333192495d7e748511robertphillips@google.com InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"), 112f4741c1322944e194ca34a8f5cf8188fe2c0efe2robertphillips@google.com [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR>, 113607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com NeverHasSideEffects; 114607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com 115607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.commulticlass ABSS_M<string opstr, InstrItinClass Itin, 116607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com SDPatternOperator OpNode= null_frag> { 117607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com def _D32 : ABSS_FT<opstr, AFGR64RegsOpnd, AFGR64RegsOpnd, Itin, OpNode>, 118607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com Requires<[NotFP64bit, HasStdEnc]>; 119607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com def _D64 : ABSS_FT<opstr, FGR64RegsOpnd, FGR64RegsOpnd, Itin, OpNode>, 120607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com Requires<[IsFP64bit, HasStdEnc]> { 121607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com string DecoderNamespace = "Mips64"; 122607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com } 123607357fde8a9c4c70549d4223e0bd1181b012e0echudy@google.com} 124 125multiclass ROUND_M<string opstr, InstrItinClass Itin> { 126 def _D32 : ABSS_FT<opstr, FGR32RegsOpnd, AFGR64RegsOpnd, Itin>, 127 Requires<[NotFP64bit, HasStdEnc]>; 128 def _D64 : ABSS_FT<opstr, FGR32RegsOpnd, FGR64RegsOpnd, Itin>, 129 Requires<[IsFP64bit, HasStdEnc]> { 130 let DecoderNamespace = "Mips64"; 131 } 132} 133 134class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 135 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 136 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"), 137 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR>; 138 139class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 140 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 141 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"), 142 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR>; 143 144class MFC1_FT_CCR<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 145 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 146 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"), 147 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR>; 148 149class MTC1_FT_CCR<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 150 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 151 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"), 152 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR>; 153 154class LW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 155 Operand MemOpnd, SDPatternOperator OpNode= null_frag> : 156 InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 157 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI> { 158 let DecoderMethod = "DecodeFMem"; 159 let mayLoad = 1; 160} 161 162class SW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 163 Operand MemOpnd, SDPatternOperator OpNode= null_frag> : 164 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 165 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI> { 166 let DecoderMethod = "DecodeFMem"; 167 let mayStore = 1; 168} 169 170class MADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 171 SDPatternOperator OpNode = null_frag> : 172 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft), 173 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"), 174 [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))], Itin, FrmFR>; 175 176class NMADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 177 SDPatternOperator OpNode = null_frag> : 178 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft), 179 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"), 180 [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))], 181 Itin, FrmFR>; 182 183class LWXC1_FT<string opstr, RegisterOperand DRC, RegisterOperand PRC, 184 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> : 185 InstSE<(outs DRC:$fd), (ins PRC:$base, PRC:$index), 186 !strconcat(opstr, "\t$fd, ${index}(${base})"), 187 [(set DRC:$fd, (OpNode (add PRC:$base, PRC:$index)))], Itin, FrmFI> { 188 let AddedComplexity = 20; 189} 190 191class SWXC1_FT<string opstr, RegisterOperand DRC, RegisterOperand PRC, 192 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> : 193 InstSE<(outs), (ins DRC:$fs, PRC:$base, PRC:$index), 194 !strconcat(opstr, "\t$fs, ${index}(${base})"), 195 [(OpNode DRC:$fs, (add PRC:$base, PRC:$index))], Itin, FrmFI> { 196 let AddedComplexity = 20; 197} 198 199class BC1F_FT<string opstr, InstrItinClass Itin, 200 SDPatternOperator Op = null_frag> : 201 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"), 202 [(MipsFPBrcond Op, bb:$offset)], Itin, FrmFI> { 203 let isBranch = 1; 204 let isTerminator = 1; 205 let hasDelaySlot = 1; 206 let Defs = [AT]; 207 let Uses = [FCR31]; 208} 209 210class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin, 211 SDPatternOperator OpNode = null_frag> : 212 InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond), 213 !strconcat("c.$cond.", typestr, "\t$fs, $ft"), 214 [(OpNode RC:$fs, RC:$ft, imm:$cond)], Itin, FrmFR> { 215 let Defs = [FCR31]; 216 let isCodeGenOnly = 1; 217} 218 219class C_COND_FT<string CondStr, string Typestr, RegisterOperand RC> : 220 InstSE<(outs), (ins RC:$fs, RC:$ft), 221 !strconcat("c.", CondStr, ".", Typestr, "\t$fs, $ft"), [], IIFcmp, 222 FrmFR>; 223 224multiclass C_COND_M<string TypeStr, RegisterOperand RC, bits<5> fmt> { 225 def C_F_#NAME : C_COND_FT<"f", TypeStr, RC>, C_COND_FM<fmt, 0>; 226 def C_UN_#NAME : C_COND_FT<"un", TypeStr, RC>, C_COND_FM<fmt, 1>; 227 def C_EQ_#NAME : C_COND_FT<"eq", TypeStr, RC>, C_COND_FM<fmt, 2>; 228 def C_UEQ_#NAME : C_COND_FT<"ueq", TypeStr, RC>, C_COND_FM<fmt, 3>; 229 def C_OLT_#NAME : C_COND_FT<"olt", TypeStr, RC>, C_COND_FM<fmt, 4>; 230 def C_ULT_#NAME : C_COND_FT<"ult", TypeStr, RC>, C_COND_FM<fmt, 5>; 231 def C_OLE_#NAME : C_COND_FT<"ole", TypeStr, RC>, C_COND_FM<fmt, 6>; 232 def C_ULE_#NAME : C_COND_FT<"ule", TypeStr, RC>, C_COND_FM<fmt, 7>; 233 def C_SF_#NAME : C_COND_FT<"sf", TypeStr, RC>, C_COND_FM<fmt, 8>; 234 def C_NGLE_#NAME : C_COND_FT<"ngle", TypeStr, RC>, C_COND_FM<fmt, 9>; 235 def C_SEQ_#NAME : C_COND_FT<"seq", TypeStr, RC>, C_COND_FM<fmt, 10>; 236 def C_NGL_#NAME : C_COND_FT<"ngl", TypeStr, RC>, C_COND_FM<fmt, 11>; 237 def C_LT_#NAME : C_COND_FT<"lt", TypeStr, RC>, C_COND_FM<fmt, 12>; 238 def C_NGE_#NAME : C_COND_FT<"nge", TypeStr, RC>, C_COND_FM<fmt, 13>; 239 def C_LE_#NAME : C_COND_FT<"le", TypeStr, RC>, C_COND_FM<fmt, 14>; 240 def C_NGT_#NAME : C_COND_FT<"ngt", TypeStr, RC>, C_COND_FM<fmt, 15>; 241} 242 243defm S : C_COND_M<"s", FGR32RegsOpnd, 16>; 244defm D32 : C_COND_M<"d", AFGR64RegsOpnd, 17>, 245 Requires<[NotFP64bit, HasStdEnc]>; 246let DecoderNamespace = "Mips64" in 247defm D64 : C_COND_M<"d", FGR64RegsOpnd, 17>, Requires<[IsFP64bit, HasStdEnc]>; 248 249//===----------------------------------------------------------------------===// 250// Floating Point Instructions 251//===----------------------------------------------------------------------===// 252def ROUND_W_S : ABSS_FT<"round.w.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFcvt>, 253 ABSS_FM<0xc, 16>; 254def TRUNC_W_S : ABSS_FT<"trunc.w.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFcvt>, 255 ABSS_FM<0xd, 16>; 256def CEIL_W_S : ABSS_FT<"ceil.w.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFcvt>, 257 ABSS_FM<0xe, 16>; 258def FLOOR_W_S : ABSS_FT<"floor.w.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFcvt>, 259 ABSS_FM<0xf, 16>; 260def CVT_W_S : ABSS_FT<"cvt.w.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFcvt>, 261 ABSS_FM<0x24, 16>; 262 263defm ROUND_W : ROUND_M<"round.w.d", IIFcvt>, ABSS_FM<0xc, 17>; 264defm TRUNC_W : ROUND_M<"trunc.w.d", IIFcvt>, ABSS_FM<0xd, 17>; 265defm CEIL_W : ROUND_M<"ceil.w.d", IIFcvt>, ABSS_FM<0xe, 17>; 266defm FLOOR_W : ROUND_M<"floor.w.d", IIFcvt>, ABSS_FM<0xf, 17>; 267defm CVT_W : ROUND_M<"cvt.w.d", IIFcvt>, ABSS_FM<0x24, 17>; 268 269let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in { 270 def ROUND_L_S : ABSS_FT<"round.l.s", FGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>, 271 ABSS_FM<0x8, 16>; 272 def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64RegsOpnd, FGR64RegsOpnd, IIFcvt>, 273 ABSS_FM<0x8, 17>; 274 def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>, 275 ABSS_FM<0x9, 16>; 276 def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64RegsOpnd, FGR64RegsOpnd, IIFcvt>, 277 ABSS_FM<0x9, 17>; 278 def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>, 279 ABSS_FM<0xa, 16>; 280 def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64RegsOpnd, FGR64RegsOpnd, IIFcvt>, 281 ABSS_FM<0xa, 17>; 282 def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>, 283 ABSS_FM<0xb, 16>; 284 def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64RegsOpnd, FGR64RegsOpnd, IIFcvt>, 285 ABSS_FM<0xb, 17>; 286} 287 288def CVT_S_W : ABSS_FT<"cvt.s.w", FGR32RegsOpnd, FGR32RegsOpnd, IIFcvt>, 289 ABSS_FM<0x20, 20>; 290def CVT_L_S : ABSS_FT<"cvt.l.s", FGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>, 291 ABSS_FM<0x25, 16>; 292def CVT_L_D64: ABSS_FT<"cvt.l.d", FGR64RegsOpnd, FGR64RegsOpnd, IIFcvt>, 293 ABSS_FM<0x25, 17>; 294 295let Predicates = [NotFP64bit, HasStdEnc] in { 296 def CVT_S_D32 : ABSS_FT<"cvt.s.d", FGR32RegsOpnd, AFGR64RegsOpnd, IIFcvt>, 297 ABSS_FM<0x20, 17>; 298 def CVT_D32_W : ABSS_FT<"cvt.d.w", AFGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>, 299 ABSS_FM<0x21, 20>; 300 def CVT_D32_S : ABSS_FT<"cvt.d.s", AFGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>, 301 ABSS_FM<0x21, 16>; 302} 303 304let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in { 305 def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32RegsOpnd, FGR64RegsOpnd, IIFcvt>, 306 ABSS_FM<0x20, 17>; 307 def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32RegsOpnd, FGR64RegsOpnd, IIFcvt>, 308 ABSS_FM<0x20, 21>; 309 def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>, 310 ABSS_FM<0x21, 20>; 311 def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>, 312 ABSS_FM<0x21, 16>; 313 def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64RegsOpnd, FGR64RegsOpnd, IIFcvt>, 314 ABSS_FM<0x21, 21>; 315} 316 317let isPseudo = 1, isCodeGenOnly = 1 in { 318 def PseudoCVT_S_W : ABSS_FT<"", FGR32RegsOpnd, CPURegsOpnd, IIFcvt>; 319 def PseudoCVT_D32_W : ABSS_FT<"", AFGR64RegsOpnd, CPURegsOpnd, IIFcvt>; 320 def PseudoCVT_S_L : ABSS_FT<"", FGR64RegsOpnd, CPU64RegsOpnd, IIFcvt>; 321 def PseudoCVT_D64_W : ABSS_FT<"", FGR64RegsOpnd, CPURegsOpnd, IIFcvt>; 322 def PseudoCVT_D64_L : ABSS_FT<"", FGR64RegsOpnd, CPU64RegsOpnd, IIFcvt>; 323} 324 325let Predicates = [NoNaNsFPMath, HasStdEnc] in { 326 def FABS_S : ABSS_FT<"abs.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFcvt, fabs>, 327 ABSS_FM<0x5, 16>; 328 def FNEG_S : ABSS_FT<"neg.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFcvt, fneg>, 329 ABSS_FM<0x7, 16>; 330 defm FABS : ABSS_M<"abs.d", IIFcvt, fabs>, ABSS_FM<0x5, 17>; 331 defm FNEG : ABSS_M<"neg.d", IIFcvt, fneg>, ABSS_FM<0x7, 17>; 332} 333 334def FSQRT_S : ABSS_FT<"sqrt.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFsqrtSingle, 335 fsqrt>, ABSS_FM<0x4, 16>; 336defm FSQRT : ABSS_M<"sqrt.d", IIFsqrtDouble, fsqrt>, ABSS_FM<0x4, 17>; 337 338// The odd-numbered registers are only referenced when doing loads, 339// stores, and moves between floating-point and integer registers. 340// When defining instructions, we reference all 32-bit registers, 341// regardless of register aliasing. 342 343/// Move Control Registers From/To CPU Registers 344def CFC1 : MFC1_FT_CCR<"cfc1", CPURegsOpnd, CCROpnd, IIFmove>, MFC1_FM<2>; 345def CTC1 : MTC1_FT_CCR<"ctc1", CCROpnd, CPURegsOpnd, IIFmove>, MFC1_FM<6>; 346def MFC1 : MFC1_FT<"mfc1", CPURegsOpnd, FGR32RegsOpnd, IIFmoveC1, bitconvert>, 347 MFC1_FM<0>; 348def MTC1 : MTC1_FT<"mtc1", FGR32RegsOpnd, CPURegsOpnd, IIFmoveC1, bitconvert>, 349 MFC1_FM<4>; 350def DMFC1 : MFC1_FT<"dmfc1", CPU64RegsOpnd, FGR64RegsOpnd, IIFmoveC1, 351 bitconvert>, MFC1_FM<1>; 352def DMTC1 : MTC1_FT<"dmtc1", FGR64RegsOpnd, CPU64RegsOpnd, IIFmoveC1, 353 bitconvert>, MFC1_FM<5>; 354 355def FMOV_S : ABSS_FT<"mov.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFmove>, 356 ABSS_FM<0x6, 16>; 357def FMOV_D32 : ABSS_FT<"mov.d", AFGR64RegsOpnd, AFGR64RegsOpnd, IIFmove>, 358 ABSS_FM<0x6, 17>, Requires<[NotFP64bit, HasStdEnc]>; 359def FMOV_D64 : ABSS_FT<"mov.d", FGR64RegsOpnd, FGR64RegsOpnd, IIFmove>, 360 ABSS_FM<0x6, 17>, Requires<[IsFP64bit, HasStdEnc]> { 361 let DecoderNamespace = "Mips64"; 362} 363 364/// Floating Point Memory Instructions 365let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in { 366 def LWC1_P8 : LW_FT<"lwc1", FGR32RegsOpnd, IIFLoad, mem64, load>, 367 LW_FM<0x31>; 368 def SWC1_P8 : SW_FT<"swc1", FGR32RegsOpnd, IIFStore, mem64, store>, 369 LW_FM<0x39>; 370 def LDC164_P8 : LW_FT<"ldc1", FGR64RegsOpnd, IIFLoad, mem64, load>, 371 LW_FM<0x35> { 372 let isCodeGenOnly =1; 373 } 374 def SDC164_P8 : SW_FT<"sdc1", FGR64RegsOpnd, IIFStore, mem64, store>, 375 LW_FM<0x3d> { 376 let isCodeGenOnly =1; 377 } 378} 379 380let Predicates = [NotN64, HasStdEnc] in { 381 def LWC1 : LW_FT<"lwc1", FGR32RegsOpnd, IIFLoad, mem, load>, LW_FM<0x31>; 382 def SWC1 : SW_FT<"swc1", FGR32RegsOpnd, IIFStore, mem, store>, LW_FM<0x39>; 383} 384 385let Predicates = [NotN64, HasMips64, HasStdEnc], 386 DecoderNamespace = "Mips64" in { 387 def LDC164 : LW_FT<"ldc1", FGR64RegsOpnd, IIFLoad, mem, load>, LW_FM<0x35>; 388 def SDC164 : SW_FT<"sdc1", FGR64RegsOpnd, IIFStore, mem, store>, LW_FM<0x3d>; 389} 390 391let Predicates = [NotN64, NotMips64, HasStdEnc] in { 392 let isPseudo = 1, isCodeGenOnly = 1 in { 393 def PseudoLDC1 : LW_FT<"", AFGR64RegsOpnd, IIFLoad, mem, load>; 394 def PseudoSDC1 : SW_FT<"", AFGR64RegsOpnd, IIFStore, mem, store>; 395 } 396 def LDC1 : LW_FT<"ldc1", AFGR64RegsOpnd, IIFLoad, mem>, LW_FM<0x35>; 397 def SDC1 : SW_FT<"sdc1", AFGR64RegsOpnd, IIFStore, mem>, LW_FM<0x3d>; 398} 399 400// Indexed loads and stores. 401let Predicates = [HasFPIdx, HasStdEnc] in { 402 def LWXC1 : LWXC1_FT<"lwxc1", FGR32RegsOpnd, CPURegsOpnd, IIFLoad, load>, 403 LWXC1_FM<0>; 404 def SWXC1 : SWXC1_FT<"swxc1", FGR32RegsOpnd, CPURegsOpnd, IIFStore, store>, 405 SWXC1_FM<8>; 406} 407 408let Predicates = [HasMips32r2, NotMips64, HasStdEnc] in { 409 def LDXC1 : LWXC1_FT<"ldxc1", AFGR64RegsOpnd, CPURegsOpnd, IIFLoad, load>, 410 LWXC1_FM<1>; 411 def SDXC1 : SWXC1_FT<"sdxc1", AFGR64RegsOpnd, CPURegsOpnd, IIFStore, store>, 412 SWXC1_FM<9>; 413} 414 415let Predicates = [HasMips64, NotN64, HasStdEnc], DecoderNamespace="Mips64" in { 416 def LDXC164 : LWXC1_FT<"ldxc1", FGR64RegsOpnd, CPURegsOpnd, IIFLoad, load>, 417 LWXC1_FM<1>; 418 def SDXC164 : SWXC1_FT<"sdxc1", FGR64RegsOpnd, CPURegsOpnd, IIFStore, store>, 419 SWXC1_FM<9>; 420} 421 422// n64 423let Predicates = [IsN64, HasStdEnc], isCodeGenOnly=1 in { 424 def LWXC1_P8 : LWXC1_FT<"lwxc1", FGR32RegsOpnd, CPU64RegsOpnd, IIFLoad, load>, 425 LWXC1_FM<0>; 426 def LDXC164_P8 : LWXC1_FT<"ldxc1", FGR64RegsOpnd, CPU64RegsOpnd, IIFLoad, 427 load>, LWXC1_FM<1>; 428 def SWXC1_P8 : SWXC1_FT<"swxc1", FGR32RegsOpnd, CPU64RegsOpnd, IIFStore, 429 store>, SWXC1_FM<8>; 430 def SDXC164_P8 : SWXC1_FT<"sdxc1", FGR64RegsOpnd, CPU64RegsOpnd, IIFStore, 431 store>, SWXC1_FM<9>; 432} 433 434// Load/store doubleword indexed unaligned. 435let Predicates = [NotMips64, HasStdEnc] in { 436 def LUXC1 : LWXC1_FT<"luxc1", AFGR64RegsOpnd, CPURegsOpnd, IIFLoad>, 437 LWXC1_FM<0x5>; 438 def SUXC1 : SWXC1_FT<"suxc1", AFGR64RegsOpnd, CPURegsOpnd, IIFStore>, 439 SWXC1_FM<0xd>; 440} 441 442let Predicates = [HasMips64, HasStdEnc], 443 DecoderNamespace="Mips64" in { 444 def LUXC164 : LWXC1_FT<"luxc1", FGR64RegsOpnd, CPURegsOpnd, IIFLoad>, 445 LWXC1_FM<0x5>; 446 def SUXC164 : SWXC1_FT<"suxc1", FGR64RegsOpnd, CPURegsOpnd, IIFStore>, 447 SWXC1_FM<0xd>; 448} 449 450/// Floating-point Aritmetic 451def FADD_S : ADDS_FT<"add.s", FGR32RegsOpnd, IIFadd, 1, fadd>, 452 ADDS_FM<0x00, 16>; 453defm FADD : ADDS_M<"add.d", IIFadd, 1, fadd>, ADDS_FM<0x00, 17>; 454def FDIV_S : ADDS_FT<"div.s", FGR32RegsOpnd, IIFdivSingle, 0, fdiv>, 455 ADDS_FM<0x03, 16>; 456defm FDIV : ADDS_M<"div.d", IIFdivDouble, 0, fdiv>, ADDS_FM<0x03, 17>; 457def FMUL_S : ADDS_FT<"mul.s", FGR32RegsOpnd, IIFmulSingle, 1, fmul>, 458 ADDS_FM<0x02, 16>; 459defm FMUL : ADDS_M<"mul.d", IIFmulDouble, 1, fmul>, ADDS_FM<0x02, 17>; 460def FSUB_S : ADDS_FT<"sub.s", FGR32RegsOpnd, IIFadd, 0, fsub>, 461 ADDS_FM<0x01, 16>; 462defm FSUB : ADDS_M<"sub.d", IIFadd, 0, fsub>, ADDS_FM<0x01, 17>; 463 464let Predicates = [HasMips32r2, HasStdEnc] in { 465 def MADD_S : MADDS_FT<"madd.s", FGR32RegsOpnd, IIFmulSingle, fadd>, 466 MADDS_FM<4, 0>; 467 def MSUB_S : MADDS_FT<"msub.s", FGR32RegsOpnd, IIFmulSingle, fsub>, 468 MADDS_FM<5, 0>; 469} 470 471let Predicates = [HasMips32r2, NoNaNsFPMath, HasStdEnc] in { 472 def NMADD_S : NMADDS_FT<"nmadd.s", FGR32RegsOpnd, IIFmulSingle, fadd>, 473 MADDS_FM<6, 0>; 474 def NMSUB_S : NMADDS_FT<"nmsub.s", FGR32RegsOpnd, IIFmulSingle, fsub>, 475 MADDS_FM<7, 0>; 476} 477 478let Predicates = [HasMips32r2, NotFP64bit, HasStdEnc] in { 479 def MADD_D32 : MADDS_FT<"madd.d", AFGR64RegsOpnd, IIFmulDouble, fadd>, 480 MADDS_FM<4, 1>; 481 def MSUB_D32 : MADDS_FT<"msub.d", AFGR64RegsOpnd, IIFmulDouble, fsub>, 482 MADDS_FM<5, 1>; 483} 484 485let Predicates = [HasMips32r2, NotFP64bit, NoNaNsFPMath, HasStdEnc] in { 486 def NMADD_D32 : NMADDS_FT<"nmadd.d", AFGR64RegsOpnd, IIFmulDouble, fadd>, 487 MADDS_FM<6, 1>; 488 def NMSUB_D32 : NMADDS_FT<"nmsub.d", AFGR64RegsOpnd, IIFmulDouble, fsub>, 489 MADDS_FM<7, 1>; 490} 491 492let Predicates = [HasMips32r2, IsFP64bit, HasStdEnc], isCodeGenOnly=1 in { 493 def MADD_D64 : MADDS_FT<"madd.d", FGR64RegsOpnd, IIFmulDouble, fadd>, 494 MADDS_FM<4, 1>; 495 def MSUB_D64 : MADDS_FT<"msub.d", FGR64RegsOpnd, IIFmulDouble, fsub>, 496 MADDS_FM<5, 1>; 497} 498 499let Predicates = [HasMips32r2, IsFP64bit, NoNaNsFPMath, HasStdEnc], 500 isCodeGenOnly=1 in { 501 def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64RegsOpnd, IIFmulDouble, fadd>, 502 MADDS_FM<6, 1>; 503 def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64RegsOpnd, IIFmulDouble, fsub>, 504 MADDS_FM<7, 1>; 505} 506 507//===----------------------------------------------------------------------===// 508// Floating Point Branch Codes 509//===----------------------------------------------------------------------===// 510// Mips branch codes. These correspond to condcode in MipsInstrInfo.h. 511// They must be kept in synch. 512def MIPS_BRANCH_F : PatLeaf<(i32 0)>; 513def MIPS_BRANCH_T : PatLeaf<(i32 1)>; 514 515let DecoderMethod = "DecodeBC1" in { 516def BC1F : BC1F_FT<"bc1f", IIBranch, MIPS_BRANCH_F>, BC1F_FM<0, 0>; 517def BC1T : BC1F_FT<"bc1t", IIBranch, MIPS_BRANCH_T>, BC1F_FM<0, 1>; 518} 519//===----------------------------------------------------------------------===// 520// Floating Point Flag Conditions 521//===----------------------------------------------------------------------===// 522// Mips condition codes. They must correspond to condcode in MipsInstrInfo.h. 523// They must be kept in synch. 524def MIPS_FCOND_F : PatLeaf<(i32 0)>; 525def MIPS_FCOND_UN : PatLeaf<(i32 1)>; 526def MIPS_FCOND_OEQ : PatLeaf<(i32 2)>; 527def MIPS_FCOND_UEQ : PatLeaf<(i32 3)>; 528def MIPS_FCOND_OLT : PatLeaf<(i32 4)>; 529def MIPS_FCOND_ULT : PatLeaf<(i32 5)>; 530def MIPS_FCOND_OLE : PatLeaf<(i32 6)>; 531def MIPS_FCOND_ULE : PatLeaf<(i32 7)>; 532def MIPS_FCOND_SF : PatLeaf<(i32 8)>; 533def MIPS_FCOND_NGLE : PatLeaf<(i32 9)>; 534def MIPS_FCOND_SEQ : PatLeaf<(i32 10)>; 535def MIPS_FCOND_NGL : PatLeaf<(i32 11)>; 536def MIPS_FCOND_LT : PatLeaf<(i32 12)>; 537def MIPS_FCOND_NGE : PatLeaf<(i32 13)>; 538def MIPS_FCOND_LE : PatLeaf<(i32 14)>; 539def MIPS_FCOND_NGT : PatLeaf<(i32 15)>; 540 541/// Floating Point Compare 542def FCMP_S32 : CEQS_FT<"s", FGR32, IIFcmp, MipsFPCmp>, CEQS_FM<16>; 543def FCMP_D32 : CEQS_FT<"d", AFGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>, 544 Requires<[NotFP64bit, HasStdEnc]>; 545let DecoderNamespace = "Mips64" in 546def FCMP_D64 : CEQS_FT<"d", FGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>, 547 Requires<[IsFP64bit, HasStdEnc]>; 548 549//===----------------------------------------------------------------------===// 550// Floating Point Pseudo-Instructions 551//===----------------------------------------------------------------------===// 552def MOVCCRToCCR : PseudoSE<(outs CCR:$dst), (ins CCROpnd:$src), []>; 553 554// This pseudo instr gets expanded into 2 mtc1 instrs after register 555// allocation. 556def BuildPairF64 : 557 PseudoSE<(outs AFGR64RegsOpnd:$dst), 558 (ins CPURegsOpnd:$lo, CPURegsOpnd:$hi), 559 [(set AFGR64RegsOpnd:$dst, 560 (MipsBuildPairF64 CPURegsOpnd:$lo, CPURegsOpnd:$hi))]>; 561 562// This pseudo instr gets expanded into 2 mfc1 instrs after register 563// allocation. 564// if n is 0, lower part of src is extracted. 565// if n is 1, higher part of src is extracted. 566def ExtractElementF64 : 567 PseudoSE<(outs CPURegsOpnd:$dst), (ins AFGR64RegsOpnd:$src, i32imm:$n), 568 [(set CPURegsOpnd:$dst, 569 (MipsExtractElementF64 AFGR64RegsOpnd:$src, imm:$n))]>; 570 571//===----------------------------------------------------------------------===// 572// Floating Point Patterns 573//===----------------------------------------------------------------------===// 574def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>; 575def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>; 576 577def : MipsPat<(f32 (sint_to_fp CPURegsOpnd:$src)), 578 (PseudoCVT_S_W CPURegsOpnd:$src)>; 579def : MipsPat<(MipsTruncIntFP FGR32RegsOpnd:$src), 580 (TRUNC_W_S FGR32RegsOpnd:$src)>; 581 582let Predicates = [NotFP64bit, HasStdEnc] in { 583 def : MipsPat<(f64 (sint_to_fp CPURegsOpnd:$src)), 584 (PseudoCVT_D32_W CPURegsOpnd:$src)>; 585 def : MipsPat<(MipsTruncIntFP AFGR64RegsOpnd:$src), 586 (TRUNC_W_D32 AFGR64RegsOpnd:$src)>; 587 def : MipsPat<(f32 (fround AFGR64RegsOpnd:$src)), 588 (CVT_S_D32 AFGR64RegsOpnd:$src)>; 589 def : MipsPat<(f64 (fextend FGR32RegsOpnd:$src)), 590 (CVT_D32_S FGR32RegsOpnd:$src)>; 591} 592 593let Predicates = [IsFP64bit, HasStdEnc] in { 594 def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>; 595 def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>; 596 597 def : MipsPat<(f64 (sint_to_fp CPURegsOpnd:$src)), 598 (PseudoCVT_D64_W CPURegsOpnd:$src)>; 599 def : MipsPat<(f32 (sint_to_fp CPU64RegsOpnd:$src)), 600 (EXTRACT_SUBREG (PseudoCVT_S_L CPU64RegsOpnd:$src), sub_32)>; 601 def : MipsPat<(f64 (sint_to_fp CPU64RegsOpnd:$src)), 602 (PseudoCVT_D64_L CPU64RegsOpnd:$src)>; 603 604 def : MipsPat<(MipsTruncIntFP FGR64RegsOpnd:$src), 605 (TRUNC_W_D64 FGR64RegsOpnd:$src)>; 606 def : MipsPat<(MipsTruncIntFP FGR32RegsOpnd:$src), 607 (TRUNC_L_S FGR32RegsOpnd:$src)>; 608 def : MipsPat<(MipsTruncIntFP FGR64RegsOpnd:$src), 609 (TRUNC_L_D64 FGR64RegsOpnd:$src)>; 610 611 def : MipsPat<(f32 (fround FGR64RegsOpnd:$src)), 612 (CVT_S_D64 FGR64RegsOpnd:$src)>; 613 def : MipsPat<(f64 (fextend FGR32RegsOpnd:$src)), 614 (CVT_D64_S FGR32RegsOpnd:$src)>; 615} 616 617// Patterns for loads/stores with a reg+imm operand. 618let AddedComplexity = 40 in { 619 let Predicates = [IsN64, HasStdEnc] in { 620 def : LoadRegImmPat<LWC1_P8, f32, load>; 621 def : StoreRegImmPat<SWC1_P8, f32>; 622 def : LoadRegImmPat<LDC164_P8, f64, load>; 623 def : StoreRegImmPat<SDC164_P8, f64>; 624 } 625 626 let Predicates = [NotN64, HasStdEnc] in { 627 def : LoadRegImmPat<LWC1, f32, load>; 628 def : StoreRegImmPat<SWC1, f32>; 629 } 630 631 let Predicates = [NotN64, HasMips64, HasStdEnc] in { 632 def : LoadRegImmPat<LDC164, f64, load>; 633 def : StoreRegImmPat<SDC164, f64>; 634 } 635 636 let Predicates = [NotN64, NotMips64, HasStdEnc] in { 637 def : LoadRegImmPat<PseudoLDC1, f64, load>; 638 def : StoreRegImmPat<PseudoSDC1, f64>; 639 } 640} 641