MipsInstrFPU.td revision 10bd7264598a806aced15d0b7a3a5fc6803112a1
1//===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Mips FPU instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Floating Point Instructions 16// ------------------------ 17// * 64bit fp: 18// - 32 64-bit registers (default mode) 19// - 16 even 32-bit registers (32-bit compatible mode) for 20// single and double access. 21// * 32bit fp: 22// - 16 even 32-bit registers - single and double (aliased) 23// - 32 32-bit registers (within single-only mode) 24//===----------------------------------------------------------------------===// 25 26// Floating Point Compare and Branch 27def SDT_MipsFPBrcond : SDTypeProfile<0, 2, [SDTCisInt<0>, 28 SDTCisVT<1, OtherVT>]>; 29def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>, 30 SDTCisVT<2, i32>]>; 31def SDT_MipsCMovFP : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, 32 SDTCisSameAs<1, 2>]>; 33def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, 34 SDTCisVT<1, i32>, 35 SDTCisSameAs<1, 2>]>; 36def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, 37 SDTCisVT<1, f64>, 38 SDTCisVT<2, i32>]>; 39 40def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>; 41def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>; 42def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>; 43def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond, 44 [SDNPHasChain, SDNPOptInGlue]>; 45def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>; 46def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64", 47 SDT_MipsExtractElementF64>; 48 49// Operand for printing out a condition code. 50let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in 51 def condcode : Operand<i32>; 52 53//===----------------------------------------------------------------------===// 54// Feature predicates. 55//===----------------------------------------------------------------------===// 56 57def IsFP64bit : Predicate<"Subtarget.isFP64bit()">, 58 AssemblerPredicate<"FeatureFP64Bit">; 59def NotFP64bit : Predicate<"!Subtarget.isFP64bit()">, 60 AssemblerPredicate<"!FeatureFP64Bit">; 61def IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">, 62 AssemblerPredicate<"FeatureSingleFloat">; 63def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">, 64 AssemblerPredicate<"!FeatureSingleFloat">; 65 66// FP immediate patterns. 67def fpimm0 : PatLeaf<(fpimm), [{ 68 return N->isExactlyValue(+0.0); 69}]>; 70 71def fpimm0neg : PatLeaf<(fpimm), [{ 72 return N->isExactlyValue(-0.0); 73}]>; 74 75//===----------------------------------------------------------------------===// 76// Instruction Class Templates 77// 78// A set of multiclasses is used to address the register usage. 79// 80// S32 - single precision in 16 32bit even fp registers 81// single precision in 32 32bit fp registers in SingleOnly mode 82// S64 - single precision in 32 64bit fp registers (In64BitMode) 83// D32 - double precision in 16 32bit even fp registers 84// D64 - double precision in 32 64bit fp registers (In64BitMode) 85// 86// Only S32 and D32 are supported right now. 87//===----------------------------------------------------------------------===// 88 89// FP unary instructions without patterns. 90class FFR1<bits<6> funct, bits<5> fmt, string opstr, RegisterClass DstRC, 91 RegisterClass SrcRC> : 92 FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs), 93 !strconcat(opstr, "\t$fd, $fs"), []> { 94 let ft = 0; 95} 96 97// FP unary instructions with patterns. 98class FFR1P<bits<6> funct, bits<5> fmt, string opstr, RegisterClass DstRC, 99 RegisterClass SrcRC, SDNode OpNode> : 100 FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs), 101 !strconcat(opstr, "\t$fd, $fs"), 102 [(set DstRC:$fd, (OpNode SrcRC:$fs))]> { 103 let ft = 0; 104} 105 106class FFR2P<bits<6> funct, bits<5> fmt, string opstr, RegisterClass RC, 107 SDNode OpNode> : 108 FFR<0x11, funct, fmt, (outs RC:$fd), (ins RC:$fs, RC:$ft), 109 !strconcat(opstr, "\t$fd, $fs, $ft"), 110 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))]>; 111 112// FP load. 113let DecoderMethod = "DecodeFMem" in { 114class FPLoad<bits<6> op, string opstr, RegisterClass RC, Operand MemOpnd>: 115 FMem<op, (outs RC:$ft), (ins MemOpnd:$addr), 116 !strconcat(opstr, "\t$ft, $addr"), [(set RC:$ft, (load addr:$addr))], 117 IILoad>; 118 119// FP store. 120class FPStore<bits<6> op, string opstr, RegisterClass RC, Operand MemOpnd>: 121 FMem<op, (outs), (ins RC:$ft, MemOpnd:$addr), 122 !strconcat(opstr, "\t$ft, $addr"), [(store RC:$ft, addr:$addr)], 123 IIStore>; 124} 125// FP indexed load. 126class FPIdxLoad<bits<6> funct, string opstr, RegisterClass DRC, 127 RegisterClass PRC, SDPatternOperator FOp = null_frag>: 128 FFMemIdx<funct, (outs DRC:$fd), (ins PRC:$base, PRC:$index), 129 !strconcat(opstr, "\t$fd, ${index}(${base})"), 130 [(set DRC:$fd, (FOp (add PRC:$base, PRC:$index)))]> { 131 let fs = 0; 132} 133 134// FP indexed store. 135class FPIdxStore<bits<6> funct, string opstr, RegisterClass DRC, 136 RegisterClass PRC, SDPatternOperator FOp= null_frag>: 137 FFMemIdx<funct, (outs), (ins DRC:$fs, PRC:$base, PRC:$index), 138 !strconcat(opstr, "\t$fs, ${index}(${base})"), 139 [(FOp DRC:$fs, (add PRC:$base, PRC:$index))]> { 140 let fd = 0; 141} 142 143// Instructions that convert an FP value to 32-bit fixed point. 144multiclass FFR1_W_M<bits<6> funct, string opstr> { 145 def _D32 : FFR1<funct, 17, opstr, FGR32, AFGR64>, 146 Requires<[NotFP64bit, HasStdEnc]>; 147 def _D64 : FFR1<funct, 17, opstr, FGR32, FGR64>, 148 Requires<[IsFP64bit, HasStdEnc]> { 149 let DecoderNamespace = "Mips64"; 150 } 151} 152 153// FP-to-FP conversion instructions. 154multiclass FFR1P_M<bits<6> funct, string opstr, SDNode OpNode> { 155 def _D32 : FFR1P<funct, 17, opstr, AFGR64, AFGR64, OpNode>, 156 Requires<[NotFP64bit, HasStdEnc]>; 157 def _D64 : FFR1P<funct, 17, opstr, FGR64, FGR64, OpNode>, 158 Requires<[IsFP64bit, HasStdEnc]> { 159 let DecoderNamespace = "Mips64"; 160 } 161} 162 163multiclass FFR2P_M<bits<6> funct, string opstr, SDNode OpNode> { 164 def _D32 : FFR2P<funct, 17, opstr, AFGR64, OpNode>, 165 Requires<[NotFP64bit, HasStdEnc]>; 166 def _D64 : FFR2P<funct, 17, opstr, FGR64, OpNode>, 167 Requires<[IsFP64bit, HasStdEnc]> { 168 let DecoderNamespace = "Mips64"; 169 } 170} 171 172// FP madd/msub/nmadd/nmsub instruction classes. 173class FMADDSUB<bits<3> funct, bits<3> fmt, string opstr, 174 SDNode OpNode, RegisterClass RC> : 175 FFMADDSUB<funct, fmt, (outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft), 176 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"), 177 [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))]>; 178 179class FNMADDSUB<bits<3> funct, bits<3> fmt, string opstr, 180 SDNode OpNode, RegisterClass RC> : 181 FFMADDSUB<funct, fmt, (outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft), 182 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"), 183 [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))]>; 184 185//===----------------------------------------------------------------------===// 186// Floating Point Instructions 187//===----------------------------------------------------------------------===// 188def ROUND_W_S : FFR1<0xc, 16, "round.w.s", FGR32, FGR32>; 189def TRUNC_W_S : FFR1<0xd, 16, "trunc.w.s", FGR32, FGR32>; 190def CEIL_W_S : FFR1<0xe, 16, "ceil.w.s", FGR32, FGR32>; 191def FLOOR_W_S : FFR1<0xf, 16, "floor.w.s", FGR32, FGR32>; 192def CVT_W_S : FFR1<0x24, 16, "cvt.w.s", FGR32, FGR32>, NeverHasSideEffects; 193 194defm ROUND_W : FFR1_W_M<0xc, "round.w.d">; 195defm TRUNC_W : FFR1_W_M<0xd, "trunc.w.d">; 196defm CEIL_W : FFR1_W_M<0xe, "ceil.w.d">; 197defm FLOOR_W : FFR1_W_M<0xf, "floor.w.d">; 198defm CVT_W : FFR1_W_M<0x24, "cvt.w.d">, NeverHasSideEffects; 199 200let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in { 201 def ROUND_L_S : FFR1<0x8, 16, "round.l.s", FGR64, FGR32>; 202 def ROUND_L_D64 : FFR1<0x8, 17, "round.l.d", FGR64, FGR64>; 203 def TRUNC_L_S : FFR1<0x9, 16, "trunc.l.s", FGR64, FGR32>; 204 def TRUNC_L_D64 : FFR1<0x9, 17, "trunc.l.d", FGR64, FGR64>; 205 def CEIL_L_S : FFR1<0xa, 16, "ceil.l.s", FGR64, FGR32>; 206 def CEIL_L_D64 : FFR1<0xa, 17, "ceil.l.d", FGR64, FGR64>; 207 def FLOOR_L_S : FFR1<0xb, 16, "floor.l.s", FGR64, FGR32>; 208 def FLOOR_L_D64 : FFR1<0xb, 17, "floor.l.d", FGR64, FGR64>; 209} 210 211def CVT_S_W : FFR1<0x20, 20, "cvt.s.w", FGR32, FGR32>, NeverHasSideEffects; 212def CVT_L_S : FFR1<0x25, 16, "cvt.l.s", FGR64, FGR32>, NeverHasSideEffects; 213def CVT_L_D64: FFR1<0x25, 17, "cvt.l.d", FGR64, FGR64>, NeverHasSideEffects; 214 215let Predicates = [NotFP64bit, HasStdEnc], neverHasSideEffects = 1 in { 216 def CVT_S_D32 : FFR1<0x20, 17, "cvt.s.d", FGR32, AFGR64>; 217 def CVT_D32_W : FFR1<0x21, 20, "cvt.d.w", AFGR64, FGR32>; 218 def CVT_D32_S : FFR1<0x21, 16, "cvt.d.s", AFGR64, FGR32>; 219} 220 221let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64", 222 neverHasSideEffects = 1 in { 223 def CVT_S_D64 : FFR1<0x20, 17, "cvt.s.d", FGR32, FGR64>; 224 def CVT_S_L : FFR1<0x20, 21, "cvt.s.l", FGR32, FGR64>; 225 def CVT_D64_W : FFR1<0x21, 20, "cvt.d.w", FGR64, FGR32>; 226 def CVT_D64_S : FFR1<0x21, 16, "cvt.d.s", FGR64, FGR32>; 227 def CVT_D64_L : FFR1<0x21, 21, "cvt.d.l", FGR64, FGR64>; 228} 229 230let Predicates = [NoNaNsFPMath, HasStdEnc] in { 231 def FABS_S : FFR1P<0x5, 16, "abs.s", FGR32, FGR32, fabs>; 232 def FNEG_S : FFR1P<0x7, 16, "neg.s", FGR32, FGR32, fneg>; 233 defm FABS : FFR1P_M<0x5, "abs.d", fabs>; 234 defm FNEG : FFR1P_M<0x7, "neg.d", fneg>; 235} 236 237def FSQRT_S : FFR1P<0x4, 16, "sqrt.s", FGR32, FGR32, fsqrt>; 238defm FSQRT : FFR1P_M<0x4, "sqrt.d", fsqrt>; 239 240// The odd-numbered registers are only referenced when doing loads, 241// stores, and moves between floating-point and integer registers. 242// When defining instructions, we reference all 32-bit registers, 243// regardless of register aliasing. 244 245class FFRGPR<bits<5> _fmt, dag outs, dag ins, string asmstr, list<dag> pattern>: 246 FFR<0x11, 0x0, _fmt, outs, ins, asmstr, pattern> { 247 bits<5> rt; 248 let ft = rt; 249 let fd = 0; 250} 251 252/// Move Control Registers From/To CPU Registers 253def CFC1 : FFRGPR<0x2, (outs CPURegs:$rt), (ins CCR:$fs), 254 "cfc1\t$rt, $fs", []>; 255 256def CTC1 : FFRGPR<0x6, (outs CCR:$fs), (ins CPURegs:$rt), 257 "ctc1\t$rt, $fs", []>; 258 259def MFC1 : FFRGPR<0x00, (outs CPURegs:$rt), (ins FGR32:$fs), 260 "mfc1\t$rt, $fs", 261 [(set CPURegs:$rt, (bitconvert FGR32:$fs))]>; 262 263def MTC1 : FFRGPR<0x04, (outs FGR32:$fs), (ins CPURegs:$rt), 264 "mtc1\t$rt, $fs", 265 [(set FGR32:$fs, (bitconvert CPURegs:$rt))]>; 266 267def DMFC1 : FFRGPR<0x01, (outs CPU64Regs:$rt), (ins FGR64:$fs), 268 "dmfc1\t$rt, $fs", 269 [(set CPU64Regs:$rt, (bitconvert FGR64:$fs))]>; 270 271def DMTC1 : FFRGPR<0x05, (outs FGR64:$fs), (ins CPU64Regs:$rt), 272 "dmtc1\t$rt, $fs", 273 [(set FGR64:$fs, (bitconvert CPU64Regs:$rt))]>; 274 275def FMOV_S : FFR1<0x6, 16, "mov.s", FGR32, FGR32>; 276def FMOV_D32 : FFR1<0x6, 17, "mov.d", AFGR64, AFGR64>, 277 Requires<[NotFP64bit, HasStdEnc]>; 278def FMOV_D64 : FFR1<0x6, 17, "mov.d", FGR64, FGR64>, 279 Requires<[IsFP64bit, HasStdEnc]> { 280 let DecoderNamespace = "Mips64"; 281} 282 283/// Floating Point Memory Instructions 284let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in { 285 def LWC1_P8 : FPLoad<0x31, "lwc1", FGR32, mem64>; 286 def SWC1_P8 : FPStore<0x39, "swc1", FGR32, mem64>; 287 def LDC164_P8 : FPLoad<0x35, "ldc1", FGR64, mem64> { 288 let isCodeGenOnly =1; 289 } 290 def SDC164_P8 : FPStore<0x3d, "sdc1", FGR64, mem64> { 291 let isCodeGenOnly =1; 292 } 293} 294 295let Predicates = [NotN64, HasStdEnc] in { 296 def LWC1 : FPLoad<0x31, "lwc1", FGR32, mem>; 297 def SWC1 : FPStore<0x39, "swc1", FGR32, mem>; 298} 299 300let Predicates = [NotN64, HasMips64, HasStdEnc], 301 DecoderNamespace = "Mips64" in { 302 def LDC164 : FPLoad<0x35, "ldc1", FGR64, mem>; 303 def SDC164 : FPStore<0x3d, "sdc1", FGR64, mem>; 304} 305 306let Predicates = [NotN64, NotMips64, HasStdEnc] in { 307 def LDC1 : FPLoad<0x35, "ldc1", AFGR64, mem>; 308 def SDC1 : FPStore<0x3d, "sdc1", AFGR64, mem>; 309} 310 311// Indexed loads and stores. 312let Predicates = [HasFPIdx, HasStdEnc] in { 313 def LWXC1 : FPIdxLoad<0x0, "lwxc1", FGR32, CPURegs, load>; 314 def SWXC1 : FPIdxStore<0x8, "swxc1", FGR32, CPURegs, store>; 315} 316 317let Predicates = [HasMips32r2, NotMips64, HasStdEnc] in { 318 def LDXC1 : FPIdxLoad<0x1, "ldxc1", AFGR64, CPURegs, load>; 319 def SDXC1 : FPIdxStore<0x9, "sdxc1", AFGR64, CPURegs, store>; 320} 321 322let Predicates = [HasMips64, NotN64, HasStdEnc], DecoderNamespace="Mips64" in { 323 def LDXC164 : FPIdxLoad<0x1, "ldxc1", FGR64, CPURegs, load>; 324 def SDXC164 : FPIdxStore<0x9, "sdxc1", FGR64, CPURegs, store>; 325} 326 327// n64 328let Predicates = [IsN64, HasStdEnc], isCodeGenOnly=1 in { 329 def LWXC1_P8 : FPIdxLoad<0x0, "lwxc1", FGR32, CPU64Regs, load>; 330 def LDXC164_P8 : FPIdxLoad<0x1, "ldxc1", FGR64, CPU64Regs, load>; 331 def SWXC1_P8 : FPIdxStore<0x8, "swxc1", FGR32, CPU64Regs, store>; 332 def SDXC164_P8 : FPIdxStore<0x9, "sdxc1", FGR64, CPU64Regs, store>; 333} 334 335// Load/store doubleword indexed unaligned. 336let Predicates = [NotMips64, HasStdEnc] in { 337 def LUXC1 : FPIdxLoad<0x5, "luxc1", AFGR64, CPURegs>; 338 def SUXC1 : FPIdxStore<0xd, "suxc1", AFGR64, CPURegs>; 339} 340 341let Predicates = [HasMips64, HasStdEnc], 342 DecoderNamespace="Mips64" in { 343 def LUXC164 : FPIdxLoad<0x5, "luxc1", FGR64, CPURegs>; 344 def SUXC164 : FPIdxStore<0xd, "suxc1", FGR64, CPURegs>; 345} 346 347/// Floating-point Aritmetic 348def FADD_S : FFR2P<0x00, 16, "add.s", FGR32, fadd>, IsCommutable; 349defm FADD : FFR2P_M<0x00, "add.d", fadd>, IsCommutable; 350def FDIV_S : FFR2P<0x03, 16, "div.s", FGR32, fdiv>; 351defm FDIV : FFR2P_M<0x03, "div.d", fdiv>; 352def FMUL_S : FFR2P<0x02, 16, "mul.s", FGR32, fmul>, IsCommutable; 353defm FMUL : FFR2P_M<0x02, "mul.d", fmul>, IsCommutable; 354def FSUB_S : FFR2P<0x01, 16, "sub.s", FGR32, fsub>; 355defm FSUB : FFR2P_M<0x01, "sub.d", fsub>; 356 357let Predicates = [HasMips32r2, HasStdEnc] in { 358 def MADD_S : FMADDSUB<0x4, 0, "madd.s", fadd, FGR32>; 359 def MSUB_S : FMADDSUB<0x5, 0, "msub.s", fsub, FGR32>; 360} 361 362let Predicates = [HasMips32r2, NoNaNsFPMath, HasStdEnc] in { 363 def NMADD_S : FNMADDSUB<0x6, 0, "nmadd.s", fadd, FGR32>; 364 def NMSUB_S : FNMADDSUB<0x7, 0, "nmsub.s", fsub, FGR32>; 365} 366 367let Predicates = [HasMips32r2, NotFP64bit, HasStdEnc] in { 368 def MADD_D32 : FMADDSUB<0x4, 1, "madd.d", fadd, AFGR64>; 369 def MSUB_D32 : FMADDSUB<0x5, 1, "msub.d", fsub, AFGR64>; 370} 371 372let Predicates = [HasMips32r2, NotFP64bit, NoNaNsFPMath, HasStdEnc] in { 373 def NMADD_D32 : FNMADDSUB<0x6, 1, "nmadd.d", fadd, AFGR64>; 374 def NMSUB_D32 : FNMADDSUB<0x7, 1, "nmsub.d", fsub, AFGR64>; 375} 376 377let Predicates = [HasMips32r2, IsFP64bit, HasStdEnc], isCodeGenOnly=1 in { 378 def MADD_D64 : FMADDSUB<0x4, 1, "madd.d", fadd, FGR64>; 379 def MSUB_D64 : FMADDSUB<0x5, 1, "msub.d", fsub, FGR64>; 380} 381 382let Predicates = [HasMips32r2, IsFP64bit, NoNaNsFPMath, HasStdEnc], 383 isCodeGenOnly=1 in { 384 def NMADD_D64 : FNMADDSUB<0x6, 1, "nmadd.d", fadd, FGR64>; 385 def NMSUB_D64 : FNMADDSUB<0x7, 1, "nmsub.d", fsub, FGR64>; 386} 387 388//===----------------------------------------------------------------------===// 389// Floating Point Branch Codes 390//===----------------------------------------------------------------------===// 391// Mips branch codes. These correspond to condcode in MipsInstrInfo.h. 392// They must be kept in synch. 393def MIPS_BRANCH_F : PatLeaf<(i32 0)>; 394def MIPS_BRANCH_T : PatLeaf<(i32 1)>; 395 396/// Floating Point Branch of False/True (Likely) 397let isBranch=1, isTerminator=1, hasDelaySlot=1, base=0x8, Uses=[FCR31] in 398 class FBRANCH<bits<1> nd, bits<1> tf, PatLeaf op, string asmstr> : 399 FFI<0x11, (outs), (ins brtarget:$dst), !strconcat(asmstr, "\t$dst"), 400 [(MipsFPBrcond op, bb:$dst)]> { 401 let Inst{20-18} = 0; 402 let Inst{17} = nd; 403 let Inst{16} = tf; 404} 405 406let DecoderMethod = "DecodeBC1" in { 407def BC1F : FBRANCH<0, 0, MIPS_BRANCH_F, "bc1f">; 408def BC1T : FBRANCH<0, 1, MIPS_BRANCH_T, "bc1t">; 409} 410//===----------------------------------------------------------------------===// 411// Floating Point Flag Conditions 412//===----------------------------------------------------------------------===// 413// Mips condition codes. They must correspond to condcode in MipsInstrInfo.h. 414// They must be kept in synch. 415def MIPS_FCOND_F : PatLeaf<(i32 0)>; 416def MIPS_FCOND_UN : PatLeaf<(i32 1)>; 417def MIPS_FCOND_OEQ : PatLeaf<(i32 2)>; 418def MIPS_FCOND_UEQ : PatLeaf<(i32 3)>; 419def MIPS_FCOND_OLT : PatLeaf<(i32 4)>; 420def MIPS_FCOND_ULT : PatLeaf<(i32 5)>; 421def MIPS_FCOND_OLE : PatLeaf<(i32 6)>; 422def MIPS_FCOND_ULE : PatLeaf<(i32 7)>; 423def MIPS_FCOND_SF : PatLeaf<(i32 8)>; 424def MIPS_FCOND_NGLE : PatLeaf<(i32 9)>; 425def MIPS_FCOND_SEQ : PatLeaf<(i32 10)>; 426def MIPS_FCOND_NGL : PatLeaf<(i32 11)>; 427def MIPS_FCOND_LT : PatLeaf<(i32 12)>; 428def MIPS_FCOND_NGE : PatLeaf<(i32 13)>; 429def MIPS_FCOND_LE : PatLeaf<(i32 14)>; 430def MIPS_FCOND_NGT : PatLeaf<(i32 15)>; 431 432class FCMP<bits<5> fmt, RegisterClass RC, string typestr> : 433 FCC<fmt, (outs), (ins RC:$fs, RC:$ft, condcode:$cc), 434 !strconcat("c.$cc.", typestr, "\t$fs, $ft"), 435 [(MipsFPCmp RC:$fs, RC:$ft, imm:$cc)]>; 436 437/// Floating Point Compare 438let Defs=[FCR31] in { 439 def FCMP_S32 : FCMP<0x10, FGR32, "s">; 440 def FCMP_D32 : FCMP<0x11, AFGR64, "d">, 441 Requires<[NotFP64bit, HasStdEnc]>; 442 def FCMP_D64 : FCMP<0x11, FGR64, "d">, 443 Requires<[IsFP64bit, HasStdEnc]> { 444 let DecoderNamespace = "Mips64"; 445 } 446} 447 448//===----------------------------------------------------------------------===// 449// Floating Point Pseudo-Instructions 450//===----------------------------------------------------------------------===// 451def MOVCCRToCCR : PseudoSE<(outs CCR:$dst), (ins CCR:$src), 452 "# MOVCCRToCCR", []>; 453 454// This pseudo instr gets expanded into 2 mtc1 instrs after register 455// allocation. 456def BuildPairF64 : 457 PseudoSE<(outs AFGR64:$dst), 458 (ins CPURegs:$lo, CPURegs:$hi), "", 459 [(set AFGR64:$dst, (MipsBuildPairF64 CPURegs:$lo, CPURegs:$hi))]>; 460 461// This pseudo instr gets expanded into 2 mfc1 instrs after register 462// allocation. 463// if n is 0, lower part of src is extracted. 464// if n is 1, higher part of src is extracted. 465def ExtractElementF64 : 466 PseudoSE<(outs CPURegs:$dst), (ins AFGR64:$src, i32imm:$n), "", 467 [(set CPURegs:$dst, (MipsExtractElementF64 AFGR64:$src, imm:$n))]>; 468 469//===----------------------------------------------------------------------===// 470// Floating Point Patterns 471//===----------------------------------------------------------------------===// 472def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>; 473def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>; 474 475def : MipsPat<(f32 (sint_to_fp CPURegs:$src)), (CVT_S_W (MTC1 CPURegs:$src))>; 476def : MipsPat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S FGR32:$src))>; 477 478let Predicates = [NotFP64bit, HasStdEnc] in { 479 def : MipsPat<(f64 (sint_to_fp CPURegs:$src)), 480 (CVT_D32_W (MTC1 CPURegs:$src))>; 481 def : MipsPat<(i32 (fp_to_sint AFGR64:$src)), 482 (MFC1 (TRUNC_W_D32 AFGR64:$src))>; 483 def : MipsPat<(f32 (fround AFGR64:$src)), (CVT_S_D32 AFGR64:$src)>; 484 def : MipsPat<(f64 (fextend FGR32:$src)), (CVT_D32_S FGR32:$src)>; 485} 486 487let Predicates = [IsFP64bit, HasStdEnc] in { 488 def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>; 489 def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>; 490 491 def : MipsPat<(f64 (sint_to_fp CPURegs:$src)), 492 (CVT_D64_W (MTC1 CPURegs:$src))>; 493 def : MipsPat<(f32 (sint_to_fp CPU64Regs:$src)), 494 (CVT_S_L (DMTC1 CPU64Regs:$src))>; 495 def : MipsPat<(f64 (sint_to_fp CPU64Regs:$src)), 496 (CVT_D64_L (DMTC1 CPU64Regs:$src))>; 497 498 def : MipsPat<(i32 (fp_to_sint FGR64:$src)), 499 (MFC1 (TRUNC_W_D64 FGR64:$src))>; 500 def : MipsPat<(i64 (fp_to_sint FGR32:$src)), (DMFC1 (TRUNC_L_S FGR32:$src))>; 501 def : MipsPat<(i64 (fp_to_sint FGR64:$src)), 502 (DMFC1 (TRUNC_L_D64 FGR64:$src))>; 503 504 def : MipsPat<(f32 (fround FGR64:$src)), (CVT_S_D64 FGR64:$src)>; 505 def : MipsPat<(f64 (fextend FGR32:$src)), (CVT_D64_S FGR32:$src)>; 506} 507