MipsInstrFPU.td revision 1c88a8d978e5cbcbd270f7a742bfe690ed798e0e
1//===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Mips FPU instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Floating Point Instructions 16// ------------------------ 17// * 64bit fp: 18// - 32 64-bit registers (default mode) 19// - 16 even 32-bit registers (32-bit compatible mode) for 20// single and double access. 21// * 32bit fp: 22// - 16 even 32-bit registers - single and double (aliased) 23// - 32 32-bit registers (within single-only mode) 24//===----------------------------------------------------------------------===// 25 26// Floating Point Compare and Branch 27def SDT_MipsFPBrcond : SDTypeProfile<0, 2, [SDTCisInt<0>, 28 SDTCisVT<1, OtherVT>]>; 29def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>, 30 SDTCisVT<2, i32>]>; 31def SDT_MipsCMovFP : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, 32 SDTCisSameAs<1, 2>]>; 33def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, 34 SDTCisVT<1, i32>, 35 SDTCisSameAs<1, 2>]>; 36def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, 37 SDTCisVT<1, f64>, 38 SDTCisVT<2, i32>]>; 39 40def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>; 41def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>; 42def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>; 43def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond, 44 [SDNPHasChain, SDNPOptInGlue]>; 45def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>; 46def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64", 47 SDT_MipsExtractElementF64>; 48 49// Operand for printing out a condition code. 50let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in 51 def condcode : Operand<i32>; 52 53//===----------------------------------------------------------------------===// 54// Feature predicates. 55//===----------------------------------------------------------------------===// 56 57def IsFP64bit : Predicate<"Subtarget.isFP64bit()">, 58 AssemblerPredicate<"FeatureFP64Bit">; 59def NotFP64bit : Predicate<"!Subtarget.isFP64bit()">, 60 AssemblerPredicate<"!FeatureFP64Bit">; 61def IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">, 62 AssemblerPredicate<"FeatureSingleFloat">; 63def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">, 64 AssemblerPredicate<"!FeatureSingleFloat">; 65 66// FP immediate patterns. 67def fpimm0 : PatLeaf<(fpimm), [{ 68 return N->isExactlyValue(+0.0); 69}]>; 70 71def fpimm0neg : PatLeaf<(fpimm), [{ 72 return N->isExactlyValue(-0.0); 73}]>; 74 75//===----------------------------------------------------------------------===// 76// Instruction Class Templates 77// 78// A set of multiclasses is used to address the register usage. 79// 80// S32 - single precision in 16 32bit even fp registers 81// single precision in 32 32bit fp registers in SingleOnly mode 82// S64 - single precision in 32 64bit fp registers (In64BitMode) 83// D32 - double precision in 16 32bit even fp registers 84// D64 - double precision in 32 64bit fp registers (In64BitMode) 85// 86// Only S32 and D32 are supported right now. 87//===----------------------------------------------------------------------===// 88 89// FP load. 90let DecoderMethod = "DecodeFMem" in { 91class FPLoad<bits<6> op, string opstr, RegisterClass RC, Operand MemOpnd>: 92 FMem<op, (outs RC:$ft), (ins MemOpnd:$addr), 93 !strconcat(opstr, "\t$ft, $addr"), [(set RC:$ft, (load addr:$addr))], 94 IILoad>; 95 96// FP store. 97class FPStore<bits<6> op, string opstr, RegisterClass RC, Operand MemOpnd>: 98 FMem<op, (outs), (ins RC:$ft, MemOpnd:$addr), 99 !strconcat(opstr, "\t$ft, $addr"), [(store RC:$ft, addr:$addr)], 100 IIStore>; 101} 102// FP indexed load. 103class FPIdxLoad<bits<6> funct, string opstr, RegisterClass DRC, 104 RegisterClass PRC, SDPatternOperator FOp = null_frag>: 105 FFMemIdx<funct, (outs DRC:$fd), (ins PRC:$base, PRC:$index), 106 !strconcat(opstr, "\t$fd, ${index}(${base})"), 107 [(set DRC:$fd, (FOp (add PRC:$base, PRC:$index)))]> { 108 let fs = 0; 109} 110 111// FP indexed store. 112class FPIdxStore<bits<6> funct, string opstr, RegisterClass DRC, 113 RegisterClass PRC, SDPatternOperator FOp= null_frag>: 114 FFMemIdx<funct, (outs), (ins DRC:$fs, PRC:$base, PRC:$index), 115 !strconcat(opstr, "\t$fs, ${index}(${base})"), 116 [(FOp DRC:$fs, (add PRC:$base, PRC:$index))]> { 117 let fd = 0; 118} 119 120// Instructions that convert an FP value to 32-bit fixed point. 121multiclass FFR1_W_M<bits<6> funct, string opstr> { 122 def _D32 : FFR1<funct, 17, opstr, FGR32, AFGR64>, 123 Requires<[NotFP64bit, HasStdEnc]>; 124 def _D64 : FFR1<funct, 17, opstr, FGR32, FGR64>, 125 Requires<[IsFP64bit, HasStdEnc]> { 126 let DecoderNamespace = "Mips64"; 127 } 128} 129 130// FP-to-FP conversion instructions. 131multiclass FFR1P_M<bits<6> funct, string opstr, SDNode OpNode> { 132 def _D32 : FFR1P<funct, 17, opstr, AFGR64, AFGR64, OpNode>, 133 Requires<[NotFP64bit, HasStdEnc]>; 134 def _D64 : FFR1P<funct, 17, opstr, FGR64, FGR64, OpNode>, 135 Requires<[IsFP64bit, HasStdEnc]> { 136 let DecoderNamespace = "Mips64"; 137 } 138} 139 140multiclass FFR2P_M<bits<6> funct, string opstr, SDNode OpNode, bit isComm = 0> { 141 let isCommutable = isComm in { 142 def _D32 : FFR2P<funct, 17, opstr, AFGR64, OpNode>, 143 Requires<[NotFP64bit, HasStdEnc]>; 144 def _D64 : FFR2P<funct, 17, opstr, FGR64, OpNode>, 145 Requires<[IsFP64bit, HasStdEnc]> { 146 let DecoderNamespace = "Mips64"; 147 } 148} 149} 150 151// FP madd/msub/nmadd/nmsub instruction classes. 152class FMADDSUB<bits<3> funct, bits<3> fmt, string opstr, 153 SDNode OpNode, RegisterClass RC> : 154 FFMADDSUB<funct, fmt, (outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft), 155 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"), 156 [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))]>; 157 158class FNMADDSUB<bits<3> funct, bits<3> fmt, string opstr, 159 SDNode OpNode, RegisterClass RC> : 160 FFMADDSUB<funct, fmt, (outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft), 161 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"), 162 [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))]>; 163 164//===----------------------------------------------------------------------===// 165// Floating Point Instructions 166//===----------------------------------------------------------------------===// 167def ROUND_W_S : FFR1<0xc, 16, "round.w.s", FGR32, FGR32>; 168def TRUNC_W_S : FFR1<0xd, 16, "trunc.w.s", FGR32, FGR32>; 169def CEIL_W_S : FFR1<0xe, 16, "ceil.w.s", FGR32, FGR32>; 170def FLOOR_W_S : FFR1<0xf, 16, "floor.w.s", FGR32, FGR32>; 171def CVT_W_S : FFR1<0x24, 16, "cvt.w.s", FGR32, FGR32>, NeverHasSideEffects; 172 173defm ROUND_W : FFR1_W_M<0xc, "round.w.d">; 174defm TRUNC_W : FFR1_W_M<0xd, "trunc.w.d">; 175defm CEIL_W : FFR1_W_M<0xe, "ceil.w.d">; 176defm FLOOR_W : FFR1_W_M<0xf, "floor.w.d">; 177defm CVT_W : FFR1_W_M<0x24, "cvt.w.d">, NeverHasSideEffects; 178 179let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in { 180 def ROUND_L_S : FFR1<0x8, 16, "round.l.s", FGR64, FGR32>; 181 def ROUND_L_D64 : FFR1<0x8, 17, "round.l.d", FGR64, FGR64>; 182 def TRUNC_L_S : FFR1<0x9, 16, "trunc.l.s", FGR64, FGR32>; 183 def TRUNC_L_D64 : FFR1<0x9, 17, "trunc.l.d", FGR64, FGR64>; 184 def CEIL_L_S : FFR1<0xa, 16, "ceil.l.s", FGR64, FGR32>; 185 def CEIL_L_D64 : FFR1<0xa, 17, "ceil.l.d", FGR64, FGR64>; 186 def FLOOR_L_S : FFR1<0xb, 16, "floor.l.s", FGR64, FGR32>; 187 def FLOOR_L_D64 : FFR1<0xb, 17, "floor.l.d", FGR64, FGR64>; 188} 189 190def CVT_S_W : FFR1<0x20, 20, "cvt.s.w", FGR32, FGR32>, NeverHasSideEffects; 191def CVT_L_S : FFR1<0x25, 16, "cvt.l.s", FGR64, FGR32>, NeverHasSideEffects; 192def CVT_L_D64: FFR1<0x25, 17, "cvt.l.d", FGR64, FGR64>, NeverHasSideEffects; 193 194let Predicates = [NotFP64bit, HasStdEnc], neverHasSideEffects = 1 in { 195 def CVT_S_D32 : FFR1<0x20, 17, "cvt.s.d", FGR32, AFGR64>; 196 def CVT_D32_W : FFR1<0x21, 20, "cvt.d.w", AFGR64, FGR32>; 197 def CVT_D32_S : FFR1<0x21, 16, "cvt.d.s", AFGR64, FGR32>; 198} 199 200let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64", 201 neverHasSideEffects = 1 in { 202 def CVT_S_D64 : FFR1<0x20, 17, "cvt.s.d", FGR32, FGR64>; 203 def CVT_S_L : FFR1<0x20, 21, "cvt.s.l", FGR32, FGR64>; 204 def CVT_D64_W : FFR1<0x21, 20, "cvt.d.w", FGR64, FGR32>; 205 def CVT_D64_S : FFR1<0x21, 16, "cvt.d.s", FGR64, FGR32>; 206 def CVT_D64_L : FFR1<0x21, 21, "cvt.d.l", FGR64, FGR64>; 207} 208 209let Predicates = [NoNaNsFPMath, HasStdEnc] in { 210 def FABS_S : FFR1P<0x5, 16, "abs.s", FGR32, FGR32, fabs>; 211 def FNEG_S : FFR1P<0x7, 16, "neg.s", FGR32, FGR32, fneg>; 212 defm FABS : FFR1P_M<0x5, "abs.d", fabs>; 213 defm FNEG : FFR1P_M<0x7, "neg.d", fneg>; 214} 215 216def FSQRT_S : FFR1P<0x4, 16, "sqrt.s", FGR32, FGR32, fsqrt>; 217defm FSQRT : FFR1P_M<0x4, "sqrt.d", fsqrt>; 218 219// The odd-numbered registers are only referenced when doing loads, 220// stores, and moves between floating-point and integer registers. 221// When defining instructions, we reference all 32-bit registers, 222// regardless of register aliasing. 223 224class FFRGPR<bits<5> _fmt, dag outs, dag ins, string asmstr, list<dag> pattern>: 225 FFR<0x11, 0x0, _fmt, outs, ins, asmstr, pattern> { 226 bits<5> rt; 227 let ft = rt; 228 let fd = 0; 229} 230 231/// Move Control Registers From/To CPU Registers 232def CFC1 : FFRGPR<0x2, (outs CPURegs:$rt), (ins CCR:$fs), 233 "cfc1\t$rt, $fs", []>; 234 235def CTC1 : FFRGPR<0x6, (outs CCR:$fs), (ins CPURegs:$rt), 236 "ctc1\t$rt, $fs", []>; 237 238def MFC1 : FFRGPR<0x00, (outs CPURegs:$rt), (ins FGR32:$fs), 239 "mfc1\t$rt, $fs", 240 [(set CPURegs:$rt, (bitconvert FGR32:$fs))]>; 241 242def MTC1 : FFRGPR<0x04, (outs FGR32:$fs), (ins CPURegs:$rt), 243 "mtc1\t$rt, $fs", 244 [(set FGR32:$fs, (bitconvert CPURegs:$rt))]>; 245 246def DMFC1 : FFRGPR<0x01, (outs CPU64Regs:$rt), (ins FGR64:$fs), 247 "dmfc1\t$rt, $fs", 248 [(set CPU64Regs:$rt, (bitconvert FGR64:$fs))]>; 249 250def DMTC1 : FFRGPR<0x05, (outs FGR64:$fs), (ins CPU64Regs:$rt), 251 "dmtc1\t$rt, $fs", 252 [(set FGR64:$fs, (bitconvert CPU64Regs:$rt))]>; 253 254def FMOV_S : FFR1<0x6, 16, "mov.s", FGR32, FGR32>; 255def FMOV_D32 : FFR1<0x6, 17, "mov.d", AFGR64, AFGR64>, 256 Requires<[NotFP64bit, HasStdEnc]>; 257def FMOV_D64 : FFR1<0x6, 17, "mov.d", FGR64, FGR64>, 258 Requires<[IsFP64bit, HasStdEnc]> { 259 let DecoderNamespace = "Mips64"; 260} 261 262/// Floating Point Memory Instructions 263let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in { 264 def LWC1_P8 : FPLoad<0x31, "lwc1", FGR32, mem64>; 265 def SWC1_P8 : FPStore<0x39, "swc1", FGR32, mem64>; 266 def LDC164_P8 : FPLoad<0x35, "ldc1", FGR64, mem64> { 267 let isCodeGenOnly =1; 268 } 269 def SDC164_P8 : FPStore<0x3d, "sdc1", FGR64, mem64> { 270 let isCodeGenOnly =1; 271 } 272} 273 274let Predicates = [NotN64, HasStdEnc] in { 275 def LWC1 : FPLoad<0x31, "lwc1", FGR32, mem>; 276 def SWC1 : FPStore<0x39, "swc1", FGR32, mem>; 277} 278 279let Predicates = [NotN64, HasMips64, HasStdEnc], 280 DecoderNamespace = "Mips64" in { 281 def LDC164 : FPLoad<0x35, "ldc1", FGR64, mem>; 282 def SDC164 : FPStore<0x3d, "sdc1", FGR64, mem>; 283} 284 285let Predicates = [NotN64, NotMips64, HasStdEnc] in { 286 def LDC1 : FPLoad<0x35, "ldc1", AFGR64, mem>; 287 def SDC1 : FPStore<0x3d, "sdc1", AFGR64, mem>; 288} 289 290// Indexed loads and stores. 291let Predicates = [HasFPIdx, HasStdEnc] in { 292 def LWXC1 : FPIdxLoad<0x0, "lwxc1", FGR32, CPURegs, load>; 293 def SWXC1 : FPIdxStore<0x8, "swxc1", FGR32, CPURegs, store>; 294} 295 296let Predicates = [HasMips32r2, NotMips64, HasStdEnc] in { 297 def LDXC1 : FPIdxLoad<0x1, "ldxc1", AFGR64, CPURegs, load>; 298 def SDXC1 : FPIdxStore<0x9, "sdxc1", AFGR64, CPURegs, store>; 299} 300 301let Predicates = [HasMips64, NotN64, HasStdEnc], DecoderNamespace="Mips64" in { 302 def LDXC164 : FPIdxLoad<0x1, "ldxc1", FGR64, CPURegs, load>; 303 def SDXC164 : FPIdxStore<0x9, "sdxc1", FGR64, CPURegs, store>; 304} 305 306// n64 307let Predicates = [IsN64, HasStdEnc], isCodeGenOnly=1 in { 308 def LWXC1_P8 : FPIdxLoad<0x0, "lwxc1", FGR32, CPU64Regs, load>; 309 def LDXC164_P8 : FPIdxLoad<0x1, "ldxc1", FGR64, CPU64Regs, load>; 310 def SWXC1_P8 : FPIdxStore<0x8, "swxc1", FGR32, CPU64Regs, store>; 311 def SDXC164_P8 : FPIdxStore<0x9, "sdxc1", FGR64, CPU64Regs, store>; 312} 313 314// Load/store doubleword indexed unaligned. 315let Predicates = [NotMips64, HasStdEnc] in { 316 def LUXC1 : FPIdxLoad<0x5, "luxc1", AFGR64, CPURegs>; 317 def SUXC1 : FPIdxStore<0xd, "suxc1", AFGR64, CPURegs>; 318} 319 320let Predicates = [HasMips64, HasStdEnc], 321 DecoderNamespace="Mips64" in { 322 def LUXC164 : FPIdxLoad<0x5, "luxc1", FGR64, CPURegs>; 323 def SUXC164 : FPIdxStore<0xd, "suxc1", FGR64, CPURegs>; 324} 325 326/// Floating-point Aritmetic 327def FADD_S : FFR2P<0x00, 16, "add.s", FGR32, fadd>, IsCommutable; 328defm FADD : FFR2P_M<0x00, "add.d", fadd, 1>; 329def FDIV_S : FFR2P<0x03, 16, "div.s", FGR32, fdiv>; 330defm FDIV : FFR2P_M<0x03, "div.d", fdiv>; 331def FMUL_S : FFR2P<0x02, 16, "mul.s", FGR32, fmul>, IsCommutable; 332defm FMUL : FFR2P_M<0x02, "mul.d", fmul, 1>; 333def FSUB_S : FFR2P<0x01, 16, "sub.s", FGR32, fsub>; 334defm FSUB : FFR2P_M<0x01, "sub.d", fsub>; 335 336let Predicates = [HasMips32r2, HasStdEnc] in { 337 def MADD_S : FMADDSUB<0x4, 0, "madd.s", fadd, FGR32>; 338 def MSUB_S : FMADDSUB<0x5, 0, "msub.s", fsub, FGR32>; 339} 340 341let Predicates = [HasMips32r2, NoNaNsFPMath, HasStdEnc] in { 342 def NMADD_S : FNMADDSUB<0x6, 0, "nmadd.s", fadd, FGR32>; 343 def NMSUB_S : FNMADDSUB<0x7, 0, "nmsub.s", fsub, FGR32>; 344} 345 346let Predicates = [HasMips32r2, NotFP64bit, HasStdEnc] in { 347 def MADD_D32 : FMADDSUB<0x4, 1, "madd.d", fadd, AFGR64>; 348 def MSUB_D32 : FMADDSUB<0x5, 1, "msub.d", fsub, AFGR64>; 349} 350 351let Predicates = [HasMips32r2, NotFP64bit, NoNaNsFPMath, HasStdEnc] in { 352 def NMADD_D32 : FNMADDSUB<0x6, 1, "nmadd.d", fadd, AFGR64>; 353 def NMSUB_D32 : FNMADDSUB<0x7, 1, "nmsub.d", fsub, AFGR64>; 354} 355 356let Predicates = [HasMips32r2, IsFP64bit, HasStdEnc], isCodeGenOnly=1 in { 357 def MADD_D64 : FMADDSUB<0x4, 1, "madd.d", fadd, FGR64>; 358 def MSUB_D64 : FMADDSUB<0x5, 1, "msub.d", fsub, FGR64>; 359} 360 361let Predicates = [HasMips32r2, IsFP64bit, NoNaNsFPMath, HasStdEnc], 362 isCodeGenOnly=1 in { 363 def NMADD_D64 : FNMADDSUB<0x6, 1, "nmadd.d", fadd, FGR64>; 364 def NMSUB_D64 : FNMADDSUB<0x7, 1, "nmsub.d", fsub, FGR64>; 365} 366 367//===----------------------------------------------------------------------===// 368// Floating Point Branch Codes 369//===----------------------------------------------------------------------===// 370// Mips branch codes. These correspond to condcode in MipsInstrInfo.h. 371// They must be kept in synch. 372def MIPS_BRANCH_F : PatLeaf<(i32 0)>; 373def MIPS_BRANCH_T : PatLeaf<(i32 1)>; 374 375/// Floating Point Branch of False/True (Likely) 376let isBranch=1, isTerminator=1, hasDelaySlot=1, base=0x8, Uses=[FCR31] in 377 class FBRANCH<bits<1> nd, bits<1> tf, PatLeaf op, string asmstr> : 378 FFI<0x11, (outs), (ins brtarget:$dst), !strconcat(asmstr, "\t$dst"), 379 [(MipsFPBrcond op, bb:$dst)]> { 380 let Inst{20-18} = 0; 381 let Inst{17} = nd; 382 let Inst{16} = tf; 383} 384 385let DecoderMethod = "DecodeBC1" in { 386def BC1F : FBRANCH<0, 0, MIPS_BRANCH_F, "bc1f">; 387def BC1T : FBRANCH<0, 1, MIPS_BRANCH_T, "bc1t">; 388} 389//===----------------------------------------------------------------------===// 390// Floating Point Flag Conditions 391//===----------------------------------------------------------------------===// 392// Mips condition codes. They must correspond to condcode in MipsInstrInfo.h. 393// They must be kept in synch. 394def MIPS_FCOND_F : PatLeaf<(i32 0)>; 395def MIPS_FCOND_UN : PatLeaf<(i32 1)>; 396def MIPS_FCOND_OEQ : PatLeaf<(i32 2)>; 397def MIPS_FCOND_UEQ : PatLeaf<(i32 3)>; 398def MIPS_FCOND_OLT : PatLeaf<(i32 4)>; 399def MIPS_FCOND_ULT : PatLeaf<(i32 5)>; 400def MIPS_FCOND_OLE : PatLeaf<(i32 6)>; 401def MIPS_FCOND_ULE : PatLeaf<(i32 7)>; 402def MIPS_FCOND_SF : PatLeaf<(i32 8)>; 403def MIPS_FCOND_NGLE : PatLeaf<(i32 9)>; 404def MIPS_FCOND_SEQ : PatLeaf<(i32 10)>; 405def MIPS_FCOND_NGL : PatLeaf<(i32 11)>; 406def MIPS_FCOND_LT : PatLeaf<(i32 12)>; 407def MIPS_FCOND_NGE : PatLeaf<(i32 13)>; 408def MIPS_FCOND_LE : PatLeaf<(i32 14)>; 409def MIPS_FCOND_NGT : PatLeaf<(i32 15)>; 410 411class FCMP<bits<5> fmt, RegisterClass RC, string typestr> : 412 FCC<fmt, (outs), (ins RC:$fs, RC:$ft, condcode:$cc), 413 !strconcat("c.$cc.", typestr, "\t$fs, $ft"), 414 [(MipsFPCmp RC:$fs, RC:$ft, imm:$cc)]>; 415 416/// Floating Point Compare 417let Defs=[FCR31] in { 418 def FCMP_S32 : FCMP<0x10, FGR32, "s">; 419 def FCMP_D32 : FCMP<0x11, AFGR64, "d">, 420 Requires<[NotFP64bit, HasStdEnc]>; 421 def FCMP_D64 : FCMP<0x11, FGR64, "d">, 422 Requires<[IsFP64bit, HasStdEnc]> { 423 let DecoderNamespace = "Mips64"; 424 } 425} 426 427//===----------------------------------------------------------------------===// 428// Floating Point Pseudo-Instructions 429//===----------------------------------------------------------------------===// 430def MOVCCRToCCR : PseudoSE<(outs CCR:$dst), (ins CCR:$src), 431 "# MOVCCRToCCR", []>; 432 433// This pseudo instr gets expanded into 2 mtc1 instrs after register 434// allocation. 435def BuildPairF64 : 436 PseudoSE<(outs AFGR64:$dst), 437 (ins CPURegs:$lo, CPURegs:$hi), "", 438 [(set AFGR64:$dst, (MipsBuildPairF64 CPURegs:$lo, CPURegs:$hi))]>; 439 440// This pseudo instr gets expanded into 2 mfc1 instrs after register 441// allocation. 442// if n is 0, lower part of src is extracted. 443// if n is 1, higher part of src is extracted. 444def ExtractElementF64 : 445 PseudoSE<(outs CPURegs:$dst), (ins AFGR64:$src, i32imm:$n), "", 446 [(set CPURegs:$dst, (MipsExtractElementF64 AFGR64:$src, imm:$n))]>; 447 448//===----------------------------------------------------------------------===// 449// Floating Point Patterns 450//===----------------------------------------------------------------------===// 451def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>; 452def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>; 453 454def : MipsPat<(f32 (sint_to_fp CPURegs:$src)), (CVT_S_W (MTC1 CPURegs:$src))>; 455def : MipsPat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S FGR32:$src))>; 456 457let Predicates = [NotFP64bit, HasStdEnc] in { 458 def : MipsPat<(f64 (sint_to_fp CPURegs:$src)), 459 (CVT_D32_W (MTC1 CPURegs:$src))>; 460 def : MipsPat<(i32 (fp_to_sint AFGR64:$src)), 461 (MFC1 (TRUNC_W_D32 AFGR64:$src))>; 462 def : MipsPat<(f32 (fround AFGR64:$src)), (CVT_S_D32 AFGR64:$src)>; 463 def : MipsPat<(f64 (fextend FGR32:$src)), (CVT_D32_S FGR32:$src)>; 464} 465 466let Predicates = [IsFP64bit, HasStdEnc] in { 467 def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>; 468 def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>; 469 470 def : MipsPat<(f64 (sint_to_fp CPURegs:$src)), 471 (CVT_D64_W (MTC1 CPURegs:$src))>; 472 def : MipsPat<(f32 (sint_to_fp CPU64Regs:$src)), 473 (CVT_S_L (DMTC1 CPU64Regs:$src))>; 474 def : MipsPat<(f64 (sint_to_fp CPU64Regs:$src)), 475 (CVT_D64_L (DMTC1 CPU64Regs:$src))>; 476 477 def : MipsPat<(i32 (fp_to_sint FGR64:$src)), 478 (MFC1 (TRUNC_W_D64 FGR64:$src))>; 479 def : MipsPat<(i64 (fp_to_sint FGR32:$src)), (DMFC1 (TRUNC_L_S FGR32:$src))>; 480 def : MipsPat<(i64 (fp_to_sint FGR64:$src)), 481 (DMFC1 (TRUNC_L_D64 FGR64:$src))>; 482 483 def : MipsPat<(f32 (fround FGR64:$src)), (CVT_S_D64 FGR64:$src)>; 484 def : MipsPat<(f64 (fextend FGR32:$src)), (CVT_D64_S FGR32:$src)>; 485} 486