MipsInstrFPU.td revision 1e7739f6140da773b6e998525d7900fa82670f00
1//===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Mips FPU instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Floating Point Instructions 16// ------------------------ 17// * 64bit fp: 18// - 32 64-bit registers (default mode) 19// - 16 even 32-bit registers (32-bit compatible mode) for 20// single and double access. 21// * 32bit fp: 22// - 16 even 32-bit registers - single and double (aliased) 23// - 32 32-bit registers (within single-only mode) 24//===----------------------------------------------------------------------===// 25 26// Floating Point Compare and Branch 27def SDT_MipsFPBrcond : SDTypeProfile<0, 2, [SDTCisInt<0>, 28 SDTCisVT<1, OtherVT>]>; 29def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>, 30 SDTCisVT<2, i32>]>; 31def SDT_MipsCMovFP : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, 32 SDTCisSameAs<1, 2>]>; 33def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, 34 SDTCisVT<1, i32>, 35 SDTCisSameAs<1, 2>]>; 36def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, 37 SDTCisVT<1, f64>, 38 SDTCisVT<2, i32>]>; 39 40def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>; 41def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>; 42def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>; 43def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond, 44 [SDNPHasChain, SDNPOptInGlue]>; 45def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>; 46def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64", 47 SDT_MipsExtractElementF64>; 48 49// Operand for printing out a condition code. 50let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in 51 def condcode : Operand<i32>; 52 53//===----------------------------------------------------------------------===// 54// Feature predicates. 55//===----------------------------------------------------------------------===// 56 57def IsFP64bit : Predicate<"Subtarget.isFP64bit()">, 58 AssemblerPredicate<"FeatureFP64Bit">; 59def NotFP64bit : Predicate<"!Subtarget.isFP64bit()">, 60 AssemblerPredicate<"!FeatureFP64Bit">; 61def IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">, 62 AssemblerPredicate<"FeatureSingleFloat">; 63def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">, 64 AssemblerPredicate<"!FeatureSingleFloat">; 65 66// FP immediate patterns. 67def fpimm0 : PatLeaf<(fpimm), [{ 68 return N->isExactlyValue(+0.0); 69}]>; 70 71def fpimm0neg : PatLeaf<(fpimm), [{ 72 return N->isExactlyValue(-0.0); 73}]>; 74 75//===----------------------------------------------------------------------===// 76// Instruction Class Templates 77// 78// A set of multiclasses is used to address the register usage. 79// 80// S32 - single precision in 16 32bit even fp registers 81// single precision in 32 32bit fp registers in SingleOnly mode 82// S64 - single precision in 32 64bit fp registers (In64BitMode) 83// D32 - double precision in 16 32bit even fp registers 84// D64 - double precision in 32 64bit fp registers (In64BitMode) 85// 86// Only S32 and D32 are supported right now. 87//===----------------------------------------------------------------------===// 88 89class ADDS_FT<string opstr, RegisterClass RC, InstrItinClass Itin, bit IsComm, 90 SDPatternOperator OpNode= null_frag> : 91 InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft), 92 !strconcat(opstr, "\t$fd, $fs, $ft"), 93 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR> { 94 let isCommutable = IsComm; 95} 96 97multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm, 98 SDPatternOperator OpNode = null_frag> { 99 def _D32 : ADDS_FT<opstr, AFGR64, Itin, IsComm, OpNode>, 100 Requires<[NotFP64bit, HasStdEnc]>; 101 def _D64 : ADDS_FT<opstr, FGR64, Itin, IsComm, OpNode>, 102 Requires<[IsFP64bit, HasStdEnc]> { 103 string DecoderNamespace = "Mips64"; 104 } 105} 106 107class ABSS_FT<string opstr, RegisterClass DstRC, RegisterClass SrcRC, 108 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 109 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"), 110 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR>; 111 112multiclass ABSS_M<string opstr, InstrItinClass Itin, 113 SDPatternOperator OpNode= null_frag> { 114 def _D32 : ABSS_FT<opstr, AFGR64, AFGR64, Itin, OpNode>, 115 Requires<[NotFP64bit, HasStdEnc]>; 116 def _D64 : ABSS_FT<opstr, FGR64, FGR64, Itin, OpNode>, 117 Requires<[IsFP64bit, HasStdEnc]> { 118 string DecoderNamespace = "Mips64"; 119 } 120} 121 122multiclass ROUND_M<string opstr, InstrItinClass Itin> { 123 def _D32 : ABSS_FT<opstr, FGR32, AFGR64, Itin>, 124 Requires<[NotFP64bit, HasStdEnc]>; 125 def _D64 : ABSS_FT<opstr, FGR32, FGR64, Itin>, 126 Requires<[IsFP64bit, HasStdEnc]> { 127 let DecoderNamespace = "Mips64"; 128 } 129} 130 131class MFC1_FT<string opstr, RegisterClass DstRC, RegisterClass SrcRC, 132 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 133 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"), 134 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR>; 135 136class MTC1_FT<string opstr, RegisterClass DstRC, RegisterClass SrcRC, 137 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 138 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"), 139 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR>; 140 141class LW_FT<string opstr, RegisterClass RC, InstrItinClass Itin, 142 Operand MemOpnd, SDPatternOperator OpNode= null_frag> : 143 InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 144 [(set RC:$rt, (OpNode addr:$addr))], Itin, FrmFI> { 145 let DecoderMethod = "DecodeFMem"; 146} 147 148class SW_FT<string opstr, RegisterClass RC, InstrItinClass Itin, 149 Operand MemOpnd, SDPatternOperator OpNode= null_frag> : 150 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 151 [(OpNode RC:$rt, addr:$addr)], Itin, FrmFI> { 152 let DecoderMethod = "DecodeFMem"; 153} 154 155class MADDS_FT<string opstr, RegisterClass RC, InstrItinClass Itin, 156 SDPatternOperator OpNode = null_frag> : 157 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft), 158 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"), 159 [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))], Itin, FrmFR>; 160 161class NMADDS_FT<string opstr, RegisterClass RC, InstrItinClass Itin, 162 SDPatternOperator OpNode = null_frag> : 163 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft), 164 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"), 165 [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))], 166 Itin, FrmFR>; 167 168class LWXC1_FT<string opstr, RegisterClass DRC, RegisterClass PRC, 169 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> : 170 InstSE<(outs DRC:$fd), (ins PRC:$base, PRC:$index), 171 !strconcat(opstr, "\t$fd, ${index}(${base})"), 172 [(set DRC:$fd, (OpNode (add PRC:$base, PRC:$index)))], Itin, FrmFI>; 173 174class SWXC1_FT<string opstr, RegisterClass DRC, RegisterClass PRC, 175 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> : 176 InstSE<(outs), (ins DRC:$fs, PRC:$base, PRC:$index), 177 !strconcat(opstr, "\t$fs, ${index}(${base})"), 178 [(OpNode DRC:$fs, (add PRC:$base, PRC:$index))], Itin, FrmFI>; 179 180class BC1F_FT<string opstr, InstrItinClass Itin, 181 SDPatternOperator Op = null_frag> : 182 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"), 183 [(MipsFPBrcond Op, bb:$offset)], Itin, FrmFI> { 184 let isBranch = 1; 185 let isTerminator = 1; 186 let hasDelaySlot = 1; 187 let Defs = [AT]; 188 let Uses = [FCR31]; 189} 190 191class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin, 192 SDPatternOperator OpNode = null_frag> : 193 InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond), 194 !strconcat("c.$cond.", typestr, "\t$fs, $ft"), 195 [(OpNode RC:$fs, RC:$ft, imm:$cond)], Itin, FrmFR> { 196 let Defs = [FCR31]; 197} 198 199//===----------------------------------------------------------------------===// 200// Floating Point Instructions 201//===----------------------------------------------------------------------===// 202def ROUND_W_S : ABSS_FT<"round.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xc, 16>; 203def TRUNC_W_S : ABSS_FT<"trunc.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xd, 16>; 204def CEIL_W_S : ABSS_FT<"ceil.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xe, 16>; 205def FLOOR_W_S : ABSS_FT<"floor.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xf, 16>; 206def CVT_W_S : ABSS_FT<"cvt.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0x24, 16>, 207 NeverHasSideEffects; 208 209defm ROUND_W : ROUND_M<"round.w.d", IIFcvt>, ABSS_FM<0xc, 17>; 210defm TRUNC_W : ROUND_M<"trunc.w.d", IIFcvt>, ABSS_FM<0xd, 17>; 211defm CEIL_W : ROUND_M<"ceil.w.d", IIFcvt>, ABSS_FM<0xe, 17>; 212defm FLOOR_W : ROUND_M<"floor.w.d", IIFcvt>, ABSS_FM<0xf, 17>; 213defm CVT_W : ROUND_M<"cvt.w.d", IIFcvt>, ABSS_FM<0x24, 17>, 214 NeverHasSideEffects; 215 216let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in { 217 def ROUND_L_S : ABSS_FT<"round.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x8, 16>; 218 def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64, FGR64, IIFcvt>, 219 ABSS_FM<0x8, 17>; 220 def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x9, 16>; 221 def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64, FGR64, IIFcvt>, 222 ABSS_FM<0x9, 17>; 223 def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0xa, 16>; 224 def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64, FGR64, IIFcvt>, ABSS_FM<0xa, 17>; 225 def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0xb, 16>; 226 def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64, FGR64, IIFcvt>, 227 ABSS_FM<0xb, 17>; 228} 229 230def CVT_S_W : ABSS_FT<"cvt.s.w", FGR32, FGR32, IIFcvt>, ABSS_FM<0x20, 20>; 231def CVT_L_S : ABSS_FT<"cvt.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x25, 16>, 232 NeverHasSideEffects; 233def CVT_L_D64: ABSS_FT<"cvt.l.d", FGR64, FGR64, IIFcvt>, ABSS_FM<0x25, 17>, 234 NeverHasSideEffects; 235 236let Predicates = [NotFP64bit, HasStdEnc], neverHasSideEffects = 1 in { 237 def CVT_S_D32 : ABSS_FT<"cvt.s.d", FGR32, AFGR64, IIFcvt>, ABSS_FM<0x20, 17>; 238 def CVT_D32_W : ABSS_FT<"cvt.d.w", AFGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 20>; 239 def CVT_D32_S : ABSS_FT<"cvt.d.s", AFGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 16>; 240} 241 242let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64", 243 neverHasSideEffects = 1 in { 244 def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32, FGR64, IIFcvt>, ABSS_FM<0x20, 17>; 245 def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32, FGR64, IIFcvt>, ABSS_FM<0x20, 21>; 246 def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 20>; 247 def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 16>; 248 def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64, FGR64, IIFcvt>, ABSS_FM<0x21, 21>; 249} 250 251let Predicates = [NoNaNsFPMath, HasStdEnc] in { 252 def FABS_S : ABSS_FT<"abs.s", FGR32, FGR32, IIFcvt, fabs>, ABSS_FM<0x5, 16>; 253 def FNEG_S : ABSS_FT<"neg.s", FGR32, FGR32, IIFcvt, fneg>, ABSS_FM<0x7, 16>; 254 defm FABS : ABSS_M<"abs.d", IIFcvt, fabs>, ABSS_FM<0x5, 17>; 255 defm FNEG : ABSS_M<"neg.d", IIFcvt, fneg>, ABSS_FM<0x7, 17>; 256} 257 258def FSQRT_S : ABSS_FT<"sqrt.s", FGR32, FGR32, IIFsqrtSingle, fsqrt>, 259 ABSS_FM<0x4, 16>; 260defm FSQRT : ABSS_M<"sqrt.d", IIFsqrtDouble, fsqrt>, ABSS_FM<0x4, 17>; 261 262// The odd-numbered registers are only referenced when doing loads, 263// stores, and moves between floating-point and integer registers. 264// When defining instructions, we reference all 32-bit registers, 265// regardless of register aliasing. 266 267/// Move Control Registers From/To CPU Registers 268def CFC1 : MFC1_FT<"cfc1", CPURegs, CCR, IIFmove>, MFC1_FM<2>; 269def CTC1 : MTC1_FT<"ctc1", CCR, CPURegs, IIFmove>, MFC1_FM<6>; 270def MFC1 : MFC1_FT<"mfc1", CPURegs, FGR32, IIFmove, bitconvert>, MFC1_FM<0>; 271def MTC1 : MTC1_FT<"mtc1", FGR32, CPURegs, IIFmove, bitconvert>, MFC1_FM<4>; 272def DMFC1 : MFC1_FT<"dmfc1", CPU64Regs, FGR64, IIFmove, bitconvert>, MFC1_FM<1>; 273def DMTC1 : MTC1_FT<"dmtc1", FGR64, CPU64Regs, IIFmove, bitconvert>, MFC1_FM<5>; 274 275def FMOV_S : ABSS_FT<"mov.s", FGR32, FGR32, IIFmove>, ABSS_FM<0x6, 16>; 276def FMOV_D32 : ABSS_FT<"mov.d", AFGR64, AFGR64, IIFmove>, ABSS_FM<0x6, 17>, 277 Requires<[NotFP64bit, HasStdEnc]>; 278def FMOV_D64 : ABSS_FT<"mov.d", FGR64, FGR64, IIFmove>, ABSS_FM<0x6, 17>, 279 Requires<[IsFP64bit, HasStdEnc]> { 280 let DecoderNamespace = "Mips64"; 281} 282 283/// Floating Point Memory Instructions 284let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in { 285 def LWC1_P8 : LW_FT<"lwc1", FGR32, IILoad, mem64, load>, LW_FM<0x31>; 286 def SWC1_P8 : SW_FT<"swc1", FGR32, IIStore, mem64, store>, LW_FM<0x39>; 287 def LDC164_P8 : LW_FT<"ldc1", FGR64, IILoad, mem64, load>, LW_FM<0x35> { 288 let isCodeGenOnly =1; 289 } 290 def SDC164_P8 : SW_FT<"sdc1", FGR64, IIStore, mem64, store>, LW_FM<0x3d> { 291 let isCodeGenOnly =1; 292 } 293} 294 295let Predicates = [NotN64, HasStdEnc] in { 296 def LWC1 : LW_FT<"lwc1", FGR32, IILoad, mem, load>, LW_FM<0x31>; 297 def SWC1 : SW_FT<"swc1", FGR32, IIStore, mem, store>, LW_FM<0x39>; 298} 299 300let Predicates = [NotN64, HasMips64, HasStdEnc], 301 DecoderNamespace = "Mips64" in { 302 def LDC164 : LW_FT<"ldc1", FGR64, IILoad, mem, load>, LW_FM<0x35>; 303 def SDC164 : SW_FT<"sdc1", FGR64, IIStore, mem, store>, LW_FM<0x3d>; 304} 305 306let Predicates = [NotN64, NotMips64, HasStdEnc] in { 307 def LDC1 : LW_FT<"ldc1", AFGR64, IILoad, mem, load>, LW_FM<0x35>; 308 def SDC1 : SW_FT<"sdc1", AFGR64, IIStore, mem, store>, LW_FM<0x3d>; 309} 310 311// Indexed loads and stores. 312let Predicates = [HasFPIdx, HasStdEnc] in { 313 def LWXC1 : LWXC1_FT<"lwxc1", FGR32, CPURegs, IILoad, load>, LWXC1_FM<0>; 314 def SWXC1 : SWXC1_FT<"swxc1", FGR32, CPURegs, IIStore, store>, SWXC1_FM<8>; 315} 316 317let Predicates = [HasMips32r2, NotMips64, HasStdEnc] in { 318 def LDXC1 : LWXC1_FT<"ldxc1", AFGR64, CPURegs, IILoad, load>, LWXC1_FM<1>; 319 def SDXC1 : SWXC1_FT<"sdxc1", AFGR64, CPURegs, IIStore, store>, SWXC1_FM<9>; 320} 321 322let Predicates = [HasMips64, NotN64, HasStdEnc], DecoderNamespace="Mips64" in { 323 def LDXC164 : LWXC1_FT<"ldxc1", FGR64, CPURegs, IILoad, load>, LWXC1_FM<1>; 324 def SDXC164 : SWXC1_FT<"sdxc1", FGR64, CPURegs, IIStore, store>, SWXC1_FM<9>; 325} 326 327// n64 328let Predicates = [IsN64, HasStdEnc], isCodeGenOnly=1 in { 329 def LWXC1_P8 : LWXC1_FT<"lwxc1", FGR32, CPU64Regs, IILoad, load>, LWXC1_FM<0>; 330 def LDXC164_P8 : LWXC1_FT<"ldxc1", FGR64, CPU64Regs, IILoad, load>, 331 LWXC1_FM<1>; 332 def SWXC1_P8 : SWXC1_FT<"swxc1", FGR32, CPU64Regs, IIStore, store>, 333 SWXC1_FM<8>; 334 def SDXC164_P8 : SWXC1_FT<"sdxc1", FGR64, CPU64Regs, IIStore, store>, 335 SWXC1_FM<9>; 336} 337 338// Load/store doubleword indexed unaligned. 339let Predicates = [NotMips64, HasStdEnc] in { 340 def LUXC1 : LWXC1_FT<"luxc1", AFGR64, CPURegs, IILoad>, LWXC1_FM<0x5>; 341 def SUXC1 : SWXC1_FT<"suxc1", AFGR64, CPURegs, IIStore>, SWXC1_FM<0xd>; 342} 343 344let Predicates = [HasMips64, HasStdEnc], 345 DecoderNamespace="Mips64" in { 346 def LUXC164 : LWXC1_FT<"luxc1", FGR64, CPURegs, IILoad>, LWXC1_FM<0x5>; 347 def SUXC164 : SWXC1_FT<"suxc1", FGR64, CPURegs, IIStore>, SWXC1_FM<0xd>; 348} 349 350/// Floating-point Aritmetic 351def FADD_S : ADDS_FT<"add.s", FGR32, IIFadd, 1, fadd>, ADDS_FM<0x00, 16>; 352defm FADD : ADDS_M<"add.d", IIFadd, 1, fadd>, ADDS_FM<0x00, 17>; 353def FDIV_S : ADDS_FT<"div.s", FGR32, IIFdivSingle, 0, fdiv>, ADDS_FM<0x03, 16>; 354defm FDIV : ADDS_M<"div.d", IIFdivDouble, 0, fdiv>, ADDS_FM<0x03, 17>; 355def FMUL_S : ADDS_FT<"mul.s", FGR32, IIFmulSingle, 1, fmul>, ADDS_FM<0x02, 16>; 356defm FMUL : ADDS_M<"mul.d", IIFmulDouble, 1, fmul>, ADDS_FM<0x02, 17>; 357def FSUB_S : ADDS_FT<"sub.s", FGR32, IIFadd, 0, fsub>, ADDS_FM<0x01, 16>; 358defm FSUB : ADDS_M<"sub.d", IIFadd, 0, fsub>, ADDS_FM<0x01, 17>; 359 360let Predicates = [HasMips32r2, HasStdEnc] in { 361 def MADD_S : MADDS_FT<"madd.s", FGR32, IIFmulSingle, fadd>, MADDS_FM<4, 0>; 362 def MSUB_S : MADDS_FT<"msub.s", FGR32, IIFmulSingle, fsub>, MADDS_FM<5, 0>; 363} 364 365let Predicates = [HasMips32r2, NoNaNsFPMath, HasStdEnc] in { 366 def NMADD_S : NMADDS_FT<"nmadd.s", FGR32, IIFmulSingle, fadd>, MADDS_FM<6, 0>; 367 def NMSUB_S : NMADDS_FT<"nmsub.s", FGR32, IIFmulSingle, fsub>, MADDS_FM<7, 0>; 368} 369 370let Predicates = [HasMips32r2, NotFP64bit, HasStdEnc] in { 371 def MADD_D32 : MADDS_FT<"madd.d", AFGR64, IIFmulDouble, fadd>, MADDS_FM<4, 1>; 372 def MSUB_D32 : MADDS_FT<"msub.d", AFGR64, IIFmulDouble, fsub>, MADDS_FM<5, 1>; 373} 374 375let Predicates = [HasMips32r2, NotFP64bit, NoNaNsFPMath, HasStdEnc] in { 376 def NMADD_D32 : NMADDS_FT<"nmadd.d", AFGR64, IIFmulDouble, fadd>, 377 MADDS_FM<6, 1>; 378 def NMSUB_D32 : NMADDS_FT<"nmsub.d", AFGR64, IIFmulDouble, fsub>, 379 MADDS_FM<7, 1>; 380} 381 382let Predicates = [HasMips32r2, IsFP64bit, HasStdEnc], isCodeGenOnly=1 in { 383 def MADD_D64 : MADDS_FT<"madd.d", FGR64, IIFmulDouble, fadd>, MADDS_FM<4, 1>; 384 def MSUB_D64 : MADDS_FT<"msub.d", FGR64, IIFmulDouble, fsub>, MADDS_FM<5, 1>; 385} 386 387let Predicates = [HasMips32r2, IsFP64bit, NoNaNsFPMath, HasStdEnc], 388 isCodeGenOnly=1 in { 389 def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64, IIFmulDouble, fadd>, 390 MADDS_FM<6, 1>; 391 def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64, IIFmulDouble, fsub>, 392 MADDS_FM<7, 1>; 393} 394 395//===----------------------------------------------------------------------===// 396// Floating Point Branch Codes 397//===----------------------------------------------------------------------===// 398// Mips branch codes. These correspond to condcode in MipsInstrInfo.h. 399// They must be kept in synch. 400def MIPS_BRANCH_F : PatLeaf<(i32 0)>; 401def MIPS_BRANCH_T : PatLeaf<(i32 1)>; 402 403let DecoderMethod = "DecodeBC1" in { 404def BC1F : BC1F_FT<"bc1f", IIBranch, MIPS_BRANCH_F>, BC1F_FM<0, 0>; 405def BC1T : BC1F_FT<"bc1t", IIBranch, MIPS_BRANCH_T>, BC1F_FM<0, 1>; 406} 407//===----------------------------------------------------------------------===// 408// Floating Point Flag Conditions 409//===----------------------------------------------------------------------===// 410// Mips condition codes. They must correspond to condcode in MipsInstrInfo.h. 411// They must be kept in synch. 412def MIPS_FCOND_F : PatLeaf<(i32 0)>; 413def MIPS_FCOND_UN : PatLeaf<(i32 1)>; 414def MIPS_FCOND_OEQ : PatLeaf<(i32 2)>; 415def MIPS_FCOND_UEQ : PatLeaf<(i32 3)>; 416def MIPS_FCOND_OLT : PatLeaf<(i32 4)>; 417def MIPS_FCOND_ULT : PatLeaf<(i32 5)>; 418def MIPS_FCOND_OLE : PatLeaf<(i32 6)>; 419def MIPS_FCOND_ULE : PatLeaf<(i32 7)>; 420def MIPS_FCOND_SF : PatLeaf<(i32 8)>; 421def MIPS_FCOND_NGLE : PatLeaf<(i32 9)>; 422def MIPS_FCOND_SEQ : PatLeaf<(i32 10)>; 423def MIPS_FCOND_NGL : PatLeaf<(i32 11)>; 424def MIPS_FCOND_LT : PatLeaf<(i32 12)>; 425def MIPS_FCOND_NGE : PatLeaf<(i32 13)>; 426def MIPS_FCOND_LE : PatLeaf<(i32 14)>; 427def MIPS_FCOND_NGT : PatLeaf<(i32 15)>; 428 429/// Floating Point Compare 430def FCMP_S32 : CEQS_FT<"s", FGR32, IIFcmp, MipsFPCmp>, CEQS_FM<16>; 431def FCMP_D32 : CEQS_FT<"d", AFGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>, 432 Requires<[NotFP64bit, HasStdEnc]>; 433let DecoderNamespace = "Mips64" in 434def FCMP_D64 : CEQS_FT<"d", FGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>, 435 Requires<[IsFP64bit, HasStdEnc]>; 436 437//===----------------------------------------------------------------------===// 438// Floating Point Pseudo-Instructions 439//===----------------------------------------------------------------------===// 440def MOVCCRToCCR : PseudoSE<(outs CCR:$dst), (ins CCR:$src), []>; 441 442// This pseudo instr gets expanded into 2 mtc1 instrs after register 443// allocation. 444def BuildPairF64 : 445 PseudoSE<(outs AFGR64:$dst), 446 (ins CPURegs:$lo, CPURegs:$hi), 447 [(set AFGR64:$dst, (MipsBuildPairF64 CPURegs:$lo, CPURegs:$hi))]>; 448 449// This pseudo instr gets expanded into 2 mfc1 instrs after register 450// allocation. 451// if n is 0, lower part of src is extracted. 452// if n is 1, higher part of src is extracted. 453def ExtractElementF64 : 454 PseudoSE<(outs CPURegs:$dst), (ins AFGR64:$src, i32imm:$n), 455 [(set CPURegs:$dst, (MipsExtractElementF64 AFGR64:$src, imm:$n))]>; 456 457//===----------------------------------------------------------------------===// 458// Floating Point Patterns 459//===----------------------------------------------------------------------===// 460def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>; 461def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>; 462 463def : MipsPat<(f32 (sint_to_fp CPURegs:$src)), (CVT_S_W (MTC1 CPURegs:$src))>; 464def : MipsPat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S FGR32:$src))>; 465 466let Predicates = [NotFP64bit, HasStdEnc] in { 467 def : MipsPat<(f64 (sint_to_fp CPURegs:$src)), 468 (CVT_D32_W (MTC1 CPURegs:$src))>; 469 def : MipsPat<(i32 (fp_to_sint AFGR64:$src)), 470 (MFC1 (TRUNC_W_D32 AFGR64:$src))>; 471 def : MipsPat<(f32 (fround AFGR64:$src)), (CVT_S_D32 AFGR64:$src)>; 472 def : MipsPat<(f64 (fextend FGR32:$src)), (CVT_D32_S FGR32:$src)>; 473} 474 475let Predicates = [IsFP64bit, HasStdEnc] in { 476 def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>; 477 def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>; 478 479 def : MipsPat<(f64 (sint_to_fp CPURegs:$src)), 480 (CVT_D64_W (MTC1 CPURegs:$src))>; 481 def : MipsPat<(f32 (sint_to_fp CPU64Regs:$src)), 482 (CVT_S_L (DMTC1 CPU64Regs:$src))>; 483 def : MipsPat<(f64 (sint_to_fp CPU64Regs:$src)), 484 (CVT_D64_L (DMTC1 CPU64Regs:$src))>; 485 486 def : MipsPat<(i32 (fp_to_sint FGR64:$src)), 487 (MFC1 (TRUNC_W_D64 FGR64:$src))>; 488 def : MipsPat<(i64 (fp_to_sint FGR32:$src)), (DMFC1 (TRUNC_L_S FGR32:$src))>; 489 def : MipsPat<(i64 (fp_to_sint FGR64:$src)), 490 (DMFC1 (TRUNC_L_D64 FGR64:$src))>; 491 492 def : MipsPat<(f32 (fround FGR64:$src)), (CVT_S_D64 FGR64:$src)>; 493 def : MipsPat<(f64 (fextend FGR32:$src)), (CVT_D64_S FGR32:$src)>; 494} 495