MipsInstrFPU.td revision ae7e7cb3d3ec657b7e6dd94cf036cdc65c182f59 
1//===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the Mips FPU instruction set.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// Floating Point Instructions
16// ------------------------
17// * 64bit fp:
18//    - 32 64-bit registers (default mode)
19//    - 16 even 32-bit registers (32-bit compatible mode) for
20//      single and double access.
21// * 32bit fp:
22//    - 16 even 32-bit registers - single and double (aliased)
23//    - 32 32-bit registers (within single-only mode)
24//===----------------------------------------------------------------------===//
25
26// Floating Point Compare and Branch
27def SDT_MipsFPBrcond : SDTypeProfile<0, 2, [SDTCisInt<0>,
28                                            SDTCisVT<1, OtherVT>]>;
29def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>,
30                                         SDTCisVT<2, i32>]>;
31def SDT_MipsCMovFP : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
32                                          SDTCisSameAs<1, 2>]>;
33def SDT_MipsTruncIntFP : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>;
34def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
35                                                SDTCisVT<1, i32>,
36                                                SDTCisSameAs<1, 2>]>;
37def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
38                                                     SDTCisVT<1, f64>,
39                                                     SDTCisVT<2, i32>]>;
40
41def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>;
42def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>;
43def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>;
44def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond,
45                          [SDNPHasChain, SDNPOptInGlue]>;
46def MipsTruncIntFP : SDNode<"MipsISD::TruncIntFP", SDT_MipsTruncIntFP>;
47def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>;
48def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64",
49                                   SDT_MipsExtractElementF64>;
50
51// Operand for printing out a condition code.
52let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in
53  def condcode : Operand<i32>;
54
55//===----------------------------------------------------------------------===//
56// Feature predicates.
57//===----------------------------------------------------------------------===//
58
59def IsFP64bit        : Predicate<"Subtarget.isFP64bit()">,
60                       AssemblerPredicate<"FeatureFP64Bit">;
61def NotFP64bit       : Predicate<"!Subtarget.isFP64bit()">,
62                       AssemblerPredicate<"!FeatureFP64Bit">;
63def IsSingleFloat    : Predicate<"Subtarget.isSingleFloat()">,
64                       AssemblerPredicate<"FeatureSingleFloat">;
65def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">,
66                       AssemblerPredicate<"!FeatureSingleFloat">;
67
68// FP immediate patterns.
69def fpimm0 : PatLeaf<(fpimm), [{
70  return N->isExactlyValue(+0.0);
71}]>;
72
73def fpimm0neg : PatLeaf<(fpimm), [{
74  return N->isExactlyValue(-0.0);
75}]>;
76
77//===----------------------------------------------------------------------===//
78// Instruction Class Templates
79//
80// A set of multiclasses is used to address the register usage.
81//
82// S32 - single precision in 16 32bit even fp registers
83//       single precision in 32 32bit fp registers in SingleOnly mode
84// S64 - single precision in 32 64bit fp registers (In64BitMode)
85// D32 - double precision in 16 32bit even fp registers
86// D64 - double precision in 32 64bit fp registers (In64BitMode)
87//
88// Only S32 and D32 are supported right now.
89//===----------------------------------------------------------------------===//
90
91class ADDS_FT<string opstr, RegisterClass RC, InstrItinClass Itin, bit IsComm,
92              SDPatternOperator OpNode= null_frag> :
93  InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft),
94         !strconcat(opstr, "\t$fd, $fs, $ft"),
95         [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR> {
96  let isCommutable = IsComm;
97}
98
99multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm,
100                  SDPatternOperator OpNode = null_frag> {
101  def _D32 : ADDS_FT<opstr, AFGR64, Itin, IsComm, OpNode>,
102             Requires<[NotFP64bit, HasStdEnc]>;
103  def _D64 : ADDS_FT<opstr, FGR64, Itin, IsComm, OpNode>,
104             Requires<[IsFP64bit, HasStdEnc]> {
105    string DecoderNamespace = "Mips64";
106  }
107}
108
109class ABSS_FT<string opstr, RegisterClass DstRC, RegisterClass SrcRC,
110              InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
111  InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
112         [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR>,
113  NeverHasSideEffects;
114
115multiclass ABSS_M<string opstr, InstrItinClass Itin,
116                  SDPatternOperator OpNode= null_frag> {
117  def _D32 : ABSS_FT<opstr, AFGR64, AFGR64, Itin, OpNode>,
118             Requires<[NotFP64bit, HasStdEnc]>;
119  def _D64 : ABSS_FT<opstr, FGR64, FGR64, Itin, OpNode>,
120             Requires<[IsFP64bit, HasStdEnc]> {
121    string DecoderNamespace = "Mips64";
122  }
123}
124
125multiclass ROUND_M<string opstr, InstrItinClass Itin> {
126  def _D32 : ABSS_FT<opstr, FGR32, AFGR64, Itin>,
127             Requires<[NotFP64bit, HasStdEnc]>;
128  def _D64 : ABSS_FT<opstr, FGR32, FGR64, Itin>,
129             Requires<[IsFP64bit, HasStdEnc]> {
130    let DecoderNamespace = "Mips64";
131  }
132}
133
134class MFC1_FT<string opstr, RegisterClass DstRC, RegisterClass SrcRC,
135              InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
136  InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
137         [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR>;
138
139class MTC1_FT<string opstr, RegisterClass DstRC, RegisterClass SrcRC,
140              InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
141  InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
142         [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR>;
143
144class MFC1_FT_CCR<string opstr, RegisterClass DstRC, RegisterOperand SrcRC,
145              InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
146  InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
147         [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR>;
148
149class MTC1_FT_CCR<string opstr, RegisterOperand DstRC, RegisterClass SrcRC,
150              InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
151  InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
152         [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR>;
153
154class LW_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
155            Operand MemOpnd, SDPatternOperator OpNode= null_frag> :
156  InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
157         [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI> {
158  let DecoderMethod = "DecodeFMem";
159  let mayLoad = 1;
160}
161
162class SW_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
163            Operand MemOpnd, SDPatternOperator OpNode= null_frag> :
164  InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
165         [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI> {
166  let DecoderMethod = "DecodeFMem";
167  let mayStore = 1;
168}
169
170class MADDS_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
171               SDPatternOperator OpNode = null_frag> :
172  InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
173         !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
174         [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))], Itin, FrmFR>;
175
176class NMADDS_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
177                SDPatternOperator OpNode = null_frag> :
178  InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
179         !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
180         [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))],
181         Itin, FrmFR>;
182
183class LWXC1_FT<string opstr, RegisterClass DRC, RegisterClass PRC,
184               InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
185  InstSE<(outs DRC:$fd), (ins PRC:$base, PRC:$index),
186         !strconcat(opstr, "\t$fd, ${index}(${base})"),
187         [(set DRC:$fd, (OpNode (add PRC:$base, PRC:$index)))], Itin, FrmFI> {
188  let AddedComplexity = 20;
189}
190
191class SWXC1_FT<string opstr, RegisterClass DRC, RegisterClass PRC,
192               InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
193  InstSE<(outs), (ins DRC:$fs, PRC:$base, PRC:$index),
194         !strconcat(opstr, "\t$fs, ${index}(${base})"),
195         [(OpNode DRC:$fs, (add PRC:$base, PRC:$index))], Itin, FrmFI> {
196  let AddedComplexity = 20;
197}
198
199class BC1F_FT<string opstr, InstrItinClass Itin,
200              SDPatternOperator Op = null_frag>  :
201  InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"),
202         [(MipsFPBrcond Op, bb:$offset)], Itin, FrmFI> {
203  let isBranch = 1;
204  let isTerminator = 1;
205  let hasDelaySlot = 1;
206  let Defs = [AT];
207  let Uses = [FCR31];
208}
209
210class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin,
211              SDPatternOperator OpNode = null_frag>  :
212  InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond),
213         !strconcat("c.$cond.", typestr, "\t$fs, $ft"),
214         [(OpNode RC:$fs, RC:$ft, imm:$cond)], Itin, FrmFR> {
215  let Defs = [FCR31];
216}
217
218//===----------------------------------------------------------------------===//
219// Floating Point Instructions
220//===----------------------------------------------------------------------===//
221def ROUND_W_S  : ABSS_FT<"round.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xc, 16>;
222def TRUNC_W_S  : ABSS_FT<"trunc.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xd, 16>;
223def CEIL_W_S   : ABSS_FT<"ceil.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xe, 16>;
224def FLOOR_W_S  : ABSS_FT<"floor.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xf, 16>;
225def CVT_W_S    : ABSS_FT<"cvt.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0x24, 16>;
226
227defm ROUND_W : ROUND_M<"round.w.d", IIFcvt>, ABSS_FM<0xc, 17>;
228defm TRUNC_W : ROUND_M<"trunc.w.d", IIFcvt>, ABSS_FM<0xd, 17>;
229defm CEIL_W  : ROUND_M<"ceil.w.d", IIFcvt>, ABSS_FM<0xe, 17>;
230defm FLOOR_W : ROUND_M<"floor.w.d", IIFcvt>, ABSS_FM<0xf, 17>;
231defm CVT_W   : ROUND_M<"cvt.w.d", IIFcvt>, ABSS_FM<0x24, 17>;
232
233let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
234  def ROUND_L_S : ABSS_FT<"round.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x8, 16>;
235  def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64, FGR64, IIFcvt>,
236                    ABSS_FM<0x8, 17>;
237  def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x9, 16>;
238  def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64, FGR64, IIFcvt>,
239                    ABSS_FM<0x9, 17>;
240  def CEIL_L_S  : ABSS_FT<"ceil.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0xa, 16>;
241  def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64, FGR64, IIFcvt>, ABSS_FM<0xa, 17>;
242  def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0xb, 16>;
243  def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64, FGR64, IIFcvt>,
244                    ABSS_FM<0xb, 17>;
245}
246
247def CVT_S_W : ABSS_FT<"cvt.s.w", FGR32, FGR32, IIFcvt>, ABSS_FM<0x20, 20>;
248def CVT_L_S : ABSS_FT<"cvt.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x25, 16>;
249def CVT_L_D64: ABSS_FT<"cvt.l.d", FGR64, FGR64, IIFcvt>, ABSS_FM<0x25, 17>;
250
251let Predicates = [NotFP64bit, HasStdEnc] in {
252  def CVT_S_D32 : ABSS_FT<"cvt.s.d", FGR32, AFGR64, IIFcvt>, ABSS_FM<0x20, 17>;
253  def CVT_D32_W : ABSS_FT<"cvt.d.w", AFGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 20>;
254  def CVT_D32_S : ABSS_FT<"cvt.d.s", AFGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 16>;
255}
256
257let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
258  def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32, FGR64, IIFcvt>, ABSS_FM<0x20, 17>;
259  def CVT_S_L   : ABSS_FT<"cvt.s.l", FGR32, FGR64, IIFcvt>, ABSS_FM<0x20, 21>;
260  def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 20>;
261  def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 16>;
262  def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64, FGR64, IIFcvt>, ABSS_FM<0x21, 21>;
263}
264
265let isPseudo = 1, isCodeGenOnly = 1 in {
266  def PseudoCVT_S_W : ABSS_FT<"", FGR32, CPURegs, IIFcvt>;
267  def PseudoCVT_D32_W : ABSS_FT<"", AFGR64, CPURegs, IIFcvt>;
268  def PseudoCVT_S_L : ABSS_FT<"", FGR64, CPU64Regs, IIFcvt>;
269  def PseudoCVT_D64_W : ABSS_FT<"", FGR64, CPURegs, IIFcvt>;
270  def PseudoCVT_D64_L : ABSS_FT<"", FGR64, CPU64Regs, IIFcvt>;
271}
272
273let Predicates = [NoNaNsFPMath, HasStdEnc] in {
274  def FABS_S : ABSS_FT<"abs.s", FGR32, FGR32, IIFcvt, fabs>, ABSS_FM<0x5, 16>;
275  def FNEG_S : ABSS_FT<"neg.s", FGR32, FGR32, IIFcvt, fneg>, ABSS_FM<0x7, 16>;
276  defm FABS : ABSS_M<"abs.d", IIFcvt, fabs>, ABSS_FM<0x5, 17>;
277  defm FNEG : ABSS_M<"neg.d", IIFcvt, fneg>, ABSS_FM<0x7, 17>;
278}
279
280def  FSQRT_S : ABSS_FT<"sqrt.s", FGR32, FGR32, IIFsqrtSingle, fsqrt>,
281               ABSS_FM<0x4, 16>;
282defm FSQRT : ABSS_M<"sqrt.d", IIFsqrtDouble, fsqrt>, ABSS_FM<0x4, 17>;
283
284// The odd-numbered registers are only referenced when doing loads,
285// stores, and moves between floating-point and integer registers.
286// When defining instructions, we reference all 32-bit registers,
287// regardless of register aliasing.
288
289/// Move Control Registers From/To CPU Registers
290def CFC1 : MFC1_FT_CCR<"cfc1", CPURegs, CCROpnd, IIFmove>, MFC1_FM<2>;
291def CTC1 : MTC1_FT_CCR<"ctc1", CCROpnd, CPURegs, IIFmove>, MFC1_FM<6>;
292def MFC1 : MFC1_FT<"mfc1", CPURegs, FGR32, IIFmove, bitconvert>, MFC1_FM<0>;
293def MTC1 : MTC1_FT<"mtc1", FGR32, CPURegs, IIFmove, bitconvert>, MFC1_FM<4>;
294def DMFC1 : MFC1_FT<"dmfc1", CPU64Regs, FGR64, IIFmove, bitconvert>, MFC1_FM<1>;
295def DMTC1 : MTC1_FT<"dmtc1", FGR64, CPU64Regs, IIFmove, bitconvert>, MFC1_FM<5>;
296
297def FMOV_S   : ABSS_FT<"mov.s", FGR32, FGR32, IIFmove>, ABSS_FM<0x6, 16>;
298def FMOV_D32 : ABSS_FT<"mov.d", AFGR64, AFGR64, IIFmove>, ABSS_FM<0x6, 17>,
299               Requires<[NotFP64bit, HasStdEnc]>;
300def FMOV_D64 : ABSS_FT<"mov.d", FGR64, FGR64, IIFmove>, ABSS_FM<0x6, 17>,
301               Requires<[IsFP64bit, HasStdEnc]> {
302  let DecoderNamespace = "Mips64";
303}
304
305/// Floating Point Memory Instructions
306let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in {
307  def LWC1_P8 : LW_FT<"lwc1", FGR32, IILoad, mem64, load>, LW_FM<0x31>;
308  def SWC1_P8 : SW_FT<"swc1", FGR32, IIStore, mem64, store>, LW_FM<0x39>;
309  def LDC164_P8 : LW_FT<"ldc1", FGR64, IILoad, mem64, load>, LW_FM<0x35> {
310    let isCodeGenOnly =1;
311  }
312  def SDC164_P8 : SW_FT<"sdc1", FGR64, IIStore, mem64, store>, LW_FM<0x3d> {
313    let isCodeGenOnly =1;
314  }
315}
316
317let Predicates = [NotN64, HasStdEnc] in {
318  def LWC1 : LW_FT<"lwc1", FGR32, IILoad, mem, load>, LW_FM<0x31>;
319  def SWC1 : SW_FT<"swc1", FGR32, IIStore, mem, store>, LW_FM<0x39>;
320}
321
322let Predicates = [NotN64, HasMips64, HasStdEnc],
323  DecoderNamespace = "Mips64" in {
324  def LDC164 : LW_FT<"ldc1", FGR64, IILoad, mem, load>, LW_FM<0x35>;
325  def SDC164 : SW_FT<"sdc1", FGR64, IIStore, mem, store>, LW_FM<0x3d>;
326}
327
328let Predicates = [NotN64, NotMips64, HasStdEnc] in {
329  let isPseudo = 1, isCodeGenOnly = 1 in {
330    def PseudoLDC1 : LW_FT<"", AFGR64, IILoad, mem, load>;
331    def PseudoSDC1 : SW_FT<"", AFGR64, IIStore, mem, store>;
332  }
333  def LDC1 : LW_FT<"ldc1", AFGR64, IILoad, mem>, LW_FM<0x35>;
334  def SDC1 : SW_FT<"sdc1", AFGR64, IIStore, mem>, LW_FM<0x3d>;
335}
336
337// Indexed loads and stores.
338let Predicates = [HasFPIdx, HasStdEnc] in {
339  def LWXC1 : LWXC1_FT<"lwxc1", FGR32, CPURegs, IILoad, load>, LWXC1_FM<0>;
340  def SWXC1 : SWXC1_FT<"swxc1", FGR32, CPURegs, IIStore, store>, SWXC1_FM<8>;
341}
342
343let Predicates = [HasMips32r2, NotMips64, HasStdEnc] in {
344  def LDXC1 : LWXC1_FT<"ldxc1", AFGR64, CPURegs, IILoad, load>, LWXC1_FM<1>;
345  def SDXC1 : SWXC1_FT<"sdxc1", AFGR64, CPURegs, IIStore, store>, SWXC1_FM<9>;
346}
347
348let Predicates = [HasMips64, NotN64, HasStdEnc], DecoderNamespace="Mips64" in {
349  def LDXC164 : LWXC1_FT<"ldxc1", FGR64, CPURegs, IILoad, load>, LWXC1_FM<1>;
350  def SDXC164 : SWXC1_FT<"sdxc1", FGR64, CPURegs, IIStore, store>, SWXC1_FM<9>;
351}
352
353// n64
354let Predicates = [IsN64, HasStdEnc], isCodeGenOnly=1 in {
355  def LWXC1_P8 : LWXC1_FT<"lwxc1", FGR32, CPU64Regs, IILoad, load>, LWXC1_FM<0>;
356  def LDXC164_P8 : LWXC1_FT<"ldxc1", FGR64, CPU64Regs, IILoad, load>,
357                   LWXC1_FM<1>;
358  def SWXC1_P8 : SWXC1_FT<"swxc1", FGR32, CPU64Regs, IIStore, store>,
359                 SWXC1_FM<8>;
360  def SDXC164_P8 : SWXC1_FT<"sdxc1", FGR64, CPU64Regs, IIStore, store>,
361                   SWXC1_FM<9>;
362}
363
364// Load/store doubleword indexed unaligned.
365let Predicates = [NotMips64, HasStdEnc] in {
366  def LUXC1 : LWXC1_FT<"luxc1", AFGR64, CPURegs, IILoad>, LWXC1_FM<0x5>;
367  def SUXC1 : SWXC1_FT<"suxc1", AFGR64, CPURegs, IIStore>, SWXC1_FM<0xd>;
368}
369
370let Predicates = [HasMips64, HasStdEnc],
371  DecoderNamespace="Mips64" in {
372  def LUXC164 : LWXC1_FT<"luxc1", FGR64, CPURegs, IILoad>, LWXC1_FM<0x5>;
373  def SUXC164 : SWXC1_FT<"suxc1", FGR64, CPURegs, IIStore>, SWXC1_FM<0xd>;
374}
375
376/// Floating-point Aritmetic
377def FADD_S : ADDS_FT<"add.s", FGR32, IIFadd, 1, fadd>, ADDS_FM<0x00, 16>;
378defm FADD : ADDS_M<"add.d", IIFadd, 1, fadd>, ADDS_FM<0x00, 17>;
379def FDIV_S : ADDS_FT<"div.s", FGR32, IIFdivSingle, 0, fdiv>, ADDS_FM<0x03, 16>;
380defm FDIV : ADDS_M<"div.d", IIFdivDouble, 0, fdiv>, ADDS_FM<0x03, 17>;
381def FMUL_S : ADDS_FT<"mul.s", FGR32, IIFmulSingle, 1, fmul>, ADDS_FM<0x02, 16>;
382defm FMUL : ADDS_M<"mul.d", IIFmulDouble, 1, fmul>, ADDS_FM<0x02, 17>;
383def FSUB_S : ADDS_FT<"sub.s", FGR32, IIFadd, 0, fsub>, ADDS_FM<0x01, 16>;
384defm FSUB : ADDS_M<"sub.d", IIFadd, 0, fsub>, ADDS_FM<0x01, 17>;
385
386let Predicates = [HasMips32r2, HasStdEnc] in {
387  def MADD_S : MADDS_FT<"madd.s", FGR32, IIFmulSingle, fadd>, MADDS_FM<4, 0>;
388  def MSUB_S : MADDS_FT<"msub.s", FGR32, IIFmulSingle, fsub>, MADDS_FM<5, 0>;
389}
390
391let Predicates = [HasMips32r2, NoNaNsFPMath, HasStdEnc] in {
392  def NMADD_S : NMADDS_FT<"nmadd.s", FGR32, IIFmulSingle, fadd>, MADDS_FM<6, 0>;
393  def NMSUB_S : NMADDS_FT<"nmsub.s", FGR32, IIFmulSingle, fsub>, MADDS_FM<7, 0>;
394}
395
396let Predicates = [HasMips32r2, NotFP64bit, HasStdEnc] in {
397  def MADD_D32 : MADDS_FT<"madd.d", AFGR64, IIFmulDouble, fadd>, MADDS_FM<4, 1>;
398  def MSUB_D32 : MADDS_FT<"msub.d", AFGR64, IIFmulDouble, fsub>, MADDS_FM<5, 1>;
399}
400
401let Predicates = [HasMips32r2, NotFP64bit, NoNaNsFPMath, HasStdEnc] in {
402  def NMADD_D32 : NMADDS_FT<"nmadd.d", AFGR64, IIFmulDouble, fadd>,
403                  MADDS_FM<6, 1>;
404  def NMSUB_D32 : NMADDS_FT<"nmsub.d", AFGR64, IIFmulDouble, fsub>,
405                  MADDS_FM<7, 1>;
406}
407
408let Predicates = [HasMips32r2, IsFP64bit, HasStdEnc], isCodeGenOnly=1 in {
409  def MADD_D64 : MADDS_FT<"madd.d", FGR64, IIFmulDouble, fadd>, MADDS_FM<4, 1>;
410  def MSUB_D64 : MADDS_FT<"msub.d", FGR64, IIFmulDouble, fsub>, MADDS_FM<5, 1>;
411}
412
413let Predicates = [HasMips32r2, IsFP64bit, NoNaNsFPMath, HasStdEnc],
414    isCodeGenOnly=1 in {
415  def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64, IIFmulDouble, fadd>,
416                  MADDS_FM<6, 1>;
417  def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64, IIFmulDouble, fsub>,
418                  MADDS_FM<7, 1>;
419}
420
421//===----------------------------------------------------------------------===//
422// Floating Point Branch Codes
423//===----------------------------------------------------------------------===//
424// Mips branch codes. These correspond to condcode in MipsInstrInfo.h.
425// They must be kept in synch.
426def MIPS_BRANCH_F  : PatLeaf<(i32 0)>;
427def MIPS_BRANCH_T  : PatLeaf<(i32 1)>;
428
429let DecoderMethod = "DecodeBC1" in {
430def BC1F : BC1F_FT<"bc1f", IIBranch, MIPS_BRANCH_F>, BC1F_FM<0, 0>;
431def BC1T : BC1F_FT<"bc1t", IIBranch, MIPS_BRANCH_T>, BC1F_FM<0, 1>;
432}
433//===----------------------------------------------------------------------===//
434// Floating Point Flag Conditions
435//===----------------------------------------------------------------------===//
436// Mips condition codes. They must correspond to condcode in MipsInstrInfo.h.
437// They must be kept in synch.
438def MIPS_FCOND_F    : PatLeaf<(i32 0)>;
439def MIPS_FCOND_UN   : PatLeaf<(i32 1)>;
440def MIPS_FCOND_OEQ  : PatLeaf<(i32 2)>;
441def MIPS_FCOND_UEQ  : PatLeaf<(i32 3)>;
442def MIPS_FCOND_OLT  : PatLeaf<(i32 4)>;
443def MIPS_FCOND_ULT  : PatLeaf<(i32 5)>;
444def MIPS_FCOND_OLE  : PatLeaf<(i32 6)>;
445def MIPS_FCOND_ULE  : PatLeaf<(i32 7)>;
446def MIPS_FCOND_SF   : PatLeaf<(i32 8)>;
447def MIPS_FCOND_NGLE : PatLeaf<(i32 9)>;
448def MIPS_FCOND_SEQ  : PatLeaf<(i32 10)>;
449def MIPS_FCOND_NGL  : PatLeaf<(i32 11)>;
450def MIPS_FCOND_LT   : PatLeaf<(i32 12)>;
451def MIPS_FCOND_NGE  : PatLeaf<(i32 13)>;
452def MIPS_FCOND_LE   : PatLeaf<(i32 14)>;
453def MIPS_FCOND_NGT  : PatLeaf<(i32 15)>;
454
455/// Floating Point Compare
456def FCMP_S32 : CEQS_FT<"s", FGR32, IIFcmp, MipsFPCmp>, CEQS_FM<16>;
457def FCMP_D32 : CEQS_FT<"d", AFGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>,
458               Requires<[NotFP64bit, HasStdEnc]>;
459let DecoderNamespace = "Mips64" in
460def FCMP_D64 : CEQS_FT<"d", FGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>,
461               Requires<[IsFP64bit, HasStdEnc]>;
462
463//===----------------------------------------------------------------------===//
464// Floating Point Pseudo-Instructions
465//===----------------------------------------------------------------------===//
466def MOVCCRToCCR : PseudoSE<(outs CCR:$dst), (ins CCROpnd:$src), []>;
467
468// This pseudo instr gets expanded into 2 mtc1 instrs after register
469// allocation.
470def BuildPairF64 :
471  PseudoSE<(outs AFGR64:$dst),
472           (ins CPURegs:$lo, CPURegs:$hi),
473           [(set AFGR64:$dst, (MipsBuildPairF64 CPURegs:$lo, CPURegs:$hi))]>;
474
475// This pseudo instr gets expanded into 2 mfc1 instrs after register
476// allocation.
477// if n is 0, lower part of src is extracted.
478// if n is 1, higher part of src is extracted.
479def ExtractElementF64 :
480  PseudoSE<(outs CPURegs:$dst), (ins AFGR64:$src, i32imm:$n),
481           [(set CPURegs:$dst, (MipsExtractElementF64 AFGR64:$src, imm:$n))]>;
482
483//===----------------------------------------------------------------------===//
484// Floating Point Patterns
485//===----------------------------------------------------------------------===//
486def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>;
487def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
488
489def : MipsPat<(f32 (sint_to_fp CPURegs:$src)), (PseudoCVT_S_W CPURegs:$src)>;
490def : MipsPat<(MipsTruncIntFP FGR32:$src), (TRUNC_W_S FGR32:$src)>;
491
492let Predicates = [NotFP64bit, HasStdEnc] in {
493  def : MipsPat<(f64 (sint_to_fp CPURegs:$src)),
494                (PseudoCVT_D32_W CPURegs:$src)>;
495  def : MipsPat<(MipsTruncIntFP AFGR64:$src), (TRUNC_W_D32 AFGR64:$src)>;
496  def : MipsPat<(f32 (fround AFGR64:$src)), (CVT_S_D32 AFGR64:$src)>;
497  def : MipsPat<(f64 (fextend FGR32:$src)), (CVT_D32_S FGR32:$src)>;
498}
499
500let Predicates = [IsFP64bit, HasStdEnc] in {
501  def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>;
502  def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>;
503
504  def : MipsPat<(f64 (sint_to_fp CPURegs:$src)),
505                (PseudoCVT_D64_W CPURegs:$src)>;
506  def : MipsPat<(f32 (sint_to_fp CPU64Regs:$src)),
507                (EXTRACT_SUBREG (PseudoCVT_S_L CPU64Regs:$src), sub_32)>;
508  def : MipsPat<(f64 (sint_to_fp CPU64Regs:$src)),
509                (PseudoCVT_D64_L CPU64Regs:$src)>;
510
511  def : MipsPat<(MipsTruncIntFP FGR64:$src), (TRUNC_W_D64 FGR64:$src)>;
512  def : MipsPat<(MipsTruncIntFP FGR32:$src), (TRUNC_L_S FGR32:$src)>;
513  def : MipsPat<(MipsTruncIntFP FGR64:$src), (TRUNC_L_D64 FGR64:$src)>;
514
515  def : MipsPat<(f32 (fround FGR64:$src)), (CVT_S_D64 FGR64:$src)>;
516  def : MipsPat<(f64 (fextend FGR32:$src)), (CVT_D64_S FGR32:$src)>;
517}
518
519// Patterns for loads/stores with a reg+imm operand.
520let AddedComplexity = 40 in {
521  let Predicates = [IsN64, HasStdEnc] in {
522    def : LoadRegImmPat<LWC1_P8, f32, load>;
523    def : StoreRegImmPat<SWC1_P8, f32>;
524    def : LoadRegImmPat<LDC164_P8, f64, load>;
525    def : StoreRegImmPat<SDC164_P8, f64>;
526  }
527
528  let Predicates = [NotN64, HasStdEnc] in {
529    def : LoadRegImmPat<LWC1, f32, load>;
530    def : StoreRegImmPat<SWC1, f32>;
531  }
532
533  let Predicates = [NotN64, HasMips64, HasStdEnc] in {
534    def : LoadRegImmPat<LDC164, f64, load>;
535    def : StoreRegImmPat<SDC164, f64>;
536  }
537
538  let Predicates = [NotN64, NotMips64, HasStdEnc] in {
539    def : LoadRegImmPat<PseudoLDC1, f64, load>;
540    def : StoreRegImmPat<PseudoSDC1, f64>;
541  }
542}
543