MipsInstrFPU.td revision afcca55ff9475cdb97ec576847fc676e95397fb4
1//===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Mips FPU instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Floating Point Instructions 16// ------------------------ 17// * 64bit fp: 18// - 32 64-bit registers (default mode) 19// - 16 even 32-bit registers (32-bit compatible mode) for 20// single and double access. 21// * 32bit fp: 22// - 16 even 32-bit registers - single and double (aliased) 23// - 32 32-bit registers (within single-only mode) 24//===----------------------------------------------------------------------===// 25 26// Floating Point Compare and Branch 27def SDT_MipsFPBrcond : SDTypeProfile<0, 2, [SDTCisInt<0>, 28 SDTCisVT<1, OtherVT>]>; 29def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>, 30 SDTCisVT<2, i32>]>; 31def SDT_MipsCMovFP : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, 32 SDTCisSameAs<1, 2>]>; 33def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, 34 SDTCisVT<1, i32>, 35 SDTCisSameAs<1, 2>]>; 36def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, 37 SDTCisVT<1, f64>, 38 SDTCisVT<2, i32>]>; 39 40def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>; 41def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>; 42def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>; 43def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond, 44 [SDNPHasChain, SDNPOptInGlue]>; 45def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>; 46def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64", 47 SDT_MipsExtractElementF64>; 48 49// Operand for printing out a condition code. 50let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in 51 def condcode : Operand<i32>; 52 53//===----------------------------------------------------------------------===// 54// Feature predicates. 55//===----------------------------------------------------------------------===// 56 57def IsFP64bit : Predicate<"Subtarget.isFP64bit()">, 58 AssemblerPredicate<"FeatureFP64Bit">; 59def NotFP64bit : Predicate<"!Subtarget.isFP64bit()">, 60 AssemblerPredicate<"!FeatureFP64Bit">; 61def IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">, 62 AssemblerPredicate<"FeatureSingleFloat">; 63def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">, 64 AssemblerPredicate<"!FeatureSingleFloat">; 65 66// FP immediate patterns. 67def fpimm0 : PatLeaf<(fpimm), [{ 68 return N->isExactlyValue(+0.0); 69}]>; 70 71def fpimm0neg : PatLeaf<(fpimm), [{ 72 return N->isExactlyValue(-0.0); 73}]>; 74 75//===----------------------------------------------------------------------===// 76// Instruction Class Templates 77// 78// A set of multiclasses is used to address the register usage. 79// 80// S32 - single precision in 16 32bit even fp registers 81// single precision in 32 32bit fp registers in SingleOnly mode 82// S64 - single precision in 32 64bit fp registers (In64BitMode) 83// D32 - double precision in 16 32bit even fp registers 84// D64 - double precision in 32 64bit fp registers (In64BitMode) 85// 86// Only S32 and D32 are supported right now. 87//===----------------------------------------------------------------------===// 88 89class ADDS_FT<string opstr, RegisterClass RC, InstrItinClass Itin, bit IsComm, 90 SDPatternOperator OpNode= null_frag> : 91 InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft), 92 !strconcat(opstr, "\t$fd, $fs, $ft"), 93 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR> { 94 let isCommutable = IsComm; 95} 96 97multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm, 98 SDPatternOperator OpNode = null_frag> { 99 def _D32 : ADDS_FT<opstr, AFGR64, Itin, IsComm, OpNode>, 100 Requires<[NotFP64bit, HasStdEnc]>; 101 def _D64 : ADDS_FT<opstr, FGR64, Itin, IsComm, OpNode>, 102 Requires<[IsFP64bit, HasStdEnc]> { 103 string DecoderNamespace = "Mips64"; 104 } 105} 106 107class ABSS_FT<string opstr, RegisterClass DstRC, RegisterClass SrcRC, 108 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 109 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"), 110 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR>, 111 NeverHasSideEffects; 112 113multiclass ABSS_M<string opstr, InstrItinClass Itin, 114 SDPatternOperator OpNode= null_frag> { 115 def _D32 : ABSS_FT<opstr, AFGR64, AFGR64, Itin, OpNode>, 116 Requires<[NotFP64bit, HasStdEnc]>; 117 def _D64 : ABSS_FT<opstr, FGR64, FGR64, Itin, OpNode>, 118 Requires<[IsFP64bit, HasStdEnc]> { 119 string DecoderNamespace = "Mips64"; 120 } 121} 122 123multiclass ROUND_M<string opstr, InstrItinClass Itin> { 124 def _D32 : ABSS_FT<opstr, FGR32, AFGR64, Itin>, 125 Requires<[NotFP64bit, HasStdEnc]>; 126 def _D64 : ABSS_FT<opstr, FGR32, FGR64, Itin>, 127 Requires<[IsFP64bit, HasStdEnc]> { 128 let DecoderNamespace = "Mips64"; 129 } 130} 131 132class MFC1_FT<string opstr, RegisterClass DstRC, RegisterClass SrcRC, 133 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 134 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"), 135 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR>; 136 137class MTC1_FT<string opstr, RegisterClass DstRC, RegisterClass SrcRC, 138 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 139 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"), 140 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR>; 141 142class MFC1_FT_CCR<string opstr, RegisterClass DstRC, RegisterOperand SrcRC, 143 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 144 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"), 145 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR>; 146 147class MTC1_FT_CCR<string opstr, RegisterOperand DstRC, RegisterClass SrcRC, 148 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 149 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"), 150 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR>; 151 152class LW_FT<string opstr, RegisterClass RC, InstrItinClass Itin, 153 Operand MemOpnd, SDPatternOperator OpNode= null_frag> : 154 InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 155 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI> { 156 let DecoderMethod = "DecodeFMem"; 157 let mayLoad = 1; 158} 159 160class SW_FT<string opstr, RegisterClass RC, InstrItinClass Itin, 161 Operand MemOpnd, SDPatternOperator OpNode= null_frag> : 162 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 163 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI> { 164 let DecoderMethod = "DecodeFMem"; 165 let mayStore = 1; 166} 167 168class MADDS_FT<string opstr, RegisterClass RC, InstrItinClass Itin, 169 SDPatternOperator OpNode = null_frag> : 170 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft), 171 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"), 172 [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))], Itin, FrmFR>; 173 174class NMADDS_FT<string opstr, RegisterClass RC, InstrItinClass Itin, 175 SDPatternOperator OpNode = null_frag> : 176 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft), 177 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"), 178 [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))], 179 Itin, FrmFR>; 180 181class LWXC1_FT<string opstr, RegisterClass DRC, RegisterClass PRC, 182 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> : 183 InstSE<(outs DRC:$fd), (ins PRC:$base, PRC:$index), 184 !strconcat(opstr, "\t$fd, ${index}(${base})"), 185 [(set DRC:$fd, (OpNode (add PRC:$base, PRC:$index)))], Itin, FrmFI> { 186 let AddedComplexity = 20; 187} 188 189class SWXC1_FT<string opstr, RegisterClass DRC, RegisterClass PRC, 190 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> : 191 InstSE<(outs), (ins DRC:$fs, PRC:$base, PRC:$index), 192 !strconcat(opstr, "\t$fs, ${index}(${base})"), 193 [(OpNode DRC:$fs, (add PRC:$base, PRC:$index))], Itin, FrmFI> { 194 let AddedComplexity = 20; 195} 196 197class BC1F_FT<string opstr, InstrItinClass Itin, 198 SDPatternOperator Op = null_frag> : 199 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"), 200 [(MipsFPBrcond Op, bb:$offset)], Itin, FrmFI> { 201 let isBranch = 1; 202 let isTerminator = 1; 203 let hasDelaySlot = 1; 204 let Defs = [AT]; 205 let Uses = [FCR31]; 206} 207 208class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin, 209 SDPatternOperator OpNode = null_frag> : 210 InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond), 211 !strconcat("c.$cond.", typestr, "\t$fs, $ft"), 212 [(OpNode RC:$fs, RC:$ft, imm:$cond)], Itin, FrmFR> { 213 let Defs = [FCR31]; 214} 215 216//===----------------------------------------------------------------------===// 217// Floating Point Instructions 218//===----------------------------------------------------------------------===// 219def ROUND_W_S : ABSS_FT<"round.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xc, 16>; 220def TRUNC_W_S : ABSS_FT<"trunc.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xd, 16>; 221def CEIL_W_S : ABSS_FT<"ceil.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xe, 16>; 222def FLOOR_W_S : ABSS_FT<"floor.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xf, 16>; 223def CVT_W_S : ABSS_FT<"cvt.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0x24, 16>; 224 225defm ROUND_W : ROUND_M<"round.w.d", IIFcvt>, ABSS_FM<0xc, 17>; 226defm TRUNC_W : ROUND_M<"trunc.w.d", IIFcvt>, ABSS_FM<0xd, 17>; 227defm CEIL_W : ROUND_M<"ceil.w.d", IIFcvt>, ABSS_FM<0xe, 17>; 228defm FLOOR_W : ROUND_M<"floor.w.d", IIFcvt>, ABSS_FM<0xf, 17>; 229defm CVT_W : ROUND_M<"cvt.w.d", IIFcvt>, ABSS_FM<0x24, 17>; 230 231let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in { 232 def ROUND_L_S : ABSS_FT<"round.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x8, 16>; 233 def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64, FGR64, IIFcvt>, 234 ABSS_FM<0x8, 17>; 235 def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x9, 16>; 236 def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64, FGR64, IIFcvt>, 237 ABSS_FM<0x9, 17>; 238 def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0xa, 16>; 239 def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64, FGR64, IIFcvt>, ABSS_FM<0xa, 17>; 240 def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0xb, 16>; 241 def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64, FGR64, IIFcvt>, 242 ABSS_FM<0xb, 17>; 243} 244 245def CVT_S_W : ABSS_FT<"cvt.s.w", FGR32, FGR32, IIFcvt>, ABSS_FM<0x20, 20>; 246def CVT_L_S : ABSS_FT<"cvt.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x25, 16>; 247def CVT_L_D64: ABSS_FT<"cvt.l.d", FGR64, FGR64, IIFcvt>, ABSS_FM<0x25, 17>; 248 249let Predicates = [NotFP64bit, HasStdEnc] in { 250 def CVT_S_D32 : ABSS_FT<"cvt.s.d", FGR32, AFGR64, IIFcvt>, ABSS_FM<0x20, 17>; 251 def CVT_D32_W : ABSS_FT<"cvt.d.w", AFGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 20>; 252 def CVT_D32_S : ABSS_FT<"cvt.d.s", AFGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 16>; 253} 254 255let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in { 256 def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32, FGR64, IIFcvt>, ABSS_FM<0x20, 17>; 257 def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32, FGR64, IIFcvt>, ABSS_FM<0x20, 21>; 258 def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 20>; 259 def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 16>; 260 def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64, FGR64, IIFcvt>, ABSS_FM<0x21, 21>; 261} 262 263let Predicates = [NoNaNsFPMath, HasStdEnc] in { 264 def FABS_S : ABSS_FT<"abs.s", FGR32, FGR32, IIFcvt, fabs>, ABSS_FM<0x5, 16>; 265 def FNEG_S : ABSS_FT<"neg.s", FGR32, FGR32, IIFcvt, fneg>, ABSS_FM<0x7, 16>; 266 defm FABS : ABSS_M<"abs.d", IIFcvt, fabs>, ABSS_FM<0x5, 17>; 267 defm FNEG : ABSS_M<"neg.d", IIFcvt, fneg>, ABSS_FM<0x7, 17>; 268} 269 270def FSQRT_S : ABSS_FT<"sqrt.s", FGR32, FGR32, IIFsqrtSingle, fsqrt>, 271 ABSS_FM<0x4, 16>; 272defm FSQRT : ABSS_M<"sqrt.d", IIFsqrtDouble, fsqrt>, ABSS_FM<0x4, 17>; 273 274// The odd-numbered registers are only referenced when doing loads, 275// stores, and moves between floating-point and integer registers. 276// When defining instructions, we reference all 32-bit registers, 277// regardless of register aliasing. 278 279/// Move Control Registers From/To CPU Registers 280def CFC1 : MFC1_FT_CCR<"cfc1", CPURegs, CCROpnd, IIFmove>, MFC1_FM<2>; 281def CTC1 : MTC1_FT_CCR<"ctc1", CCROpnd, CPURegs, IIFmove>, MFC1_FM<6>; 282def MFC1 : MFC1_FT<"mfc1", CPURegs, FGR32, IIFmove, bitconvert>, MFC1_FM<0>; 283def MTC1 : MTC1_FT<"mtc1", FGR32, CPURegs, IIFmove, bitconvert>, MFC1_FM<4>; 284def DMFC1 : MFC1_FT<"dmfc1", CPU64Regs, FGR64, IIFmove, bitconvert>, MFC1_FM<1>; 285def DMTC1 : MTC1_FT<"dmtc1", FGR64, CPU64Regs, IIFmove, bitconvert>, MFC1_FM<5>; 286 287def FMOV_S : ABSS_FT<"mov.s", FGR32, FGR32, IIFmove>, ABSS_FM<0x6, 16>; 288def FMOV_D32 : ABSS_FT<"mov.d", AFGR64, AFGR64, IIFmove>, ABSS_FM<0x6, 17>, 289 Requires<[NotFP64bit, HasStdEnc]>; 290def FMOV_D64 : ABSS_FT<"mov.d", FGR64, FGR64, IIFmove>, ABSS_FM<0x6, 17>, 291 Requires<[IsFP64bit, HasStdEnc]> { 292 let DecoderNamespace = "Mips64"; 293} 294 295/// Floating Point Memory Instructions 296let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in { 297 def LWC1_P8 : LW_FT<"lwc1", FGR32, IILoad, mem64, load>, LW_FM<0x31>; 298 def SWC1_P8 : SW_FT<"swc1", FGR32, IIStore, mem64, store>, LW_FM<0x39>; 299 def LDC164_P8 : LW_FT<"ldc1", FGR64, IILoad, mem64, load>, LW_FM<0x35> { 300 let isCodeGenOnly =1; 301 } 302 def SDC164_P8 : SW_FT<"sdc1", FGR64, IIStore, mem64, store>, LW_FM<0x3d> { 303 let isCodeGenOnly =1; 304 } 305} 306 307let Predicates = [NotN64, HasStdEnc] in { 308 def LWC1 : LW_FT<"lwc1", FGR32, IILoad, mem, load>, LW_FM<0x31>; 309 def SWC1 : SW_FT<"swc1", FGR32, IIStore, mem, store>, LW_FM<0x39>; 310} 311 312let Predicates = [NotN64, HasMips64, HasStdEnc], 313 DecoderNamespace = "Mips64" in { 314 def LDC164 : LW_FT<"ldc1", FGR64, IILoad, mem, load>, LW_FM<0x35>; 315 def SDC164 : SW_FT<"sdc1", FGR64, IIStore, mem, store>, LW_FM<0x3d>; 316} 317 318let Predicates = [NotN64, NotMips64, HasStdEnc] in { 319 let isPseudo = 1, isCodeGenOnly = 1 in { 320 def PseudoLDC1 : LW_FT<"", AFGR64, IILoad, mem, load>; 321 def PseudoSDC1 : SW_FT<"", AFGR64, IIStore, mem, store>; 322 } 323 def LDC1 : LW_FT<"ldc1", AFGR64, IILoad, mem>, LW_FM<0x35>; 324 def SDC1 : SW_FT<"sdc1", AFGR64, IIStore, mem>, LW_FM<0x3d>; 325} 326 327// Indexed loads and stores. 328let Predicates = [HasFPIdx, HasStdEnc] in { 329 def LWXC1 : LWXC1_FT<"lwxc1", FGR32, CPURegs, IILoad, load>, LWXC1_FM<0>; 330 def SWXC1 : SWXC1_FT<"swxc1", FGR32, CPURegs, IIStore, store>, SWXC1_FM<8>; 331} 332 333let Predicates = [HasMips32r2, NotMips64, HasStdEnc] in { 334 def LDXC1 : LWXC1_FT<"ldxc1", AFGR64, CPURegs, IILoad, load>, LWXC1_FM<1>; 335 def SDXC1 : SWXC1_FT<"sdxc1", AFGR64, CPURegs, IIStore, store>, SWXC1_FM<9>; 336} 337 338let Predicates = [HasMips64, NotN64, HasStdEnc], DecoderNamespace="Mips64" in { 339 def LDXC164 : LWXC1_FT<"ldxc1", FGR64, CPURegs, IILoad, load>, LWXC1_FM<1>; 340 def SDXC164 : SWXC1_FT<"sdxc1", FGR64, CPURegs, IIStore, store>, SWXC1_FM<9>; 341} 342 343// n64 344let Predicates = [IsN64, HasStdEnc], isCodeGenOnly=1 in { 345 def LWXC1_P8 : LWXC1_FT<"lwxc1", FGR32, CPU64Regs, IILoad, load>, LWXC1_FM<0>; 346 def LDXC164_P8 : LWXC1_FT<"ldxc1", FGR64, CPU64Regs, IILoad, load>, 347 LWXC1_FM<1>; 348 def SWXC1_P8 : SWXC1_FT<"swxc1", FGR32, CPU64Regs, IIStore, store>, 349 SWXC1_FM<8>; 350 def SDXC164_P8 : SWXC1_FT<"sdxc1", FGR64, CPU64Regs, IIStore, store>, 351 SWXC1_FM<9>; 352} 353 354// Load/store doubleword indexed unaligned. 355let Predicates = [NotMips64, HasStdEnc] in { 356 def LUXC1 : LWXC1_FT<"luxc1", AFGR64, CPURegs, IILoad>, LWXC1_FM<0x5>; 357 def SUXC1 : SWXC1_FT<"suxc1", AFGR64, CPURegs, IIStore>, SWXC1_FM<0xd>; 358} 359 360let Predicates = [HasMips64, HasStdEnc], 361 DecoderNamespace="Mips64" in { 362 def LUXC164 : LWXC1_FT<"luxc1", FGR64, CPURegs, IILoad>, LWXC1_FM<0x5>; 363 def SUXC164 : SWXC1_FT<"suxc1", FGR64, CPURegs, IIStore>, SWXC1_FM<0xd>; 364} 365 366/// Floating-point Aritmetic 367def FADD_S : ADDS_FT<"add.s", FGR32, IIFadd, 1, fadd>, ADDS_FM<0x00, 16>; 368defm FADD : ADDS_M<"add.d", IIFadd, 1, fadd>, ADDS_FM<0x00, 17>; 369def FDIV_S : ADDS_FT<"div.s", FGR32, IIFdivSingle, 0, fdiv>, ADDS_FM<0x03, 16>; 370defm FDIV : ADDS_M<"div.d", IIFdivDouble, 0, fdiv>, ADDS_FM<0x03, 17>; 371def FMUL_S : ADDS_FT<"mul.s", FGR32, IIFmulSingle, 1, fmul>, ADDS_FM<0x02, 16>; 372defm FMUL : ADDS_M<"mul.d", IIFmulDouble, 1, fmul>, ADDS_FM<0x02, 17>; 373def FSUB_S : ADDS_FT<"sub.s", FGR32, IIFadd, 0, fsub>, ADDS_FM<0x01, 16>; 374defm FSUB : ADDS_M<"sub.d", IIFadd, 0, fsub>, ADDS_FM<0x01, 17>; 375 376let Predicates = [HasMips32r2, HasStdEnc] in { 377 def MADD_S : MADDS_FT<"madd.s", FGR32, IIFmulSingle, fadd>, MADDS_FM<4, 0>; 378 def MSUB_S : MADDS_FT<"msub.s", FGR32, IIFmulSingle, fsub>, MADDS_FM<5, 0>; 379} 380 381let Predicates = [HasMips32r2, NoNaNsFPMath, HasStdEnc] in { 382 def NMADD_S : NMADDS_FT<"nmadd.s", FGR32, IIFmulSingle, fadd>, MADDS_FM<6, 0>; 383 def NMSUB_S : NMADDS_FT<"nmsub.s", FGR32, IIFmulSingle, fsub>, MADDS_FM<7, 0>; 384} 385 386let Predicates = [HasMips32r2, NotFP64bit, HasStdEnc] in { 387 def MADD_D32 : MADDS_FT<"madd.d", AFGR64, IIFmulDouble, fadd>, MADDS_FM<4, 1>; 388 def MSUB_D32 : MADDS_FT<"msub.d", AFGR64, IIFmulDouble, fsub>, MADDS_FM<5, 1>; 389} 390 391let Predicates = [HasMips32r2, NotFP64bit, NoNaNsFPMath, HasStdEnc] in { 392 def NMADD_D32 : NMADDS_FT<"nmadd.d", AFGR64, IIFmulDouble, fadd>, 393 MADDS_FM<6, 1>; 394 def NMSUB_D32 : NMADDS_FT<"nmsub.d", AFGR64, IIFmulDouble, fsub>, 395 MADDS_FM<7, 1>; 396} 397 398let Predicates = [HasMips32r2, IsFP64bit, HasStdEnc], isCodeGenOnly=1 in { 399 def MADD_D64 : MADDS_FT<"madd.d", FGR64, IIFmulDouble, fadd>, MADDS_FM<4, 1>; 400 def MSUB_D64 : MADDS_FT<"msub.d", FGR64, IIFmulDouble, fsub>, MADDS_FM<5, 1>; 401} 402 403let Predicates = [HasMips32r2, IsFP64bit, NoNaNsFPMath, HasStdEnc], 404 isCodeGenOnly=1 in { 405 def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64, IIFmulDouble, fadd>, 406 MADDS_FM<6, 1>; 407 def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64, IIFmulDouble, fsub>, 408 MADDS_FM<7, 1>; 409} 410 411//===----------------------------------------------------------------------===// 412// Floating Point Branch Codes 413//===----------------------------------------------------------------------===// 414// Mips branch codes. These correspond to condcode in MipsInstrInfo.h. 415// They must be kept in synch. 416def MIPS_BRANCH_F : PatLeaf<(i32 0)>; 417def MIPS_BRANCH_T : PatLeaf<(i32 1)>; 418 419let DecoderMethod = "DecodeBC1" in { 420def BC1F : BC1F_FT<"bc1f", IIBranch, MIPS_BRANCH_F>, BC1F_FM<0, 0>; 421def BC1T : BC1F_FT<"bc1t", IIBranch, MIPS_BRANCH_T>, BC1F_FM<0, 1>; 422} 423//===----------------------------------------------------------------------===// 424// Floating Point Flag Conditions 425//===----------------------------------------------------------------------===// 426// Mips condition codes. They must correspond to condcode in MipsInstrInfo.h. 427// They must be kept in synch. 428def MIPS_FCOND_F : PatLeaf<(i32 0)>; 429def MIPS_FCOND_UN : PatLeaf<(i32 1)>; 430def MIPS_FCOND_OEQ : PatLeaf<(i32 2)>; 431def MIPS_FCOND_UEQ : PatLeaf<(i32 3)>; 432def MIPS_FCOND_OLT : PatLeaf<(i32 4)>; 433def MIPS_FCOND_ULT : PatLeaf<(i32 5)>; 434def MIPS_FCOND_OLE : PatLeaf<(i32 6)>; 435def MIPS_FCOND_ULE : PatLeaf<(i32 7)>; 436def MIPS_FCOND_SF : PatLeaf<(i32 8)>; 437def MIPS_FCOND_NGLE : PatLeaf<(i32 9)>; 438def MIPS_FCOND_SEQ : PatLeaf<(i32 10)>; 439def MIPS_FCOND_NGL : PatLeaf<(i32 11)>; 440def MIPS_FCOND_LT : PatLeaf<(i32 12)>; 441def MIPS_FCOND_NGE : PatLeaf<(i32 13)>; 442def MIPS_FCOND_LE : PatLeaf<(i32 14)>; 443def MIPS_FCOND_NGT : PatLeaf<(i32 15)>; 444 445/// Floating Point Compare 446def FCMP_S32 : CEQS_FT<"s", FGR32, IIFcmp, MipsFPCmp>, CEQS_FM<16>; 447def FCMP_D32 : CEQS_FT<"d", AFGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>, 448 Requires<[NotFP64bit, HasStdEnc]>; 449let DecoderNamespace = "Mips64" in 450def FCMP_D64 : CEQS_FT<"d", FGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>, 451 Requires<[IsFP64bit, HasStdEnc]>; 452 453//===----------------------------------------------------------------------===// 454// Floating Point Pseudo-Instructions 455//===----------------------------------------------------------------------===// 456def MOVCCRToCCR : PseudoSE<(outs CCR:$dst), (ins CCROpnd:$src), []>; 457 458// This pseudo instr gets expanded into 2 mtc1 instrs after register 459// allocation. 460def BuildPairF64 : 461 PseudoSE<(outs AFGR64:$dst), 462 (ins CPURegs:$lo, CPURegs:$hi), 463 [(set AFGR64:$dst, (MipsBuildPairF64 CPURegs:$lo, CPURegs:$hi))]>; 464 465// This pseudo instr gets expanded into 2 mfc1 instrs after register 466// allocation. 467// if n is 0, lower part of src is extracted. 468// if n is 1, higher part of src is extracted. 469def ExtractElementF64 : 470 PseudoSE<(outs CPURegs:$dst), (ins AFGR64:$src, i32imm:$n), 471 [(set CPURegs:$dst, (MipsExtractElementF64 AFGR64:$src, imm:$n))]>; 472 473//===----------------------------------------------------------------------===// 474// Floating Point Patterns 475//===----------------------------------------------------------------------===// 476def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>; 477def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>; 478 479def : MipsPat<(f32 (sint_to_fp CPURegs:$src)), (CVT_S_W (MTC1 CPURegs:$src))>; 480def : MipsPat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S FGR32:$src))>; 481 482let Predicates = [NotFP64bit, HasStdEnc] in { 483 def : MipsPat<(f64 (sint_to_fp CPURegs:$src)), 484 (CVT_D32_W (MTC1 CPURegs:$src))>; 485 def : MipsPat<(i32 (fp_to_sint AFGR64:$src)), 486 (MFC1 (TRUNC_W_D32 AFGR64:$src))>; 487 def : MipsPat<(f32 (fround AFGR64:$src)), (CVT_S_D32 AFGR64:$src)>; 488 def : MipsPat<(f64 (fextend FGR32:$src)), (CVT_D32_S FGR32:$src)>; 489} 490 491let Predicates = [IsFP64bit, HasStdEnc] in { 492 def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>; 493 def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>; 494 495 def : MipsPat<(f64 (sint_to_fp CPURegs:$src)), 496 (CVT_D64_W (MTC1 CPURegs:$src))>; 497 def : MipsPat<(f32 (sint_to_fp CPU64Regs:$src)), 498 (CVT_S_L (DMTC1 CPU64Regs:$src))>; 499 def : MipsPat<(f64 (sint_to_fp CPU64Regs:$src)), 500 (CVT_D64_L (DMTC1 CPU64Regs:$src))>; 501 502 def : MipsPat<(i32 (fp_to_sint FGR64:$src)), 503 (MFC1 (TRUNC_W_D64 FGR64:$src))>; 504 def : MipsPat<(i64 (fp_to_sint FGR32:$src)), (DMFC1 (TRUNC_L_S FGR32:$src))>; 505 def : MipsPat<(i64 (fp_to_sint FGR64:$src)), 506 (DMFC1 (TRUNC_L_D64 FGR64:$src))>; 507 508 def : MipsPat<(f32 (fround FGR64:$src)), (CVT_S_D64 FGR64:$src)>; 509 def : MipsPat<(f64 (fextend FGR32:$src)), (CVT_D64_S FGR32:$src)>; 510} 511 512// Patterns for loads/stores with a reg+imm operand. 513let AddedComplexity = 40 in { 514 let Predicates = [IsN64, HasStdEnc] in { 515 def : LoadRegImmPat<LWC1_P8, f32, load>; 516 def : StoreRegImmPat<SWC1_P8, f32>; 517 def : LoadRegImmPat<LDC164_P8, f64, load>; 518 def : StoreRegImmPat<SDC164_P8, f64>; 519 } 520 521 let Predicates = [NotN64, HasStdEnc] in { 522 def : LoadRegImmPat<LWC1, f32, load>; 523 def : StoreRegImmPat<SWC1, f32>; 524 } 525 526 let Predicates = [NotN64, HasMips64, HasStdEnc] in { 527 def : LoadRegImmPat<LDC164, f64, load>; 528 def : StoreRegImmPat<SDC164, f64>; 529 } 530 531 let Predicates = [NotN64, NotMips64, HasStdEnc] in { 532 def : LoadRegImmPat<PseudoLDC1, f64, load>; 533 def : StoreRegImmPat<PseudoSDC1, f64>; 534 } 535} 536