MipsInstrFPU.td revision b1f4f120a50c392c85c6b4388d63e36251fce279
1//===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Mips FPU instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Floating Point Instructions 16// ------------------------ 17// * 64bit fp: 18// - 32 64-bit registers (default mode) 19// - 16 even 32-bit registers (32-bit compatible mode) for 20// single and double access. 21// * 32bit fp: 22// - 16 even 32-bit registers - single and double (aliased) 23// - 32 32-bit registers (within single-only mode) 24//===----------------------------------------------------------------------===// 25 26// Floating Point Compare and Branch 27def SDT_MipsFPBrcond : SDTypeProfile<0, 3, [SDTCisInt<0>, 28 SDTCisVT<1, i32>, 29 SDTCisVT<2, OtherVT>]>; 30def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>, 31 SDTCisVT<2, i32>]>; 32def SDT_MipsCMovFP : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisVT<2, i32>, 33 SDTCisSameAs<1, 3>]>; 34def SDT_MipsTruncIntFP : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>; 35def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, 36 SDTCisVT<1, i32>, 37 SDTCisSameAs<1, 2>]>; 38def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, 39 SDTCisVT<1, f64>, 40 SDTCisVT<2, i32>]>; 41 42def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>; 43def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>; 44def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>; 45def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond, 46 [SDNPHasChain, SDNPOptInGlue]>; 47def MipsTruncIntFP : SDNode<"MipsISD::TruncIntFP", SDT_MipsTruncIntFP>; 48def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>; 49def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64", 50 SDT_MipsExtractElementF64>; 51 52// Operand for printing out a condition code. 53let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in 54 def condcode : Operand<i32>; 55 56//===----------------------------------------------------------------------===// 57// Feature predicates. 58//===----------------------------------------------------------------------===// 59 60def IsFP64bit : Predicate<"Subtarget.isFP64bit()">, 61 AssemblerPredicate<"FeatureFP64Bit">; 62def NotFP64bit : Predicate<"!Subtarget.isFP64bit()">, 63 AssemblerPredicate<"!FeatureFP64Bit">; 64def IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">, 65 AssemblerPredicate<"FeatureSingleFloat">; 66def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">, 67 AssemblerPredicate<"!FeatureSingleFloat">; 68 69// FP immediate patterns. 70def fpimm0 : PatLeaf<(fpimm), [{ 71 return N->isExactlyValue(+0.0); 72}]>; 73 74def fpimm0neg : PatLeaf<(fpimm), [{ 75 return N->isExactlyValue(-0.0); 76}]>; 77 78//===----------------------------------------------------------------------===// 79// Instruction Class Templates 80// 81// A set of multiclasses is used to address the register usage. 82// 83// S32 - single precision in 16 32bit even fp registers 84// single precision in 32 32bit fp registers in SingleOnly mode 85// S64 - single precision in 32 64bit fp registers (In64BitMode) 86// D32 - double precision in 16 32bit even fp registers 87// D64 - double precision in 32 64bit fp registers (In64BitMode) 88// 89// Only S32 and D32 are supported right now. 90//===----------------------------------------------------------------------===// 91 92class ADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, bit IsComm, 93 SDPatternOperator OpNode= null_frag> : 94 InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft), 95 !strconcat(opstr, "\t$fd, $fs, $ft"), 96 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR> { 97 let isCommutable = IsComm; 98} 99 100multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm, 101 SDPatternOperator OpNode = null_frag> { 102 def _D32 : ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>, 103 Requires<[NotFP64bit, HasStdEnc]>; 104 def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin, IsComm, OpNode>, 105 Requires<[IsFP64bit, HasStdEnc]> { 106 string DecoderNamespace = "Mips64"; 107 } 108} 109 110class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 111 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 112 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"), 113 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR>, 114 NeverHasSideEffects; 115 116multiclass ABSS_M<string opstr, InstrItinClass Itin, 117 SDPatternOperator OpNode= null_frag> { 118 def _D32 : ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>, 119 Requires<[NotFP64bit, HasStdEnc]>; 120 def _D64 : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>, 121 Requires<[IsFP64bit, HasStdEnc]> { 122 string DecoderNamespace = "Mips64"; 123 } 124} 125 126multiclass ROUND_M<string opstr, InstrItinClass Itin> { 127 def _D32 : ABSS_FT<opstr, FGR32Opnd, AFGR64Opnd, Itin>, 128 Requires<[NotFP64bit, HasStdEnc]>; 129 def _D64 : ABSS_FT<opstr, FGR32Opnd, FGR64Opnd, Itin>, 130 Requires<[IsFP64bit, HasStdEnc]> { 131 let DecoderNamespace = "Mips64"; 132 } 133} 134 135class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 136 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 137 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"), 138 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR>; 139 140class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 141 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 142 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"), 143 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR>; 144 145class LW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 146 SDPatternOperator OpNode= null_frag> : 147 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 148 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI> { 149 let DecoderMethod = "DecodeFMem"; 150 let mayLoad = 1; 151} 152 153class SW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 154 SDPatternOperator OpNode= null_frag> : 155 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 156 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI> { 157 let DecoderMethod = "DecodeFMem"; 158 let mayStore = 1; 159} 160 161class MADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 162 SDPatternOperator OpNode = null_frag> : 163 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft), 164 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"), 165 [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))], Itin, FrmFR>; 166 167class NMADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 168 SDPatternOperator OpNode = null_frag> : 169 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft), 170 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"), 171 [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))], 172 Itin, FrmFR>; 173 174class LWXC1_FT<string opstr, RegisterOperand DRC, RegisterOperand PRC, 175 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> : 176 InstSE<(outs DRC:$fd), (ins PRC:$base, PRC:$index), 177 !strconcat(opstr, "\t$fd, ${index}(${base})"), 178 [(set DRC:$fd, (OpNode (add PRC:$base, PRC:$index)))], Itin, FrmFI> { 179 let AddedComplexity = 20; 180} 181 182class SWXC1_FT<string opstr, RegisterOperand DRC, RegisterOperand PRC, 183 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> : 184 InstSE<(outs), (ins DRC:$fs, PRC:$base, PRC:$index), 185 !strconcat(opstr, "\t$fs, ${index}(${base})"), 186 [(OpNode DRC:$fs, (add PRC:$base, PRC:$index))], Itin, FrmFI> { 187 let AddedComplexity = 20; 188} 189 190class BC1F_FT<string opstr, InstrItinClass Itin, 191 SDPatternOperator Op = null_frag> : 192 InstSE<(outs), (ins FCCRegsOpnd:$fcc, brtarget:$offset), 193 !strconcat(opstr, "\t$fcc, $offset"), 194 [(MipsFPBrcond Op, FCCRegsOpnd:$fcc, bb:$offset)], Itin, FrmFI> { 195 let isBranch = 1; 196 let isTerminator = 1; 197 let hasDelaySlot = 1; 198 let Defs = [AT]; 199} 200 201class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin, 202 SDPatternOperator OpNode = null_frag> : 203 InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond), 204 !strconcat("c.$cond.", typestr, "\t$fs, $ft"), 205 [(OpNode RC:$fs, RC:$ft, imm:$cond)], Itin, FrmFR> { 206 let Defs = [FCC0]; 207 let isCodeGenOnly = 1; 208} 209 210class C_COND_FT<string CondStr, string Typestr, RegisterOperand RC> : 211 InstSE<(outs), (ins RC:$fs, RC:$ft), 212 !strconcat("c.", CondStr, ".", Typestr, "\t$fs, $ft"), [], IIFcmp, 213 FrmFR>; 214 215multiclass C_COND_M<string TypeStr, RegisterOperand RC, bits<5> fmt> { 216 def C_F_#NAME : C_COND_FT<"f", TypeStr, RC>, C_COND_FM<fmt, 0>; 217 def C_UN_#NAME : C_COND_FT<"un", TypeStr, RC>, C_COND_FM<fmt, 1>; 218 def C_EQ_#NAME : C_COND_FT<"eq", TypeStr, RC>, C_COND_FM<fmt, 2>; 219 def C_UEQ_#NAME : C_COND_FT<"ueq", TypeStr, RC>, C_COND_FM<fmt, 3>; 220 def C_OLT_#NAME : C_COND_FT<"olt", TypeStr, RC>, C_COND_FM<fmt, 4>; 221 def C_ULT_#NAME : C_COND_FT<"ult", TypeStr, RC>, C_COND_FM<fmt, 5>; 222 def C_OLE_#NAME : C_COND_FT<"ole", TypeStr, RC>, C_COND_FM<fmt, 6>; 223 def C_ULE_#NAME : C_COND_FT<"ule", TypeStr, RC>, C_COND_FM<fmt, 7>; 224 def C_SF_#NAME : C_COND_FT<"sf", TypeStr, RC>, C_COND_FM<fmt, 8>; 225 def C_NGLE_#NAME : C_COND_FT<"ngle", TypeStr, RC>, C_COND_FM<fmt, 9>; 226 def C_SEQ_#NAME : C_COND_FT<"seq", TypeStr, RC>, C_COND_FM<fmt, 10>; 227 def C_NGL_#NAME : C_COND_FT<"ngl", TypeStr, RC>, C_COND_FM<fmt, 11>; 228 def C_LT_#NAME : C_COND_FT<"lt", TypeStr, RC>, C_COND_FM<fmt, 12>; 229 def C_NGE_#NAME : C_COND_FT<"nge", TypeStr, RC>, C_COND_FM<fmt, 13>; 230 def C_LE_#NAME : C_COND_FT<"le", TypeStr, RC>, C_COND_FM<fmt, 14>; 231 def C_NGT_#NAME : C_COND_FT<"ngt", TypeStr, RC>, C_COND_FM<fmt, 15>; 232} 233 234defm S : C_COND_M<"s", FGR32Opnd, 16>; 235defm D32 : C_COND_M<"d", AFGR64Opnd, 17>, 236 Requires<[NotFP64bit, HasStdEnc]>; 237let DecoderNamespace = "Mips64" in 238defm D64 : C_COND_M<"d", FGR64Opnd, 17>, Requires<[IsFP64bit, HasStdEnc]>; 239 240//===----------------------------------------------------------------------===// 241// Floating Point Instructions 242//===----------------------------------------------------------------------===// 243def ROUND_W_S : ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>, 244 ABSS_FM<0xc, 16>; 245def TRUNC_W_S : ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>, 246 ABSS_FM<0xd, 16>; 247def CEIL_W_S : ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>, 248 ABSS_FM<0xe, 16>; 249def FLOOR_W_S : ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>, 250 ABSS_FM<0xf, 16>; 251def CVT_W_S : ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>, 252 ABSS_FM<0x24, 16>; 253 254defm ROUND_W : ROUND_M<"round.w.d", IIFcvt>, ABSS_FM<0xc, 17>; 255defm TRUNC_W : ROUND_M<"trunc.w.d", IIFcvt>, ABSS_FM<0xd, 17>; 256defm CEIL_W : ROUND_M<"ceil.w.d", IIFcvt>, ABSS_FM<0xe, 17>; 257defm FLOOR_W : ROUND_M<"floor.w.d", IIFcvt>, ABSS_FM<0xf, 17>; 258defm CVT_W : ROUND_M<"cvt.w.d", IIFcvt>, ABSS_FM<0x24, 17>; 259 260let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in { 261 def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, IIFcvt>, 262 ABSS_FM<0x8, 16>; 263 def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, IIFcvt>, 264 ABSS_FM<0x8, 17>; 265 def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64Opnd, FGR32Opnd, IIFcvt>, 266 ABSS_FM<0x9, 16>; 267 def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64Opnd, FGR64Opnd, IIFcvt>, 268 ABSS_FM<0x9, 17>; 269 def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64Opnd, FGR32Opnd, IIFcvt>, 270 ABSS_FM<0xa, 16>; 271 def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64Opnd, FGR64Opnd, IIFcvt>, 272 ABSS_FM<0xa, 17>; 273 def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64Opnd, FGR32Opnd, IIFcvt>, 274 ABSS_FM<0xb, 16>; 275 def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64Opnd, FGR64Opnd, IIFcvt>, 276 ABSS_FM<0xb, 17>; 277} 278 279def CVT_S_W : ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, IIFcvt>, 280 ABSS_FM<0x20, 20>; 281def CVT_L_S : ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, IIFcvt>, 282 ABSS_FM<0x25, 16>; 283def CVT_L_D64: ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, IIFcvt>, 284 ABSS_FM<0x25, 17>; 285 286let Predicates = [NotFP64bit, HasStdEnc] in { 287 def CVT_S_D32 : ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, IIFcvt>, 288 ABSS_FM<0x20, 17>; 289 def CVT_D32_W : ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, IIFcvt>, 290 ABSS_FM<0x21, 20>; 291 def CVT_D32_S : ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, IIFcvt>, 292 ABSS_FM<0x21, 16>; 293} 294 295let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in { 296 def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, IIFcvt>, 297 ABSS_FM<0x20, 17>; 298 def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, IIFcvt>, 299 ABSS_FM<0x20, 21>; 300 def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, IIFcvt>, 301 ABSS_FM<0x21, 20>; 302 def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, IIFcvt>, 303 ABSS_FM<0x21, 16>; 304 def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64Opnd, FGR64Opnd, IIFcvt>, 305 ABSS_FM<0x21, 21>; 306} 307 308let isPseudo = 1, isCodeGenOnly = 1 in { 309 def PseudoCVT_S_W : ABSS_FT<"", FGR32Opnd, GPR32Opnd, IIFcvt>; 310 def PseudoCVT_D32_W : ABSS_FT<"", AFGR64Opnd, GPR32Opnd, IIFcvt>; 311 def PseudoCVT_S_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, IIFcvt>; 312 def PseudoCVT_D64_W : ABSS_FT<"", FGR64Opnd, GPR32Opnd, IIFcvt>; 313 def PseudoCVT_D64_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, IIFcvt>; 314} 315 316let Predicates = [NoNaNsFPMath, HasStdEnc] in { 317 def FABS_S : ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, IIFcvt, fabs>, 318 ABSS_FM<0x5, 16>; 319 def FNEG_S : ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, IIFcvt, fneg>, 320 ABSS_FM<0x7, 16>; 321 defm FABS : ABSS_M<"abs.d", IIFcvt, fabs>, ABSS_FM<0x5, 17>; 322 defm FNEG : ABSS_M<"neg.d", IIFcvt, fneg>, ABSS_FM<0x7, 17>; 323} 324 325def FSQRT_S : ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, IIFsqrtSingle, 326 fsqrt>, ABSS_FM<0x4, 16>; 327defm FSQRT : ABSS_M<"sqrt.d", IIFsqrtDouble, fsqrt>, ABSS_FM<0x4, 17>; 328 329// The odd-numbered registers are only referenced when doing loads, 330// stores, and moves between floating-point and integer registers. 331// When defining instructions, we reference all 32-bit registers, 332// regardless of register aliasing. 333 334/// Move Control Registers From/To CPU Registers 335def CFC1 : MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, IIFmove>, MFC1_FM<2>; 336def CTC1 : MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, IIFmove>, MFC1_FM<6>; 337def MFC1 : MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, IIFmoveC1, bitconvert>, 338 MFC1_FM<0>; 339def MTC1 : MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, IIFmoveC1, bitconvert>, 340 MFC1_FM<4>; 341def MFHC1 : MFC1_FT<"mfhc1", GPR32Opnd, FGRH32Opnd, IIFmoveC1>, 342 MFC1_FM<3>; 343def MTHC1 : MTC1_FT<"mthc1", FGRH32Opnd, GPR32Opnd, IIFmoveC1>, 344 MFC1_FM<7>; 345def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, IIFmoveC1, 346 bitconvert>, MFC1_FM<1>; 347def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, IIFmoveC1, 348 bitconvert>, MFC1_FM<5>; 349 350def FMOV_S : ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, IIFmove>, 351 ABSS_FM<0x6, 16>; 352def FMOV_D32 : ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, IIFmove>, 353 ABSS_FM<0x6, 17>, Requires<[NotFP64bit, HasStdEnc]>; 354def FMOV_D64 : ABSS_FT<"mov.d", FGR64Opnd, FGR64Opnd, IIFmove>, 355 ABSS_FM<0x6, 17>, Requires<[IsFP64bit, HasStdEnc]> { 356 let DecoderNamespace = "Mips64"; 357} 358 359/// Floating Point Memory Instructions 360let Predicates = [HasStdEnc] in { 361 def LWC1 : LW_FT<"lwc1", FGR32Opnd, IIFLoad, load>, LW_FM<0x31>; 362 def SWC1 : SW_FT<"swc1", FGR32Opnd, IIFStore, store>, LW_FM<0x39>; 363} 364 365let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in { 366 def LDC164 : LW_FT<"ldc1", FGR64Opnd, IIFLoad, load>, LW_FM<0x35>; 367 def SDC164 : SW_FT<"sdc1", FGR64Opnd, IIFStore, store>, LW_FM<0x3d>; 368} 369 370let Predicates = [NotFP64bit, HasStdEnc] in { 371 let isPseudo = 1, isCodeGenOnly = 1 in { 372 def PseudoLDC1 : LW_FT<"", AFGR64Opnd, IIFLoad, load>; 373 def PseudoSDC1 : SW_FT<"", AFGR64Opnd, IIFStore, store>; 374 } 375 def LDC1 : LW_FT<"ldc1", AFGR64Opnd, IIFLoad>, LW_FM<0x35>; 376 def SDC1 : SW_FT<"sdc1", AFGR64Opnd, IIFStore>, LW_FM<0x3d>; 377} 378 379// Indexed loads and stores. 380let Predicates = [HasFPIdx, HasStdEnc] in { 381 def LWXC1 : LWXC1_FT<"lwxc1", FGR32Opnd, GPR32Opnd, IIFLoad, load>, 382 LWXC1_FM<0>; 383 def SWXC1 : SWXC1_FT<"swxc1", FGR32Opnd, GPR32Opnd, IIFStore, store>, 384 SWXC1_FM<8>; 385} 386 387let Predicates = [HasMips32r2, NotMips64, HasStdEnc] in { 388 def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, GPR32Opnd, IIFLoad, load>, 389 LWXC1_FM<1>; 390 def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, GPR32Opnd, IIFStore, store>, 391 SWXC1_FM<9>; 392} 393 394let Predicates = [HasMips64, NotN64, HasStdEnc], DecoderNamespace="Mips64" in { 395 def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, GPR32Opnd, IIFLoad, load>, 396 LWXC1_FM<1>; 397 def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, GPR32Opnd, IIFStore, store>, 398 SWXC1_FM<9>; 399} 400 401// n64 402let Predicates = [IsN64, HasStdEnc], isCodeGenOnly=1 in { 403 def LWXC1_P8 : LWXC1_FT<"lwxc1", FGR32Opnd, GPR64Opnd, IIFLoad, load>, 404 LWXC1_FM<0>; 405 def LDXC164_P8 : LWXC1_FT<"ldxc1", FGR64Opnd, GPR64Opnd, IIFLoad, 406 load>, LWXC1_FM<1>; 407 def SWXC1_P8 : SWXC1_FT<"swxc1", FGR32Opnd, GPR64Opnd, IIFStore, 408 store>, SWXC1_FM<8>; 409 def SDXC164_P8 : SWXC1_FT<"sdxc1", FGR64Opnd, GPR64Opnd, IIFStore, 410 store>, SWXC1_FM<9>; 411} 412 413// Load/store doubleword indexed unaligned. 414let Predicates = [NotMips64, HasStdEnc] in { 415 def LUXC1 : LWXC1_FT<"luxc1", AFGR64Opnd, GPR32Opnd, IIFLoad>, 416 LWXC1_FM<0x5>; 417 def SUXC1 : SWXC1_FT<"suxc1", AFGR64Opnd, GPR32Opnd, IIFStore>, 418 SWXC1_FM<0xd>; 419} 420 421let Predicates = [HasMips64, HasStdEnc], 422 DecoderNamespace="Mips64" in { 423 def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, GPR32Opnd, IIFLoad>, 424 LWXC1_FM<0x5>; 425 def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, GPR32Opnd, IIFStore>, 426 SWXC1_FM<0xd>; 427} 428 429/// Floating-point Aritmetic 430def FADD_S : ADDS_FT<"add.s", FGR32Opnd, IIFadd, 1, fadd>, 431 ADDS_FM<0x00, 16>; 432defm FADD : ADDS_M<"add.d", IIFadd, 1, fadd>, ADDS_FM<0x00, 17>; 433def FDIV_S : ADDS_FT<"div.s", FGR32Opnd, IIFdivSingle, 0, fdiv>, 434 ADDS_FM<0x03, 16>; 435defm FDIV : ADDS_M<"div.d", IIFdivDouble, 0, fdiv>, ADDS_FM<0x03, 17>; 436def FMUL_S : ADDS_FT<"mul.s", FGR32Opnd, IIFmulSingle, 1, fmul>, 437 ADDS_FM<0x02, 16>; 438defm FMUL : ADDS_M<"mul.d", IIFmulDouble, 1, fmul>, ADDS_FM<0x02, 17>; 439def FSUB_S : ADDS_FT<"sub.s", FGR32Opnd, IIFadd, 0, fsub>, 440 ADDS_FM<0x01, 16>; 441defm FSUB : ADDS_M<"sub.d", IIFadd, 0, fsub>, ADDS_FM<0x01, 17>; 442 443let Predicates = [HasMips32r2, HasStdEnc] in { 444 def MADD_S : MADDS_FT<"madd.s", FGR32Opnd, IIFmulSingle, fadd>, 445 MADDS_FM<4, 0>; 446 def MSUB_S : MADDS_FT<"msub.s", FGR32Opnd, IIFmulSingle, fsub>, 447 MADDS_FM<5, 0>; 448} 449 450let Predicates = [HasMips32r2, NoNaNsFPMath, HasStdEnc] in { 451 def NMADD_S : NMADDS_FT<"nmadd.s", FGR32Opnd, IIFmulSingle, fadd>, 452 MADDS_FM<6, 0>; 453 def NMSUB_S : NMADDS_FT<"nmsub.s", FGR32Opnd, IIFmulSingle, fsub>, 454 MADDS_FM<7, 0>; 455} 456 457let Predicates = [HasMips32r2, NotFP64bit, HasStdEnc] in { 458 def MADD_D32 : MADDS_FT<"madd.d", AFGR64Opnd, IIFmulDouble, fadd>, 459 MADDS_FM<4, 1>; 460 def MSUB_D32 : MADDS_FT<"msub.d", AFGR64Opnd, IIFmulDouble, fsub>, 461 MADDS_FM<5, 1>; 462} 463 464let Predicates = [HasMips32r2, NotFP64bit, NoNaNsFPMath, HasStdEnc] in { 465 def NMADD_D32 : NMADDS_FT<"nmadd.d", AFGR64Opnd, IIFmulDouble, fadd>, 466 MADDS_FM<6, 1>; 467 def NMSUB_D32 : NMADDS_FT<"nmsub.d", AFGR64Opnd, IIFmulDouble, fsub>, 468 MADDS_FM<7, 1>; 469} 470 471let Predicates = [HasMips32r2, IsFP64bit, HasStdEnc], isCodeGenOnly=1 in { 472 def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, IIFmulDouble, fadd>, 473 MADDS_FM<4, 1>; 474 def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, IIFmulDouble, fsub>, 475 MADDS_FM<5, 1>; 476} 477 478let Predicates = [HasMips32r2, IsFP64bit, NoNaNsFPMath, HasStdEnc], 479 isCodeGenOnly=1 in { 480 def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, IIFmulDouble, fadd>, 481 MADDS_FM<6, 1>; 482 def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd, IIFmulDouble, fsub>, 483 MADDS_FM<7, 1>; 484} 485 486//===----------------------------------------------------------------------===// 487// Floating Point Branch Codes 488//===----------------------------------------------------------------------===// 489// Mips branch codes. These correspond to condcode in MipsInstrInfo.h. 490// They must be kept in synch. 491def MIPS_BRANCH_F : PatLeaf<(i32 0)>; 492def MIPS_BRANCH_T : PatLeaf<(i32 1)>; 493 494def BC1F : BC1F_FT<"bc1f", IIBranch, MIPS_BRANCH_F>, BC1F_FM<0, 0>; 495def BC1T : BC1F_FT<"bc1t", IIBranch, MIPS_BRANCH_T>, BC1F_FM<0, 1>; 496 497//===----------------------------------------------------------------------===// 498// Floating Point Flag Conditions 499//===----------------------------------------------------------------------===// 500// Mips condition codes. They must correspond to condcode in MipsInstrInfo.h. 501// They must be kept in synch. 502def MIPS_FCOND_F : PatLeaf<(i32 0)>; 503def MIPS_FCOND_UN : PatLeaf<(i32 1)>; 504def MIPS_FCOND_OEQ : PatLeaf<(i32 2)>; 505def MIPS_FCOND_UEQ : PatLeaf<(i32 3)>; 506def MIPS_FCOND_OLT : PatLeaf<(i32 4)>; 507def MIPS_FCOND_ULT : PatLeaf<(i32 5)>; 508def MIPS_FCOND_OLE : PatLeaf<(i32 6)>; 509def MIPS_FCOND_ULE : PatLeaf<(i32 7)>; 510def MIPS_FCOND_SF : PatLeaf<(i32 8)>; 511def MIPS_FCOND_NGLE : PatLeaf<(i32 9)>; 512def MIPS_FCOND_SEQ : PatLeaf<(i32 10)>; 513def MIPS_FCOND_NGL : PatLeaf<(i32 11)>; 514def MIPS_FCOND_LT : PatLeaf<(i32 12)>; 515def MIPS_FCOND_NGE : PatLeaf<(i32 13)>; 516def MIPS_FCOND_LE : PatLeaf<(i32 14)>; 517def MIPS_FCOND_NGT : PatLeaf<(i32 15)>; 518 519/// Floating Point Compare 520def FCMP_S32 : CEQS_FT<"s", FGR32, IIFcmp, MipsFPCmp>, CEQS_FM<16>; 521def FCMP_D32 : CEQS_FT<"d", AFGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>, 522 Requires<[NotFP64bit, HasStdEnc]>; 523let DecoderNamespace = "Mips64" in 524def FCMP_D64 : CEQS_FT<"d", FGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>, 525 Requires<[IsFP64bit, HasStdEnc]>; 526 527//===----------------------------------------------------------------------===// 528// Floating Point Pseudo-Instructions 529//===----------------------------------------------------------------------===// 530 531// This pseudo instr gets expanded into 2 mtc1 instrs after register 532// allocation. 533class BuildPairF64Base<RegisterOperand RO> : 534 PseudoSE<(outs RO:$dst), (ins GPR32Opnd:$lo, GPR32Opnd:$hi), 535 [(set RO:$dst, (MipsBuildPairF64 GPR32Opnd:$lo, GPR32Opnd:$hi))]>; 536 537def BuildPairF64 : BuildPairF64Base<AFGR64Opnd>, 538 Requires<[NotFP64bit, HasStdEnc]>; 539def BuildPairF64_64 : BuildPairF64Base<FGR64Opnd>, 540 Requires<[IsFP64bit, HasStdEnc]>; 541 542// This pseudo instr gets expanded into 2 mfc1 instrs after register 543// allocation. 544// if n is 0, lower part of src is extracted. 545// if n is 1, higher part of src is extracted. 546class ExtractElementF64Base<RegisterOperand RO> : 547 PseudoSE<(outs GPR32Opnd:$dst), (ins RO:$src, i32imm:$n), 548 [(set GPR32Opnd:$dst, (MipsExtractElementF64 RO:$src, imm:$n))]>; 549 550def ExtractElementF64 : ExtractElementF64Base<AFGR64Opnd>, 551 Requires<[NotFP64bit, HasStdEnc]>; 552def ExtractElementF64_64 : ExtractElementF64Base<FGR64Opnd>, 553 Requires<[IsFP64bit, HasStdEnc]>; 554 555//===----------------------------------------------------------------------===// 556// InstAliases. 557//===----------------------------------------------------------------------===// 558def : InstAlias<"bc1t $offset", (BC1T FCC0, brtarget:$offset)>; 559def : InstAlias<"bc1f $offset", (BC1F FCC0, brtarget:$offset)>; 560 561//===----------------------------------------------------------------------===// 562// Floating Point Patterns 563//===----------------------------------------------------------------------===// 564def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>; 565def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>; 566 567def : MipsPat<(f32 (sint_to_fp GPR32Opnd:$src)), 568 (PseudoCVT_S_W GPR32Opnd:$src)>; 569def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src), 570 (TRUNC_W_S FGR32Opnd:$src)>; 571 572let Predicates = [NotFP64bit, HasStdEnc] in { 573 def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)), 574 (PseudoCVT_D32_W GPR32Opnd:$src)>; 575 def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src), 576 (TRUNC_W_D32 AFGR64Opnd:$src)>; 577 def : MipsPat<(f32 (fround AFGR64Opnd:$src)), 578 (CVT_S_D32 AFGR64Opnd:$src)>; 579 def : MipsPat<(f64 (fextend FGR32Opnd:$src)), 580 (CVT_D32_S FGR32Opnd:$src)>; 581} 582 583let Predicates = [IsFP64bit, HasStdEnc] in { 584 def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>; 585 def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>; 586 587 def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)), 588 (PseudoCVT_D64_W GPR32Opnd:$src)>; 589 def : MipsPat<(f32 (sint_to_fp GPR64Opnd:$src)), 590 (EXTRACT_SUBREG (PseudoCVT_S_L GPR64Opnd:$src), sub_lo)>; 591 def : MipsPat<(f64 (sint_to_fp GPR64Opnd:$src)), 592 (PseudoCVT_D64_L GPR64Opnd:$src)>; 593 594 def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src), 595 (TRUNC_W_D64 FGR64Opnd:$src)>; 596 def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src), 597 (TRUNC_L_S FGR32Opnd:$src)>; 598 def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src), 599 (TRUNC_L_D64 FGR64Opnd:$src)>; 600 601 def : MipsPat<(f32 (fround FGR64Opnd:$src)), 602 (CVT_S_D64 FGR64Opnd:$src)>; 603 def : MipsPat<(f64 (fextend FGR32Opnd:$src)), 604 (CVT_D64_S FGR32Opnd:$src)>; 605} 606 607// Patterns for loads/stores with a reg+imm operand. 608let AddedComplexity = 40 in { 609 let Predicates = [HasStdEnc] in { 610 def : LoadRegImmPat<LWC1, f32, load>; 611 def : StoreRegImmPat<SWC1, f32>; 612 } 613 614 let Predicates = [IsFP64bit, HasStdEnc] in { 615 def : LoadRegImmPat<LDC164, f64, load>; 616 def : StoreRegImmPat<SDC164, f64>; 617 } 618 619 let Predicates = [NotFP64bit, HasStdEnc] in { 620 def : LoadRegImmPat<PseudoLDC1, f64, load>; 621 def : StoreRegImmPat<PseudoSDC1, f64>; 622 } 623} 624