MipsInstrFPU.td revision b573539c6b47d020ade2e41c0ff3afcd00f294f4 
1//===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the Mips FPU instruction set.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// Floating Point Instructions
16// ------------------------
17// * 64bit fp:
18//    - 32 64-bit registers (default mode)
19//    - 16 even 32-bit registers (32-bit compatible mode) for
20//      single and double access.
21// * 32bit fp:
22//    - 16 even 32-bit registers - single and double (aliased)
23//    - 32 32-bit registers (within single-only mode)
24//===----------------------------------------------------------------------===//
25
26// Floating Point Compare and Branch
27def SDT_MipsFPBrcond : SDTypeProfile<0, 2, [SDTCisInt<0>,
28                                            SDTCisVT<1, OtherVT>]>;
29def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>,
30                                         SDTCisVT<2, i32>]>;
31def SDT_MipsCMovFP : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
32                                          SDTCisSameAs<1, 2>]>;
33def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
34                                                SDTCisVT<1, i32>,
35                                                SDTCisSameAs<1, 2>]>;
36def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
37                                                     SDTCisVT<1, f64>,
38                                                     SDTCisVT<2, i32>]>;
39
40def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>;
41def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>;
42def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>;
43def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond,
44                          [SDNPHasChain, SDNPOptInGlue]>;
45def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>;
46def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64",
47                                   SDT_MipsExtractElementF64>;
48
49// Operand for printing out a condition code.
50let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in
51  def condcode : Operand<i32>;
52
53//===----------------------------------------------------------------------===//
54// Feature predicates.
55//===----------------------------------------------------------------------===//
56
57def IsFP64bit        : Predicate<"Subtarget.isFP64bit()">,
58                       AssemblerPredicate<"FeatureFP64Bit">;
59def NotFP64bit       : Predicate<"!Subtarget.isFP64bit()">,
60                       AssemblerPredicate<"!FeatureFP64Bit">;
61def IsSingleFloat    : Predicate<"Subtarget.isSingleFloat()">,
62                       AssemblerPredicate<"FeatureSingleFloat">;
63def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">,
64                       AssemblerPredicate<"!FeatureSingleFloat">;
65
66// FP immediate patterns.
67def fpimm0 : PatLeaf<(fpimm), [{
68  return N->isExactlyValue(+0.0);
69}]>;
70
71def fpimm0neg : PatLeaf<(fpimm), [{
72  return N->isExactlyValue(-0.0);
73}]>;
74
75//===----------------------------------------------------------------------===//
76// Instruction Class Templates
77//
78// A set of multiclasses is used to address the register usage.
79//
80// S32 - single precision in 16 32bit even fp registers
81//       single precision in 32 32bit fp registers in SingleOnly mode
82// S64 - single precision in 32 64bit fp registers (In64BitMode)
83// D32 - double precision in 16 32bit even fp registers
84// D64 - double precision in 32 64bit fp registers (In64BitMode)
85//
86// Only S32 and D32 are supported right now.
87//===----------------------------------------------------------------------===//
88
89// FP unary instructions without patterns.
90class FFR1<bits<6> funct, bits<5> fmt, string opstr, RegisterClass DstRC,
91           RegisterClass SrcRC> :
92  FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs),
93      !strconcat(opstr, "\t$fd, $fs"), []> {
94  let ft = 0;
95}
96
97// FP unary instructions with patterns.
98class FFR1P<bits<6> funct, bits<5> fmt, string opstr, RegisterClass DstRC,
99            RegisterClass SrcRC, SDNode OpNode> :
100  FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs),
101      !strconcat(opstr, "\t$fd, $fs"),
102      [(set DstRC:$fd, (OpNode SrcRC:$fs))]> {
103  let ft = 0;
104}
105
106class FFR2P<bits<6> funct, bits<5> fmt, string opstr, RegisterClass RC,
107            SDNode OpNode> :
108  FFR<0x11, funct, fmt, (outs RC:$fd), (ins RC:$fs, RC:$ft),
109      !strconcat(opstr, "\t$fd, $fs, $ft"),
110      [(set RC:$fd, (OpNode RC:$fs, RC:$ft))]>;
111
112// FP load.
113let DecoderMethod = "DecodeFMem" in {
114class FPLoad<bits<6> op, string opstr, RegisterClass RC, Operand MemOpnd>:
115  FMem<op, (outs RC:$ft), (ins MemOpnd:$addr),
116      !strconcat(opstr, "\t$ft, $addr"), [(set RC:$ft, (load addr:$addr))],
117      IILoad>;
118
119// FP store.
120class FPStore<bits<6> op, string opstr, RegisterClass RC, Operand MemOpnd>:
121  FMem<op, (outs), (ins RC:$ft, MemOpnd:$addr),
122      !strconcat(opstr, "\t$ft, $addr"), [(store RC:$ft, addr:$addr)],
123      IIStore>;
124}
125// FP indexed load.
126class FPIdxLoad<bits<6> funct, string opstr, RegisterClass DRC,
127                RegisterClass PRC, SDPatternOperator FOp = null_frag>:
128  FFMemIdx<funct, (outs DRC:$fd), (ins PRC:$base, PRC:$index),
129           !strconcat(opstr, "\t$fd, ${index}(${base})"),
130           [(set DRC:$fd, (FOp (add PRC:$base, PRC:$index)))]> {
131  let fs = 0;
132}
133
134// FP indexed store.
135class FPIdxStore<bits<6> funct, string opstr, RegisterClass DRC,
136                 RegisterClass PRC, SDPatternOperator FOp= null_frag>:
137  FFMemIdx<funct, (outs), (ins DRC:$fs, PRC:$base, PRC:$index),
138           !strconcat(opstr, "\t$fs, ${index}(${base})"),
139           [(FOp DRC:$fs, (add PRC:$base, PRC:$index))]> {
140  let fd = 0;
141}
142
143// Instructions that convert an FP value to 32-bit fixed point.
144multiclass FFR1_W_M<bits<6> funct, string opstr> {
145  def _D32 : FFR1<funct, 17, opstr, FGR32, AFGR64>,
146             Requires<[NotFP64bit, HasStdEnc]>;
147  def _D64 : FFR1<funct, 17, opstr, FGR32, FGR64>,
148             Requires<[IsFP64bit, HasStdEnc]> {
149    let DecoderNamespace = "Mips64";
150  }
151}
152
153// FP-to-FP conversion instructions.
154multiclass FFR1P_M<bits<6> funct, string opstr, SDNode OpNode> {
155  def _D32 : FFR1P<funct, 17, opstr, AFGR64, AFGR64, OpNode>,
156             Requires<[NotFP64bit, HasStdEnc]>;
157  def _D64 : FFR1P<funct, 17, opstr, FGR64, FGR64, OpNode>,
158             Requires<[IsFP64bit, HasStdEnc]> {
159    let DecoderNamespace = "Mips64";
160  }
161}
162
163multiclass FFR2P_M<bits<6> funct, string opstr, SDNode OpNode> {
164  def _D32 : FFR2P<funct, 17, opstr, AFGR64, OpNode>,
165             Requires<[NotFP64bit, HasStdEnc]>;
166  def _D64 : FFR2P<funct, 17, opstr, FGR64, OpNode>,
167             Requires<[IsFP64bit, HasStdEnc]> {
168    let DecoderNamespace = "Mips64";
169  }
170}
171
172// FP madd/msub/nmadd/nmsub instruction classes.
173class FMADDSUB<bits<3> funct, bits<3> fmt, string opstr,
174               SDNode OpNode, RegisterClass RC> :
175  FFMADDSUB<funct, fmt, (outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
176            !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
177            [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))]>;
178
179class FNMADDSUB<bits<3> funct, bits<3> fmt, string opstr,
180                SDNode OpNode, RegisterClass RC> :
181  FFMADDSUB<funct, fmt, (outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
182            !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
183            [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))]>;
184
185class ADDS_FT<string opstr, RegisterClass RC, InstrItinClass Itin, bit IsComm,
186              SDPatternOperator OpNode= null_frag> :
187  InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft),
188         !strconcat(opstr, "\t$fd, $fs, $ft"),
189         [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR> {
190  let isCommutable = IsComm;
191}
192
193multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm,
194                  SDPatternOperator OpNode = null_frag> {
195  def _D32 : ADDS_FT<opstr, AFGR64, Itin, IsComm, OpNode>,
196             Requires<[NotFP64bit, HasStdEnc]>;
197  def _D64 : ADDS_FT<opstr, FGR64, Itin, IsComm, OpNode>,
198             Requires<[IsFP64bit, HasStdEnc]> {
199    string DecoderNamespace = "Mips64";
200  }
201}
202
203class ABSS_FT<string opstr, RegisterClass DstRC, RegisterClass SrcRC,
204              InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
205  InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
206         [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR>;
207
208multiclass ABSS_M<string opstr, InstrItinClass Itin,
209                  SDPatternOperator OpNode= null_frag> {
210  def _D32 : ABSS_FT<opstr, AFGR64, AFGR64, Itin, OpNode>,
211             Requires<[NotFP64bit, HasStdEnc]>;
212  def _D64 : ABSS_FT<opstr, FGR64, FGR64, Itin, OpNode>,
213             Requires<[IsFP64bit, HasStdEnc]> {
214    string DecoderNamespace = "Mips64";
215  }
216}
217
218multiclass ROUND_M<string opstr, InstrItinClass Itin> {
219  def _D32 : ABSS_FT<opstr, FGR32, AFGR64, Itin>,
220             Requires<[NotFP64bit, HasStdEnc]>;
221  def _D64 : ABSS_FT<opstr, FGR32, FGR64, Itin>,
222             Requires<[IsFP64bit, HasStdEnc]> {
223    let DecoderNamespace = "Mips64";
224  }
225}
226
227class MFC1_FT<string opstr, RegisterClass DstRC, RegisterClass SrcRC,
228              InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
229  InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
230         [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR>;
231
232class MTC1_FT<string opstr, RegisterClass DstRC, RegisterClass SrcRC,
233              InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
234  InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
235         [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR>;
236
237class LW_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
238            Operand MemOpnd, SDPatternOperator OpNode= null_frag> :
239  InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
240         [(set RC:$rt, (OpNode addr:$addr))], Itin, FrmFI> {
241  let DecoderMethod = "DecodeFMem";
242}
243
244class SW_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
245            Operand MemOpnd, SDPatternOperator OpNode= null_frag> :
246  InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
247         [(OpNode RC:$rt, addr:$addr)], Itin, FrmFI> {
248  let DecoderMethod = "DecodeFMem";
249}
250
251class MADDS_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
252               SDPatternOperator OpNode = null_frag> :
253  InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
254         !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
255         [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))], Itin, FrmFR>;
256
257class NMADDS_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
258                SDPatternOperator OpNode = null_frag> :
259  InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
260         !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
261         [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))],
262         Itin, FrmFR>;
263
264class LWXC1_FT<string opstr, RegisterClass DRC, RegisterClass PRC,
265               InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
266  InstSE<(outs DRC:$fd), (ins PRC:$base, PRC:$index),
267         !strconcat(opstr, "\t$fd, ${index}(${base})"),
268         [(set DRC:$fd, (OpNode (add PRC:$base, PRC:$index)))], Itin, FrmFI>;
269
270class SWXC1_FT<string opstr, RegisterClass DRC, RegisterClass PRC,
271               InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
272  InstSE<(outs), (ins DRC:$fs, PRC:$base, PRC:$index),
273         !strconcat(opstr, "\t$fs, ${index}(${base})"),
274         [(OpNode DRC:$fs, (add PRC:$base, PRC:$index))], Itin, FrmFI>;
275
276class BC1F_FT<string opstr, InstrItinClass Itin,
277              SDPatternOperator Op = null_frag>  :
278  InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"),
279         [(MipsFPBrcond Op, bb:$offset)], Itin, FrmFI> {
280  let isBranch = 1;
281  let isTerminator = 1;
282  let hasDelaySlot = 1;
283  let Defs = [AT];
284  let Uses = [FCR31];
285}
286
287class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin,
288              SDPatternOperator OpNode = null_frag>  :
289  InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond),
290         !strconcat("c.$cond.", typestr, "\t$fs, $ft"),
291         [(OpNode RC:$fs, RC:$ft, imm:$cond)], Itin, FrmFR> {
292  let Defs = [FCR31];
293}
294
295//===----------------------------------------------------------------------===//
296// Floating Point Instructions
297//===----------------------------------------------------------------------===//
298def ROUND_W_S  : ABSS_FT<"round.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xc, 16>;
299def TRUNC_W_S  : ABSS_FT<"trunc.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xd, 16>;
300def CEIL_W_S   : ABSS_FT<"ceil.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xe, 16>;
301def FLOOR_W_S  : ABSS_FT<"floor.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xf, 16>;
302def CVT_W_S    : ABSS_FT<"cvt.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0x24, 16>,
303                 NeverHasSideEffects;
304
305defm ROUND_W : ROUND_M<"round.w.d", IIFcvt>, ABSS_FM<0xc, 17>;
306defm TRUNC_W : ROUND_M<"trunc.w.d", IIFcvt>, ABSS_FM<0xd, 17>;
307defm CEIL_W  : ROUND_M<"ceil.w.d", IIFcvt>, ABSS_FM<0xe, 17>;
308defm FLOOR_W : ROUND_M<"floor.w.d", IIFcvt>, ABSS_FM<0xf, 17>;
309defm CVT_W   : ROUND_M<"cvt.w.d", IIFcvt>, ABSS_FM<0x24, 17>,
310               NeverHasSideEffects;
311
312let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
313  def ROUND_L_S : ABSS_FT<"round.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x8, 16>;
314  def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64, FGR64, IIFcvt>,
315                    ABSS_FM<0x8, 17>;
316  def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x9, 16>;
317  def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64, FGR64, IIFcvt>,
318                    ABSS_FM<0x9, 17>;
319  def CEIL_L_S  : ABSS_FT<"ceil.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0xa, 16>;
320  def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64, FGR64, IIFcvt>, ABSS_FM<0xa, 17>;
321  def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0xb, 16>;
322  def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64, FGR64, IIFcvt>,
323                    ABSS_FM<0xb, 17>;
324}
325
326def CVT_S_W : ABSS_FT<"cvt.s.w", FGR32, FGR32, IIFcvt>, ABSS_FM<0x20, 20>;
327def CVT_L_S : ABSS_FT<"cvt.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x25, 16>,
328              NeverHasSideEffects;
329def CVT_L_D64: ABSS_FT<"cvt.l.d", FGR64, FGR64, IIFcvt>, ABSS_FM<0x25, 17>,
330               NeverHasSideEffects;
331
332let Predicates = [NotFP64bit, HasStdEnc], neverHasSideEffects = 1 in {
333  def CVT_S_D32 : ABSS_FT<"cvt.s.d", FGR32, AFGR64, IIFcvt>, ABSS_FM<0x20, 17>;
334  def CVT_D32_W : ABSS_FT<"cvt.d.w", AFGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 20>;
335  def CVT_D32_S : ABSS_FT<"cvt.d.s", AFGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 16>;
336}
337
338let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64",
339    neverHasSideEffects = 1 in {
340 def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32, FGR64, IIFcvt>, ABSS_FM<0x20, 17>;
341 def CVT_S_L   : ABSS_FT<"cvt.s.l", FGR32, FGR64, IIFcvt>, ABSS_FM<0x20, 21>;
342 def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 20>;
343 def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 16>;
344 def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64, FGR64, IIFcvt>, ABSS_FM<0x21, 21>;
345}
346
347let Predicates = [NoNaNsFPMath, HasStdEnc] in {
348  def FABS_S : ABSS_FT<"abs.s", FGR32, FGR32, IIFcvt, fabs>, ABSS_FM<0x5, 16>;
349  def FNEG_S : ABSS_FT<"neg.s", FGR32, FGR32, IIFcvt, fneg>, ABSS_FM<0x7, 16>;
350  defm FABS : ABSS_M<"abs.d", IIFcvt, fabs>, ABSS_FM<0x5, 17>;
351  defm FNEG : ABSS_M<"neg.d", IIFcvt, fneg>, ABSS_FM<0x7, 17>;
352}
353
354def  FSQRT_S : ABSS_FT<"sqrt.s", FGR32, FGR32, IIFsqrtSingle, fsqrt>,
355               ABSS_FM<0x4, 16>;
356defm FSQRT : ABSS_M<"sqrt.d", IIFsqrtDouble, fsqrt>, ABSS_FM<0x4, 17>;
357
358// The odd-numbered registers are only referenced when doing loads,
359// stores, and moves between floating-point and integer registers.
360// When defining instructions, we reference all 32-bit registers,
361// regardless of register aliasing.
362
363class FFRGPR<bits<5> _fmt, dag outs, dag ins, string asmstr, list<dag> pattern>:
364             FFR<0x11, 0x0, _fmt, outs, ins, asmstr, pattern> {
365  bits<5> rt;
366  let ft = rt;
367  let fd = 0;
368}
369
370/// Move Control Registers From/To CPU Registers
371def CFC1 : MFC1_FT<"cfc1", CPURegs, CCR, IIFmove>, MFC1_FM<2>;
372def CTC1 : MTC1_FT<"ctc1", CCR, CPURegs, IIFmove>, MFC1_FM<6>;
373def MFC1 : MFC1_FT<"mfc1", CPURegs, FGR32, IIFmove, bitconvert>, MFC1_FM<0>;
374def MTC1 : MTC1_FT<"mtc1", FGR32, CPURegs, IIFmove, bitconvert>, MFC1_FM<4>;
375def DMFC1 : MFC1_FT<"dmfc1", CPU64Regs, FGR64, IIFmove, bitconvert>, MFC1_FM<1>;
376def DMTC1 : MTC1_FT<"dmtc1", FGR64, CPU64Regs, IIFmove, bitconvert>, MFC1_FM<5>;
377
378def FMOV_S   : ABSS_FT<"mov.s", FGR32, FGR32, IIFmove>, ABSS_FM<0x6, 16>;
379def FMOV_D32 : ABSS_FT<"mov.d", AFGR64, AFGR64, IIFmove>, ABSS_FM<0x6, 17>,
380               Requires<[NotFP64bit, HasStdEnc]>;
381def FMOV_D64 : ABSS_FT<"mov.d", FGR64, FGR64, IIFmove>, ABSS_FM<0x6, 17>,
382               Requires<[IsFP64bit, HasStdEnc]> {
383  let DecoderNamespace = "Mips64";
384}
385
386/// Floating Point Memory Instructions
387let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in {
388  def LWC1_P8 : LW_FT<"lwc1", FGR32, IILoad, mem64, load>, LW_FM<0x31>;
389  def SWC1_P8 : SW_FT<"swc1", FGR32, IIStore, mem64, store>, LW_FM<0x39>;
390  def LDC164_P8 : LW_FT<"ldc1", FGR64, IILoad, mem64, load>, LW_FM<0x35> {
391    let isCodeGenOnly =1;
392  }
393  def SDC164_P8 : SW_FT<"sdc1", FGR64, IIStore, mem64, store>, LW_FM<0x3d> {
394    let isCodeGenOnly =1;
395  }
396}
397
398let Predicates = [NotN64, HasStdEnc] in {
399  def LWC1 : LW_FT<"lwc1", FGR32, IILoad, mem, load>, LW_FM<0x31>;
400  def SWC1 : SW_FT<"swc1", FGR32, IIStore, mem, store>, LW_FM<0x39>;
401}
402
403let Predicates = [NotN64, HasMips64, HasStdEnc],
404  DecoderNamespace = "Mips64" in {
405  def LDC164 : LW_FT<"ldc1", FGR64, IILoad, mem, load>, LW_FM<0x35>;
406  def SDC164 : SW_FT<"sdc1", FGR64, IIStore, mem, store>, LW_FM<0x3d>;
407}
408
409let Predicates = [NotN64, NotMips64, HasStdEnc] in {
410  def LDC1 : LW_FT<"ldc1", AFGR64, IILoad, mem, load>, LW_FM<0x35>;
411  def SDC1 : SW_FT<"sdc1", AFGR64, IIStore, mem, store>, LW_FM<0x3d>;
412}
413
414// Indexed loads and stores.
415let Predicates = [HasFPIdx, HasStdEnc] in {
416  def LWXC1 : LWXC1_FT<"lwxc1", FGR32, CPURegs, IILoad, load>, LWXC1_FM<0>;
417  def SWXC1 : SWXC1_FT<"swxc1", FGR32, CPURegs, IIStore, store>, SWXC1_FM<8>;
418}
419
420let Predicates = [HasMips32r2, NotMips64, HasStdEnc] in {
421  def LDXC1 : LWXC1_FT<"ldxc1", AFGR64, CPURegs, IILoad, load>, LWXC1_FM<1>;
422  def SDXC1 : SWXC1_FT<"sdxc1", AFGR64, CPURegs, IIStore, store>, SWXC1_FM<9>;
423}
424
425let Predicates = [HasMips64, NotN64, HasStdEnc], DecoderNamespace="Mips64" in {
426  def LDXC164 : LWXC1_FT<"ldxc1", FGR64, CPURegs, IILoad, load>, LWXC1_FM<1>;
427  def SDXC164 : SWXC1_FT<"sdxc1", FGR64, CPURegs, IIStore, store>, SWXC1_FM<9>;
428}
429
430// n64
431let Predicates = [IsN64, HasStdEnc], isCodeGenOnly=1 in {
432  def LWXC1_P8 : LWXC1_FT<"lwxc1", FGR32, CPU64Regs, IILoad, load>, LWXC1_FM<0>;
433  def LDXC164_P8 : LWXC1_FT<"ldxc1", FGR64, CPU64Regs, IILoad, load>,
434                   LWXC1_FM<1>;
435  def SWXC1_P8 : SWXC1_FT<"swxc1", FGR32, CPU64Regs, IIStore, store>,
436                 SWXC1_FM<8>;
437  def SDXC164_P8 : SWXC1_FT<"sdxc1", FGR64, CPU64Regs, IIStore, store>,
438                   SWXC1_FM<9>;
439}
440
441// Load/store doubleword indexed unaligned.
442let Predicates = [NotMips64, HasStdEnc] in {
443  def LUXC1 : LWXC1_FT<"luxc1", AFGR64, CPURegs, IILoad>, LWXC1_FM<0x5>;
444  def SUXC1 : SWXC1_FT<"suxc1", AFGR64, CPURegs, IIStore>, SWXC1_FM<0xd>;
445}
446
447let Predicates = [HasMips64, HasStdEnc],
448  DecoderNamespace="Mips64" in {
449  def LUXC164 : LWXC1_FT<"luxc1", FGR64, CPURegs, IILoad>, LWXC1_FM<0x5>;
450  def SUXC164 : SWXC1_FT<"suxc1", FGR64, CPURegs, IIStore>, SWXC1_FM<0xd>;
451}
452
453/// Floating-point Aritmetic
454def FADD_S : ADDS_FT<"add.s", FGR32, IIFadd, 1, fadd>, ADDS_FM<0x00, 16>;
455defm FADD : ADDS_M<"add.d", IIFadd, 1, fadd>, ADDS_FM<0x00, 17>;
456def FDIV_S : ADDS_FT<"div.s", FGR32, IIFdivSingle, 0, fdiv>, ADDS_FM<0x03, 16>;
457defm FDIV : ADDS_M<"div.d", IIFdivDouble, 0, fdiv>, ADDS_FM<0x03, 17>;
458def FMUL_S : ADDS_FT<"mul.s", FGR32, IIFmulSingle, 1, fmul>, ADDS_FM<0x02, 16>;
459defm FMUL : ADDS_M<"mul.d", IIFmulDouble, 1, fmul>, ADDS_FM<0x02, 17>;
460def FSUB_S : ADDS_FT<"sub.s", FGR32, IIFadd, 0, fsub>, ADDS_FM<0x01, 16>;
461defm FSUB : ADDS_M<"sub.d", IIFadd, 0, fsub>, ADDS_FM<0x01, 17>;
462
463let Predicates = [HasMips32r2, HasStdEnc] in {
464  def MADD_S : MADDS_FT<"madd.s", FGR32, IIFmulSingle, fadd>, MADDS_FM<4, 0>;
465  def MSUB_S : MADDS_FT<"msub.s", FGR32, IIFmulSingle, fsub>, MADDS_FM<5, 0>;
466}
467
468let Predicates = [HasMips32r2, NoNaNsFPMath, HasStdEnc] in {
469  def NMADD_S : NMADDS_FT<"nmadd.s", FGR32, IIFmulSingle, fadd>, MADDS_FM<6, 0>;
470  def NMSUB_S : NMADDS_FT<"nmsub.s", FGR32, IIFmulSingle, fsub>, MADDS_FM<7, 0>;
471}
472
473let Predicates = [HasMips32r2, NotFP64bit, HasStdEnc] in {
474  def MADD_D32 : MADDS_FT<"madd.d", AFGR64, IIFmulDouble, fadd>, MADDS_FM<4, 1>;
475  def MSUB_D32 : MADDS_FT<"msub.d", AFGR64, IIFmulDouble, fsub>, MADDS_FM<5, 1>;
476}
477
478let Predicates = [HasMips32r2, NotFP64bit, NoNaNsFPMath, HasStdEnc] in {
479  def NMADD_D32 : NMADDS_FT<"nmadd.d", AFGR64, IIFmulDouble, fadd>,
480                  MADDS_FM<6, 1>;
481  def NMSUB_D32 : NMADDS_FT<"nmsub.d", AFGR64, IIFmulDouble, fsub>,
482                  MADDS_FM<7, 1>;
483}
484
485let Predicates = [HasMips32r2, IsFP64bit, HasStdEnc], isCodeGenOnly=1 in {
486  def MADD_D64 : MADDS_FT<"madd.d", FGR64, IIFmulDouble, fadd>, MADDS_FM<4, 1>;
487  def MSUB_D64 : MADDS_FT<"msub.d", FGR64, IIFmulDouble, fsub>, MADDS_FM<5, 1>;
488}
489
490let Predicates = [HasMips32r2, IsFP64bit, NoNaNsFPMath, HasStdEnc],
491    isCodeGenOnly=1 in {
492  def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64, IIFmulDouble, fadd>,
493                  MADDS_FM<6, 1>;
494  def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64, IIFmulDouble, fsub>,
495                  MADDS_FM<7, 1>;
496}
497
498//===----------------------------------------------------------------------===//
499// Floating Point Branch Codes
500//===----------------------------------------------------------------------===//
501// Mips branch codes. These correspond to condcode in MipsInstrInfo.h.
502// They must be kept in synch.
503def MIPS_BRANCH_F  : PatLeaf<(i32 0)>;
504def MIPS_BRANCH_T  : PatLeaf<(i32 1)>;
505
506/// Floating Point Branch of False/True (Likely)
507let isBranch=1, isTerminator=1, hasDelaySlot=1, base=0x8, Uses=[FCR31] in
508  class FBRANCH<bits<1> nd, bits<1> tf, PatLeaf op, string asmstr> :
509      FFI<0x11, (outs), (ins brtarget:$dst), !strconcat(asmstr, "\t$dst"),
510        [(MipsFPBrcond op, bb:$dst)]> {
511  let Inst{20-18} = 0;
512  let Inst{17} = nd;
513  let Inst{16} = tf;
514}
515
516let DecoderMethod = "DecodeBC1" in {
517def BC1F : BC1F_FT<"bc1f", IIBranch, MIPS_BRANCH_F>, BC1F_FM<0, 0>;
518def BC1T : BC1F_FT<"bc1t", IIBranch, MIPS_BRANCH_T>, BC1F_FM<0, 1>;
519}
520//===----------------------------------------------------------------------===//
521// Floating Point Flag Conditions
522//===----------------------------------------------------------------------===//
523// Mips condition codes. They must correspond to condcode in MipsInstrInfo.h.
524// They must be kept in synch.
525def MIPS_FCOND_F    : PatLeaf<(i32 0)>;
526def MIPS_FCOND_UN   : PatLeaf<(i32 1)>;
527def MIPS_FCOND_OEQ  : PatLeaf<(i32 2)>;
528def MIPS_FCOND_UEQ  : PatLeaf<(i32 3)>;
529def MIPS_FCOND_OLT  : PatLeaf<(i32 4)>;
530def MIPS_FCOND_ULT  : PatLeaf<(i32 5)>;
531def MIPS_FCOND_OLE  : PatLeaf<(i32 6)>;
532def MIPS_FCOND_ULE  : PatLeaf<(i32 7)>;
533def MIPS_FCOND_SF   : PatLeaf<(i32 8)>;
534def MIPS_FCOND_NGLE : PatLeaf<(i32 9)>;
535def MIPS_FCOND_SEQ  : PatLeaf<(i32 10)>;
536def MIPS_FCOND_NGL  : PatLeaf<(i32 11)>;
537def MIPS_FCOND_LT   : PatLeaf<(i32 12)>;
538def MIPS_FCOND_NGE  : PatLeaf<(i32 13)>;
539def MIPS_FCOND_LE   : PatLeaf<(i32 14)>;
540def MIPS_FCOND_NGT  : PatLeaf<(i32 15)>;
541
542class FCMP<bits<5> fmt, RegisterClass RC, string typestr> :
543  FCC<fmt, (outs), (ins RC:$fs, RC:$ft, condcode:$cc),
544      !strconcat("c.$cc.", typestr, "\t$fs, $ft"),
545      [(MipsFPCmp RC:$fs, RC:$ft, imm:$cc)]>;
546
547/// Floating Point Compare
548def FCMP_S32 : CEQS_FT<"s", FGR32, IIFcmp, MipsFPCmp>, CEQS_FM<16>;
549def FCMP_D32 : CEQS_FT<"d", AFGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>,
550               Requires<[NotFP64bit, HasStdEnc]>;
551let DecoderNamespace = "Mips64" in
552def FCMP_D64 : CEQS_FT<"d", FGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>,
553               Requires<[IsFP64bit, HasStdEnc]>;
554
555//===----------------------------------------------------------------------===//
556// Floating Point Pseudo-Instructions
557//===----------------------------------------------------------------------===//
558def MOVCCRToCCR : PseudoSE<(outs CCR:$dst), (ins CCR:$src),
559                           "# MOVCCRToCCR", []>;
560
561// This pseudo instr gets expanded into 2 mtc1 instrs after register
562// allocation.
563def BuildPairF64 :
564  PseudoSE<(outs AFGR64:$dst),
565           (ins CPURegs:$lo, CPURegs:$hi), "",
566           [(set AFGR64:$dst, (MipsBuildPairF64 CPURegs:$lo, CPURegs:$hi))]>;
567
568// This pseudo instr gets expanded into 2 mfc1 instrs after register
569// allocation.
570// if n is 0, lower part of src is extracted.
571// if n is 1, higher part of src is extracted.
572def ExtractElementF64 :
573  PseudoSE<(outs CPURegs:$dst), (ins AFGR64:$src, i32imm:$n), "",
574           [(set CPURegs:$dst, (MipsExtractElementF64 AFGR64:$src, imm:$n))]>;
575
576//===----------------------------------------------------------------------===//
577// Floating Point Patterns
578//===----------------------------------------------------------------------===//
579def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>;
580def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
581
582def : MipsPat<(f32 (sint_to_fp CPURegs:$src)), (CVT_S_W (MTC1 CPURegs:$src))>;
583def : MipsPat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S FGR32:$src))>;
584
585let Predicates = [NotFP64bit, HasStdEnc] in {
586  def : MipsPat<(f64 (sint_to_fp CPURegs:$src)),
587                (CVT_D32_W (MTC1 CPURegs:$src))>;
588  def : MipsPat<(i32 (fp_to_sint AFGR64:$src)),
589                (MFC1 (TRUNC_W_D32 AFGR64:$src))>;
590  def : MipsPat<(f32 (fround AFGR64:$src)), (CVT_S_D32 AFGR64:$src)>;
591  def : MipsPat<(f64 (fextend FGR32:$src)), (CVT_D32_S FGR32:$src)>;
592}
593
594let Predicates = [IsFP64bit, HasStdEnc] in {
595  def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>;
596  def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>;
597
598  def : MipsPat<(f64 (sint_to_fp CPURegs:$src)),
599                (CVT_D64_W (MTC1 CPURegs:$src))>;
600  def : MipsPat<(f32 (sint_to_fp CPU64Regs:$src)),
601                (CVT_S_L (DMTC1 CPU64Regs:$src))>;
602  def : MipsPat<(f64 (sint_to_fp CPU64Regs:$src)),
603                (CVT_D64_L (DMTC1 CPU64Regs:$src))>;
604
605  def : MipsPat<(i32 (fp_to_sint FGR64:$src)),
606                (MFC1 (TRUNC_W_D64 FGR64:$src))>;
607  def : MipsPat<(i64 (fp_to_sint FGR32:$src)), (DMFC1 (TRUNC_L_S FGR32:$src))>;
608  def : MipsPat<(i64 (fp_to_sint FGR64:$src)),
609                (DMFC1 (TRUNC_L_D64 FGR64:$src))>;
610
611  def : MipsPat<(f32 (fround FGR64:$src)), (CVT_S_D64 FGR64:$src)>;
612  def : MipsPat<(f64 (fextend FGR32:$src)), (CVT_D64_S FGR32:$src)>;
613}
614