MipsInstrFPU.td revision ec4db6ab5f64318b1aa2351f7e710569869193e9 
1//===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the Mips FPU instruction set.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// Floating Point Instructions
16// ------------------------
17// * 64bit fp:
18//    - 32 64-bit registers (default mode)
19//    - 16 even 32-bit registers (32-bit compatible mode) for
20//      single and double access.
21// * 32bit fp:
22//    - 16 even 32-bit registers - single and double (aliased)
23//    - 32 32-bit registers (within single-only mode)
24//===----------------------------------------------------------------------===//
25
26// Floating Point Compare and Branch
27def SDT_MipsFPBrcond : SDTypeProfile<0, 2, [SDTCisInt<0>,
28                                            SDTCisVT<1, OtherVT>]>;
29def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>,
30                                         SDTCisVT<2, i32>]>;
31def SDT_MipsCMovFP : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
32                                          SDTCisSameAs<1, 2>]>;
33def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
34                                                SDTCisVT<1, i32>,
35                                                SDTCisSameAs<1, 2>]>;
36def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
37                                                     SDTCisVT<1, f64>,
38                                                     SDTCisVT<2, i32>]>;
39
40def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>;
41def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>;
42def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>;
43def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond,
44                          [SDNPHasChain, SDNPOptInGlue]>;
45def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>;
46def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64",
47                                   SDT_MipsExtractElementF64>;
48
49// Operand for printing out a condition code.
50let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in
51  def condcode : Operand<i32>;
52
53//===----------------------------------------------------------------------===//
54// Feature predicates.
55//===----------------------------------------------------------------------===//
56
57def IsFP64bit        : Predicate<"Subtarget.isFP64bit()">,
58                       AssemblerPredicate<"FeatureFP64Bit">;
59def NotFP64bit       : Predicate<"!Subtarget.isFP64bit()">,
60                       AssemblerPredicate<"!FeatureFP64Bit">;
61def IsSingleFloat    : Predicate<"Subtarget.isSingleFloat()">,
62                       AssemblerPredicate<"FeatureSingleFloat">;
63def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">,
64                       AssemblerPredicate<"!FeatureSingleFloat">;
65
66// FP immediate patterns.
67def fpimm0 : PatLeaf<(fpimm), [{
68  return N->isExactlyValue(+0.0);
69}]>;
70
71def fpimm0neg : PatLeaf<(fpimm), [{
72  return N->isExactlyValue(-0.0);
73}]>;
74
75//===----------------------------------------------------------------------===//
76// Instruction Class Templates
77//
78// A set of multiclasses is used to address the register usage.
79//
80// S32 - single precision in 16 32bit even fp registers
81//       single precision in 32 32bit fp registers in SingleOnly mode
82// S64 - single precision in 32 64bit fp registers (In64BitMode)
83// D32 - double precision in 16 32bit even fp registers
84// D64 - double precision in 32 64bit fp registers (In64BitMode)
85//
86// Only S32 and D32 are supported right now.
87//===----------------------------------------------------------------------===//
88
89class ADDS_FT<string opstr, RegisterClass RC, InstrItinClass Itin, bit IsComm,
90              SDPatternOperator OpNode= null_frag> :
91  InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft),
92         !strconcat(opstr, "\t$fd, $fs, $ft"),
93         [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR> {
94  let isCommutable = IsComm;
95}
96
97multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm,
98                  SDPatternOperator OpNode = null_frag> {
99  def _D32 : ADDS_FT<opstr, AFGR64, Itin, IsComm, OpNode>,
100             Requires<[NotFP64bit, HasStdEnc]>;
101  def _D64 : ADDS_FT<opstr, FGR64, Itin, IsComm, OpNode>,
102             Requires<[IsFP64bit, HasStdEnc]> {
103    string DecoderNamespace = "Mips64";
104  }
105}
106
107class ABSS_FT<string opstr, RegisterClass DstRC, RegisterClass SrcRC,
108              InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
109  InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
110         [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR>,
111  NeverHasSideEffects;
112
113multiclass ABSS_M<string opstr, InstrItinClass Itin,
114                  SDPatternOperator OpNode= null_frag> {
115  def _D32 : ABSS_FT<opstr, AFGR64, AFGR64, Itin, OpNode>,
116             Requires<[NotFP64bit, HasStdEnc]>;
117  def _D64 : ABSS_FT<opstr, FGR64, FGR64, Itin, OpNode>,
118             Requires<[IsFP64bit, HasStdEnc]> {
119    string DecoderNamespace = "Mips64";
120  }
121}
122
123multiclass ROUND_M<string opstr, InstrItinClass Itin> {
124  def _D32 : ABSS_FT<opstr, FGR32, AFGR64, Itin>,
125             Requires<[NotFP64bit, HasStdEnc]>;
126  def _D64 : ABSS_FT<opstr, FGR32, FGR64, Itin>,
127             Requires<[IsFP64bit, HasStdEnc]> {
128    let DecoderNamespace = "Mips64";
129  }
130}
131
132class MFC1_FT<string opstr, RegisterClass DstRC, RegisterClass SrcRC,
133              InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
134  InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
135         [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR>;
136
137class MTC1_FT<string opstr, RegisterClass DstRC, RegisterClass SrcRC,
138              InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
139  InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
140         [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR>;
141
142class MFC1_FT_CCR<string opstr, RegisterClass DstRC, RegisterOperand SrcRC,
143              InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
144  InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
145         [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR>;
146
147class MTC1_FT_CCR<string opstr, RegisterOperand DstRC, RegisterClass SrcRC,
148              InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
149  InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
150         [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR>;
151
152class LW_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
153            Operand MemOpnd, SDPatternOperator OpNode= null_frag> :
154  InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
155         [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI> {
156  let DecoderMethod = "DecodeFMem";
157  let mayLoad = 1;
158}
159
160class SW_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
161            Operand MemOpnd, SDPatternOperator OpNode= null_frag> :
162  InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
163         [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI> {
164  let DecoderMethod = "DecodeFMem";
165  let mayStore = 1;
166}
167
168class MADDS_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
169               SDPatternOperator OpNode = null_frag> :
170  InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
171         !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
172         [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))], Itin, FrmFR>;
173
174class NMADDS_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
175                SDPatternOperator OpNode = null_frag> :
176  InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
177         !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
178         [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))],
179         Itin, FrmFR>;
180
181class LWXC1_FT<string opstr, RegisterClass DRC, RegisterClass PRC,
182               InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
183  InstSE<(outs DRC:$fd), (ins PRC:$base, PRC:$index),
184         !strconcat(opstr, "\t$fd, ${index}(${base})"),
185         [(set DRC:$fd, (OpNode (add PRC:$base, PRC:$index)))], Itin, FrmFI> {
186  let AddedComplexity = 20;
187}
188
189class SWXC1_FT<string opstr, RegisterClass DRC, RegisterClass PRC,
190               InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
191  InstSE<(outs), (ins DRC:$fs, PRC:$base, PRC:$index),
192         !strconcat(opstr, "\t$fs, ${index}(${base})"),
193         [(OpNode DRC:$fs, (add PRC:$base, PRC:$index))], Itin, FrmFI> {
194  let AddedComplexity = 20;
195}
196
197class BC1F_FT<string opstr, InstrItinClass Itin,
198              SDPatternOperator Op = null_frag>  :
199  InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"),
200         [(MipsFPBrcond Op, bb:$offset)], Itin, FrmFI> {
201  let isBranch = 1;
202  let isTerminator = 1;
203  let hasDelaySlot = 1;
204  let Defs = [AT];
205  let Uses = [FCR31];
206}
207
208class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin,
209              SDPatternOperator OpNode = null_frag>  :
210  InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond),
211         !strconcat("c.$cond.", typestr, "\t$fs, $ft"),
212         [(OpNode RC:$fs, RC:$ft, imm:$cond)], Itin, FrmFR> {
213  let Defs = [FCR31];
214}
215
216//===----------------------------------------------------------------------===//
217// Floating Point Instructions
218//===----------------------------------------------------------------------===//
219def ROUND_W_S  : ABSS_FT<"round.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xc, 16>;
220def TRUNC_W_S  : ABSS_FT<"trunc.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xd, 16>;
221def CEIL_W_S   : ABSS_FT<"ceil.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xe, 16>;
222def FLOOR_W_S  : ABSS_FT<"floor.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xf, 16>;
223def CVT_W_S    : ABSS_FT<"cvt.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0x24, 16>;
224
225defm ROUND_W : ROUND_M<"round.w.d", IIFcvt>, ABSS_FM<0xc, 17>;
226defm TRUNC_W : ROUND_M<"trunc.w.d", IIFcvt>, ABSS_FM<0xd, 17>;
227defm CEIL_W  : ROUND_M<"ceil.w.d", IIFcvt>, ABSS_FM<0xe, 17>;
228defm FLOOR_W : ROUND_M<"floor.w.d", IIFcvt>, ABSS_FM<0xf, 17>;
229defm CVT_W   : ROUND_M<"cvt.w.d", IIFcvt>, ABSS_FM<0x24, 17>;
230
231let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
232  def ROUND_L_S : ABSS_FT<"round.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x8, 16>;
233  def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64, FGR64, IIFcvt>,
234                    ABSS_FM<0x8, 17>;
235  def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x9, 16>;
236  def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64, FGR64, IIFcvt>,
237                    ABSS_FM<0x9, 17>;
238  def CEIL_L_S  : ABSS_FT<"ceil.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0xa, 16>;
239  def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64, FGR64, IIFcvt>, ABSS_FM<0xa, 17>;
240  def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0xb, 16>;
241  def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64, FGR64, IIFcvt>,
242                    ABSS_FM<0xb, 17>;
243}
244
245def CVT_S_W : ABSS_FT<"cvt.s.w", FGR32, FGR32, IIFcvt>, ABSS_FM<0x20, 20>;
246def CVT_L_S : ABSS_FT<"cvt.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x25, 16>;
247def CVT_L_D64: ABSS_FT<"cvt.l.d", FGR64, FGR64, IIFcvt>, ABSS_FM<0x25, 17>;
248
249let Predicates = [NotFP64bit, HasStdEnc] in {
250  def CVT_S_D32 : ABSS_FT<"cvt.s.d", FGR32, AFGR64, IIFcvt>, ABSS_FM<0x20, 17>;
251  def CVT_D32_W : ABSS_FT<"cvt.d.w", AFGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 20>;
252  def CVT_D32_S : ABSS_FT<"cvt.d.s", AFGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 16>;
253}
254
255let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
256  def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32, FGR64, IIFcvt>, ABSS_FM<0x20, 17>;
257  def CVT_S_L   : ABSS_FT<"cvt.s.l", FGR32, FGR64, IIFcvt>, ABSS_FM<0x20, 21>;
258  def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 20>;
259  def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 16>;
260  def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64, FGR64, IIFcvt>, ABSS_FM<0x21, 21>;
261}
262
263let isPseudo = 1, isCodeGenOnly = 1 in {
264  def PseudoCVT_S_W : ABSS_FT<"", FGR32, CPURegs, IIFcvt>;
265  def PseudoCVT_D32_W : ABSS_FT<"", AFGR64, CPURegs, IIFcvt>;
266  def PseudoCVT_S_L : ABSS_FT<"", FGR64, CPU64Regs, IIFcvt>;
267  def PseudoCVT_D64_W : ABSS_FT<"", FGR64, CPURegs, IIFcvt>;
268  def PseudoCVT_D64_L : ABSS_FT<"", FGR64, CPU64Regs, IIFcvt>;
269}
270
271let Predicates = [NoNaNsFPMath, HasStdEnc] in {
272  def FABS_S : ABSS_FT<"abs.s", FGR32, FGR32, IIFcvt, fabs>, ABSS_FM<0x5, 16>;
273  def FNEG_S : ABSS_FT<"neg.s", FGR32, FGR32, IIFcvt, fneg>, ABSS_FM<0x7, 16>;
274  defm FABS : ABSS_M<"abs.d", IIFcvt, fabs>, ABSS_FM<0x5, 17>;
275  defm FNEG : ABSS_M<"neg.d", IIFcvt, fneg>, ABSS_FM<0x7, 17>;
276}
277
278def  FSQRT_S : ABSS_FT<"sqrt.s", FGR32, FGR32, IIFsqrtSingle, fsqrt>,
279               ABSS_FM<0x4, 16>;
280defm FSQRT : ABSS_M<"sqrt.d", IIFsqrtDouble, fsqrt>, ABSS_FM<0x4, 17>;
281
282// The odd-numbered registers are only referenced when doing loads,
283// stores, and moves between floating-point and integer registers.
284// When defining instructions, we reference all 32-bit registers,
285// regardless of register aliasing.
286
287/// Move Control Registers From/To CPU Registers
288def CFC1 : MFC1_FT_CCR<"cfc1", CPURegs, CCROpnd, IIFmove>, MFC1_FM<2>;
289def CTC1 : MTC1_FT_CCR<"ctc1", CCROpnd, CPURegs, IIFmove>, MFC1_FM<6>;
290def MFC1 : MFC1_FT<"mfc1", CPURegs, FGR32, IIFmove, bitconvert>, MFC1_FM<0>;
291def MTC1 : MTC1_FT<"mtc1", FGR32, CPURegs, IIFmove, bitconvert>, MFC1_FM<4>;
292def DMFC1 : MFC1_FT<"dmfc1", CPU64Regs, FGR64, IIFmove, bitconvert>, MFC1_FM<1>;
293def DMTC1 : MTC1_FT<"dmtc1", FGR64, CPU64Regs, IIFmove, bitconvert>, MFC1_FM<5>;
294
295def FMOV_S   : ABSS_FT<"mov.s", FGR32, FGR32, IIFmove>, ABSS_FM<0x6, 16>;
296def FMOV_D32 : ABSS_FT<"mov.d", AFGR64, AFGR64, IIFmove>, ABSS_FM<0x6, 17>,
297               Requires<[NotFP64bit, HasStdEnc]>;
298def FMOV_D64 : ABSS_FT<"mov.d", FGR64, FGR64, IIFmove>, ABSS_FM<0x6, 17>,
299               Requires<[IsFP64bit, HasStdEnc]> {
300  let DecoderNamespace = "Mips64";
301}
302
303/// Floating Point Memory Instructions
304let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in {
305  def LWC1_P8 : LW_FT<"lwc1", FGR32, IILoad, mem64, load>, LW_FM<0x31>;
306  def SWC1_P8 : SW_FT<"swc1", FGR32, IIStore, mem64, store>, LW_FM<0x39>;
307  def LDC164_P8 : LW_FT<"ldc1", FGR64, IILoad, mem64, load>, LW_FM<0x35> {
308    let isCodeGenOnly =1;
309  }
310  def SDC164_P8 : SW_FT<"sdc1", FGR64, IIStore, mem64, store>, LW_FM<0x3d> {
311    let isCodeGenOnly =1;
312  }
313}
314
315let Predicates = [NotN64, HasStdEnc] in {
316  def LWC1 : LW_FT<"lwc1", FGR32, IILoad, mem, load>, LW_FM<0x31>;
317  def SWC1 : SW_FT<"swc1", FGR32, IIStore, mem, store>, LW_FM<0x39>;
318}
319
320let Predicates = [NotN64, HasMips64, HasStdEnc],
321  DecoderNamespace = "Mips64" in {
322  def LDC164 : LW_FT<"ldc1", FGR64, IILoad, mem, load>, LW_FM<0x35>;
323  def SDC164 : SW_FT<"sdc1", FGR64, IIStore, mem, store>, LW_FM<0x3d>;
324}
325
326let Predicates = [NotN64, NotMips64, HasStdEnc] in {
327  let isPseudo = 1, isCodeGenOnly = 1 in {
328    def PseudoLDC1 : LW_FT<"", AFGR64, IILoad, mem, load>;
329    def PseudoSDC1 : SW_FT<"", AFGR64, IIStore, mem, store>;
330  }
331  def LDC1 : LW_FT<"ldc1", AFGR64, IILoad, mem>, LW_FM<0x35>;
332  def SDC1 : SW_FT<"sdc1", AFGR64, IIStore, mem>, LW_FM<0x3d>;
333}
334
335// Indexed loads and stores.
336let Predicates = [HasFPIdx, HasStdEnc] in {
337  def LWXC1 : LWXC1_FT<"lwxc1", FGR32, CPURegs, IILoad, load>, LWXC1_FM<0>;
338  def SWXC1 : SWXC1_FT<"swxc1", FGR32, CPURegs, IIStore, store>, SWXC1_FM<8>;
339}
340
341let Predicates = [HasMips32r2, NotMips64, HasStdEnc] in {
342  def LDXC1 : LWXC1_FT<"ldxc1", AFGR64, CPURegs, IILoad, load>, LWXC1_FM<1>;
343  def SDXC1 : SWXC1_FT<"sdxc1", AFGR64, CPURegs, IIStore, store>, SWXC1_FM<9>;
344}
345
346let Predicates = [HasMips64, NotN64, HasStdEnc], DecoderNamespace="Mips64" in {
347  def LDXC164 : LWXC1_FT<"ldxc1", FGR64, CPURegs, IILoad, load>, LWXC1_FM<1>;
348  def SDXC164 : SWXC1_FT<"sdxc1", FGR64, CPURegs, IIStore, store>, SWXC1_FM<9>;
349}
350
351// n64
352let Predicates = [IsN64, HasStdEnc], isCodeGenOnly=1 in {
353  def LWXC1_P8 : LWXC1_FT<"lwxc1", FGR32, CPU64Regs, IILoad, load>, LWXC1_FM<0>;
354  def LDXC164_P8 : LWXC1_FT<"ldxc1", FGR64, CPU64Regs, IILoad, load>,
355                   LWXC1_FM<1>;
356  def SWXC1_P8 : SWXC1_FT<"swxc1", FGR32, CPU64Regs, IIStore, store>,
357                 SWXC1_FM<8>;
358  def SDXC164_P8 : SWXC1_FT<"sdxc1", FGR64, CPU64Regs, IIStore, store>,
359                   SWXC1_FM<9>;
360}
361
362// Load/store doubleword indexed unaligned.
363let Predicates = [NotMips64, HasStdEnc] in {
364  def LUXC1 : LWXC1_FT<"luxc1", AFGR64, CPURegs, IILoad>, LWXC1_FM<0x5>;
365  def SUXC1 : SWXC1_FT<"suxc1", AFGR64, CPURegs, IIStore>, SWXC1_FM<0xd>;
366}
367
368let Predicates = [HasMips64, HasStdEnc],
369  DecoderNamespace="Mips64" in {
370  def LUXC164 : LWXC1_FT<"luxc1", FGR64, CPURegs, IILoad>, LWXC1_FM<0x5>;
371  def SUXC164 : SWXC1_FT<"suxc1", FGR64, CPURegs, IIStore>, SWXC1_FM<0xd>;
372}
373
374/// Floating-point Aritmetic
375def FADD_S : ADDS_FT<"add.s", FGR32, IIFadd, 1, fadd>, ADDS_FM<0x00, 16>;
376defm FADD : ADDS_M<"add.d", IIFadd, 1, fadd>, ADDS_FM<0x00, 17>;
377def FDIV_S : ADDS_FT<"div.s", FGR32, IIFdivSingle, 0, fdiv>, ADDS_FM<0x03, 16>;
378defm FDIV : ADDS_M<"div.d", IIFdivDouble, 0, fdiv>, ADDS_FM<0x03, 17>;
379def FMUL_S : ADDS_FT<"mul.s", FGR32, IIFmulSingle, 1, fmul>, ADDS_FM<0x02, 16>;
380defm FMUL : ADDS_M<"mul.d", IIFmulDouble, 1, fmul>, ADDS_FM<0x02, 17>;
381def FSUB_S : ADDS_FT<"sub.s", FGR32, IIFadd, 0, fsub>, ADDS_FM<0x01, 16>;
382defm FSUB : ADDS_M<"sub.d", IIFadd, 0, fsub>, ADDS_FM<0x01, 17>;
383
384let Predicates = [HasMips32r2, HasStdEnc] in {
385  def MADD_S : MADDS_FT<"madd.s", FGR32, IIFmulSingle, fadd>, MADDS_FM<4, 0>;
386  def MSUB_S : MADDS_FT<"msub.s", FGR32, IIFmulSingle, fsub>, MADDS_FM<5, 0>;
387}
388
389let Predicates = [HasMips32r2, NoNaNsFPMath, HasStdEnc] in {
390  def NMADD_S : NMADDS_FT<"nmadd.s", FGR32, IIFmulSingle, fadd>, MADDS_FM<6, 0>;
391  def NMSUB_S : NMADDS_FT<"nmsub.s", FGR32, IIFmulSingle, fsub>, MADDS_FM<7, 0>;
392}
393
394let Predicates = [HasMips32r2, NotFP64bit, HasStdEnc] in {
395  def MADD_D32 : MADDS_FT<"madd.d", AFGR64, IIFmulDouble, fadd>, MADDS_FM<4, 1>;
396  def MSUB_D32 : MADDS_FT<"msub.d", AFGR64, IIFmulDouble, fsub>, MADDS_FM<5, 1>;
397}
398
399let Predicates = [HasMips32r2, NotFP64bit, NoNaNsFPMath, HasStdEnc] in {
400  def NMADD_D32 : NMADDS_FT<"nmadd.d", AFGR64, IIFmulDouble, fadd>,
401                  MADDS_FM<6, 1>;
402  def NMSUB_D32 : NMADDS_FT<"nmsub.d", AFGR64, IIFmulDouble, fsub>,
403                  MADDS_FM<7, 1>;
404}
405
406let Predicates = [HasMips32r2, IsFP64bit, HasStdEnc], isCodeGenOnly=1 in {
407  def MADD_D64 : MADDS_FT<"madd.d", FGR64, IIFmulDouble, fadd>, MADDS_FM<4, 1>;
408  def MSUB_D64 : MADDS_FT<"msub.d", FGR64, IIFmulDouble, fsub>, MADDS_FM<5, 1>;
409}
410
411let Predicates = [HasMips32r2, IsFP64bit, NoNaNsFPMath, HasStdEnc],
412    isCodeGenOnly=1 in {
413  def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64, IIFmulDouble, fadd>,
414                  MADDS_FM<6, 1>;
415  def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64, IIFmulDouble, fsub>,
416                  MADDS_FM<7, 1>;
417}
418
419//===----------------------------------------------------------------------===//
420// Floating Point Branch Codes
421//===----------------------------------------------------------------------===//
422// Mips branch codes. These correspond to condcode in MipsInstrInfo.h.
423// They must be kept in synch.
424def MIPS_BRANCH_F  : PatLeaf<(i32 0)>;
425def MIPS_BRANCH_T  : PatLeaf<(i32 1)>;
426
427let DecoderMethod = "DecodeBC1" in {
428def BC1F : BC1F_FT<"bc1f", IIBranch, MIPS_BRANCH_F>, BC1F_FM<0, 0>;
429def BC1T : BC1F_FT<"bc1t", IIBranch, MIPS_BRANCH_T>, BC1F_FM<0, 1>;
430}
431//===----------------------------------------------------------------------===//
432// Floating Point Flag Conditions
433//===----------------------------------------------------------------------===//
434// Mips condition codes. They must correspond to condcode in MipsInstrInfo.h.
435// They must be kept in synch.
436def MIPS_FCOND_F    : PatLeaf<(i32 0)>;
437def MIPS_FCOND_UN   : PatLeaf<(i32 1)>;
438def MIPS_FCOND_OEQ  : PatLeaf<(i32 2)>;
439def MIPS_FCOND_UEQ  : PatLeaf<(i32 3)>;
440def MIPS_FCOND_OLT  : PatLeaf<(i32 4)>;
441def MIPS_FCOND_ULT  : PatLeaf<(i32 5)>;
442def MIPS_FCOND_OLE  : PatLeaf<(i32 6)>;
443def MIPS_FCOND_ULE  : PatLeaf<(i32 7)>;
444def MIPS_FCOND_SF   : PatLeaf<(i32 8)>;
445def MIPS_FCOND_NGLE : PatLeaf<(i32 9)>;
446def MIPS_FCOND_SEQ  : PatLeaf<(i32 10)>;
447def MIPS_FCOND_NGL  : PatLeaf<(i32 11)>;
448def MIPS_FCOND_LT   : PatLeaf<(i32 12)>;
449def MIPS_FCOND_NGE  : PatLeaf<(i32 13)>;
450def MIPS_FCOND_LE   : PatLeaf<(i32 14)>;
451def MIPS_FCOND_NGT  : PatLeaf<(i32 15)>;
452
453/// Floating Point Compare
454def FCMP_S32 : CEQS_FT<"s", FGR32, IIFcmp, MipsFPCmp>, CEQS_FM<16>;
455def FCMP_D32 : CEQS_FT<"d", AFGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>,
456               Requires<[NotFP64bit, HasStdEnc]>;
457let DecoderNamespace = "Mips64" in
458def FCMP_D64 : CEQS_FT<"d", FGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>,
459               Requires<[IsFP64bit, HasStdEnc]>;
460
461//===----------------------------------------------------------------------===//
462// Floating Point Pseudo-Instructions
463//===----------------------------------------------------------------------===//
464def MOVCCRToCCR : PseudoSE<(outs CCR:$dst), (ins CCROpnd:$src), []>;
465
466// This pseudo instr gets expanded into 2 mtc1 instrs after register
467// allocation.
468def BuildPairF64 :
469  PseudoSE<(outs AFGR64:$dst),
470           (ins CPURegs:$lo, CPURegs:$hi),
471           [(set AFGR64:$dst, (MipsBuildPairF64 CPURegs:$lo, CPURegs:$hi))]>;
472
473// This pseudo instr gets expanded into 2 mfc1 instrs after register
474// allocation.
475// if n is 0, lower part of src is extracted.
476// if n is 1, higher part of src is extracted.
477def ExtractElementF64 :
478  PseudoSE<(outs CPURegs:$dst), (ins AFGR64:$src, i32imm:$n),
479           [(set CPURegs:$dst, (MipsExtractElementF64 AFGR64:$src, imm:$n))]>;
480
481//===----------------------------------------------------------------------===//
482// Floating Point Patterns
483//===----------------------------------------------------------------------===//
484def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>;
485def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
486
487def : MipsPat<(f32 (sint_to_fp CPURegs:$src)), (PseudoCVT_S_W CPURegs:$src)>;
488def : MipsPat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S FGR32:$src))>;
489
490let Predicates = [NotFP64bit, HasStdEnc] in {
491  def : MipsPat<(f64 (sint_to_fp CPURegs:$src)),
492                (PseudoCVT_D32_W CPURegs:$src)>;
493  def : MipsPat<(i32 (fp_to_sint AFGR64:$src)),
494                (MFC1 (TRUNC_W_D32 AFGR64:$src))>;
495  def : MipsPat<(f32 (fround AFGR64:$src)), (CVT_S_D32 AFGR64:$src)>;
496  def : MipsPat<(f64 (fextend FGR32:$src)), (CVT_D32_S FGR32:$src)>;
497}
498
499let Predicates = [IsFP64bit, HasStdEnc] in {
500  def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>;
501  def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>;
502
503  def : MipsPat<(f64 (sint_to_fp CPURegs:$src)),
504                (PseudoCVT_D64_W CPURegs:$src)>;
505  def : MipsPat<(f32 (sint_to_fp CPU64Regs:$src)),
506                (EXTRACT_SUBREG (PseudoCVT_S_L CPU64Regs:$src), sub_32)>;
507  def : MipsPat<(f64 (sint_to_fp CPU64Regs:$src)),
508                (PseudoCVT_D64_L CPU64Regs:$src)>;
509
510  def : MipsPat<(i32 (fp_to_sint FGR64:$src)),
511                (MFC1 (TRUNC_W_D64 FGR64:$src))>;
512  def : MipsPat<(i64 (fp_to_sint FGR32:$src)), (DMFC1 (TRUNC_L_S FGR32:$src))>;
513  def : MipsPat<(i64 (fp_to_sint FGR64:$src)),
514                (DMFC1 (TRUNC_L_D64 FGR64:$src))>;
515
516  def : MipsPat<(f32 (fround FGR64:$src)), (CVT_S_D64 FGR64:$src)>;
517  def : MipsPat<(f64 (fextend FGR32:$src)), (CVT_D64_S FGR32:$src)>;
518}
519
520// Patterns for loads/stores with a reg+imm operand.
521let AddedComplexity = 40 in {
522  let Predicates = [IsN64, HasStdEnc] in {
523    def : LoadRegImmPat<LWC1_P8, f32, load>;
524    def : StoreRegImmPat<SWC1_P8, f32>;
525    def : LoadRegImmPat<LDC164_P8, f64, load>;
526    def : StoreRegImmPat<SDC164_P8, f64>;
527  }
528
529  let Predicates = [NotN64, HasStdEnc] in {
530    def : LoadRegImmPat<LWC1, f32, load>;
531    def : StoreRegImmPat<SWC1, f32>;
532  }
533
534  let Predicates = [NotN64, HasMips64, HasStdEnc] in {
535    def : LoadRegImmPat<LDC164, f64, load>;
536    def : StoreRegImmPat<SDC164, f64>;
537  }
538
539  let Predicates = [NotN64, NotMips64, HasStdEnc] in {
540    def : LoadRegImmPat<PseudoLDC1, f64, load>;
541    def : StoreRegImmPat<PseudoSDC1, f64>;
542  }
543}
544