MipsInstrFormats.td revision 089741479be03b625f5a8cc52e750b4e532338c6
1//===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Describe MIPS instructions format 12// 13// CPU INSTRUCTION FORMATS 14// 15// opcode - operation code. 16// rs - src reg. 17// rt - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr). 18// rd - dst reg, only used on 3 regs instr. 19// shamt - only used on shift instructions, contains the shift amount. 20// funct - combined with opcode field give us an operation code. 21// 22//===----------------------------------------------------------------------===// 23 24// Format specifies the encoding used by the instruction. This is part of the 25// ad-hoc solution used to emit machine instruction encodings by our machine 26// code emitter. 27class Format<bits<4> val> { 28 bits<4> Value = val; 29} 30 31def Pseudo : Format<0>; 32def FrmR : Format<1>; 33def FrmI : Format<2>; 34def FrmJ : Format<3>; 35def FrmFR : Format<4>; 36def FrmFI : Format<5>; 37def FrmOther : Format<6>; // Instruction w/ a custom format 38 39class MMRel; 40 41def Std2MicroMips : InstrMapping { 42 let FilterClass = "MMRel"; 43 // Instructions with the same BaseOpcode and isNVStore values form a row. 44 let RowFields = ["BaseOpcode"]; 45 // Instructions with the same predicate sense form a column. 46 let ColFields = ["Arch"]; 47 // The key column is the unpredicated instructions. 48 let KeyCol = ["se"]; 49 // Value columns are PredSense=true and PredSense=false 50 let ValueCols = [["se"], ["micromips"]]; 51} 52 53class StdArch { 54 string Arch = "se"; 55} 56 57// Generic Mips Format 58class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern, 59 InstrItinClass itin, Format f>: Instruction 60{ 61 field bits<32> Inst; 62 Format Form = f; 63 64 let Namespace = "Mips"; 65 66 let Size = 4; 67 68 bits<6> Opcode = 0; 69 70 // Top 6 bits are the 'opcode' field 71 let Inst{31-26} = Opcode; 72 73 let OutOperandList = outs; 74 let InOperandList = ins; 75 76 let AsmString = asmstr; 77 let Pattern = pattern; 78 let Itinerary = itin; 79 80 // 81 // Attributes specific to Mips instructions... 82 // 83 bits<4> FormBits = Form.Value; 84 85 // TSFlags layout should be kept in sync with MipsInstrInfo.h. 86 let TSFlags{3-0} = FormBits; 87 88 let DecoderNamespace = "Mips"; 89 90 field bits<32> SoftFail = 0; 91} 92 93// Mips32/64 Instruction Format 94class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern, 95 InstrItinClass itin, Format f, string opstr = ""> : 96 MipsInst<outs, ins, asmstr, pattern, itin, f> { 97 let Predicates = [HasStdEnc]; 98 string BaseOpcode = opstr; 99 string Arch; 100} 101 102// Mips Pseudo Instructions Format 103class MipsPseudo<dag outs, dag ins, list<dag> pattern, 104 InstrItinClass itin = IIPseudo> : 105 MipsInst<outs, ins, "", pattern, itin, Pseudo> { 106 let isCodeGenOnly = 1; 107 let isPseudo = 1; 108} 109 110// Mips32/64 Pseudo Instruction Format 111class PseudoSE<dag outs, dag ins, list<dag> pattern, 112 InstrItinClass itin = IIPseudo>: 113 MipsPseudo<outs, ins, pattern, itin> { 114 let Predicates = [HasStdEnc]; 115} 116 117// Pseudo-instructions for alternate assembly syntax (never used by codegen). 118// These are aliases that require C++ handling to convert to the target 119// instruction, while InstAliases can be handled directly by tblgen. 120class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>: 121 MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> { 122 let isPseudo = 1; 123 let Pattern = []; 124} 125//===----------------------------------------------------------------------===// 126// Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|> 127//===----------------------------------------------------------------------===// 128 129class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr, 130 list<dag> pattern, InstrItinClass itin>: 131 InstSE<outs, ins, asmstr, pattern, itin, FrmR> 132{ 133 bits<5> rd; 134 bits<5> rs; 135 bits<5> rt; 136 bits<5> shamt; 137 bits<6> funct; 138 139 let Opcode = op; 140 let funct = _funct; 141 142 let Inst{25-21} = rs; 143 let Inst{20-16} = rt; 144 let Inst{15-11} = rd; 145 let Inst{10-6} = shamt; 146 let Inst{5-0} = funct; 147} 148 149//===----------------------------------------------------------------------===// 150// Format I instruction class in Mips : <|opcode|rs|rt|immediate|> 151//===----------------------------------------------------------------------===// 152 153class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 154 InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI> 155{ 156 bits<5> rt; 157 bits<5> rs; 158 bits<16> imm16; 159 160 let Opcode = op; 161 162 let Inst{25-21} = rs; 163 let Inst{20-16} = rt; 164 let Inst{15-0} = imm16; 165} 166 167class BranchBase<bits<6> op, dag outs, dag ins, string asmstr, 168 list<dag> pattern, InstrItinClass itin>: 169 InstSE<outs, ins, asmstr, pattern, itin, FrmI> 170{ 171 bits<5> rs; 172 bits<5> rt; 173 bits<16> imm16; 174 175 let Opcode = op; 176 177 let Inst{25-21} = rs; 178 let Inst{20-16} = rt; 179 let Inst{15-0} = imm16; 180} 181 182//===----------------------------------------------------------------------===// 183// Format J instruction class in Mips : <|opcode|address|> 184//===----------------------------------------------------------------------===// 185 186class FJ<bits<6> op> 187{ 188 bits<26> target; 189 190 bits<32> Inst; 191 192 let Inst{31-26} = op; 193 let Inst{25-0} = target; 194} 195 196//===----------------------------------------------------------------------===// 197// MFC instruction class in Mips : <|op|mf|rt|rd|0000000|sel|> 198//===----------------------------------------------------------------------===// 199class MFC3OP_FM<bits<6> op, bits<5> mfmt> 200{ 201 bits<5> rt; 202 bits<5> rd; 203 bits<3> sel; 204 205 bits<32> Inst; 206 207 let Inst{31-26} = op; 208 let Inst{25-21} = mfmt; 209 let Inst{20-16} = rt; 210 let Inst{15-11} = rd; 211 let Inst{10-3} = 0; 212 let Inst{2-0} = sel; 213} 214 215class ADD_FM<bits<6> op, bits<6> funct> : StdArch { 216 bits<5> rd; 217 bits<5> rs; 218 bits<5> rt; 219 220 bits<32> Inst; 221 222 let Inst{31-26} = op; 223 let Inst{25-21} = rs; 224 let Inst{20-16} = rt; 225 let Inst{15-11} = rd; 226 let Inst{10-6} = 0; 227 let Inst{5-0} = funct; 228} 229 230class ADDI_FM<bits<6> op> : StdArch { 231 bits<5> rs; 232 bits<5> rt; 233 bits<16> imm16; 234 235 bits<32> Inst; 236 237 let Inst{31-26} = op; 238 let Inst{25-21} = rs; 239 let Inst{20-16} = rt; 240 let Inst{15-0} = imm16; 241} 242 243class SRA_FM<bits<6> funct, bit rotate> : StdArch { 244 bits<5> rd; 245 bits<5> rt; 246 bits<5> shamt; 247 248 bits<32> Inst; 249 250 let Inst{31-26} = 0; 251 let Inst{25-22} = 0; 252 let Inst{21} = rotate; 253 let Inst{20-16} = rt; 254 let Inst{15-11} = rd; 255 let Inst{10-6} = shamt; 256 let Inst{5-0} = funct; 257} 258 259class SRLV_FM<bits<6> funct, bit rotate> : StdArch { 260 bits<5> rd; 261 bits<5> rt; 262 bits<5> rs; 263 264 bits<32> Inst; 265 266 let Inst{31-26} = 0; 267 let Inst{25-21} = rs; 268 let Inst{20-16} = rt; 269 let Inst{15-11} = rd; 270 let Inst{10-7} = 0; 271 let Inst{6} = rotate; 272 let Inst{5-0} = funct; 273} 274 275class BEQ_FM<bits<6> op> { 276 bits<5> rs; 277 bits<5> rt; 278 bits<16> offset; 279 280 bits<32> Inst; 281 282 let Inst{31-26} = op; 283 let Inst{25-21} = rs; 284 let Inst{20-16} = rt; 285 let Inst{15-0} = offset; 286} 287 288class BGEZ_FM<bits<6> op, bits<5> funct> { 289 bits<5> rs; 290 bits<16> offset; 291 292 bits<32> Inst; 293 294 let Inst{31-26} = op; 295 let Inst{25-21} = rs; 296 let Inst{20-16} = funct; 297 let Inst{15-0} = offset; 298} 299 300class B_FM { 301 bits<16> offset; 302 303 bits<32> Inst; 304 305 let Inst{31-26} = 4; 306 let Inst{25-21} = 0; 307 let Inst{20-16} = 0; 308 let Inst{15-0} = offset; 309} 310 311class SLTI_FM<bits<6> op> : StdArch { 312 bits<5> rt; 313 bits<5> rs; 314 bits<16> imm16; 315 316 bits<32> Inst; 317 318 let Inst{31-26} = op; 319 let Inst{25-21} = rs; 320 let Inst{20-16} = rt; 321 let Inst{15-0} = imm16; 322} 323 324class MFLO_FM<bits<6> funct> { 325 bits<5> rd; 326 327 bits<32> Inst; 328 329 let Inst{31-26} = 0; 330 let Inst{25-16} = 0; 331 let Inst{15-11} = rd; 332 let Inst{10-6} = 0; 333 let Inst{5-0} = funct; 334} 335 336class MTLO_FM<bits<6> funct> { 337 bits<5> rs; 338 339 bits<32> Inst; 340 341 let Inst{31-26} = 0; 342 let Inst{25-21} = rs; 343 let Inst{20-6} = 0; 344 let Inst{5-0} = funct; 345} 346 347class SEB_FM<bits<5> funct, bits<6> funct2> { 348 bits<5> rd; 349 bits<5> rt; 350 351 bits<32> Inst; 352 353 let Inst{31-26} = 0x1f; 354 let Inst{25-21} = 0; 355 let Inst{20-16} = rt; 356 let Inst{15-11} = rd; 357 let Inst{10-6} = funct; 358 let Inst{5-0} = funct2; 359} 360 361class CLO_FM<bits<6> funct> { 362 bits<5> rd; 363 bits<5> rs; 364 bits<5> rt; 365 366 bits<32> Inst; 367 368 let Inst{31-26} = 0x1c; 369 let Inst{25-21} = rs; 370 let Inst{20-16} = rt; 371 let Inst{15-11} = rd; 372 let Inst{10-6} = 0; 373 let Inst{5-0} = funct; 374 let rt = rd; 375} 376 377class LUI_FM { 378 bits<5> rt; 379 bits<16> imm16; 380 381 bits<32> Inst; 382 383 let Inst{31-26} = 0xf; 384 let Inst{25-21} = 0; 385 let Inst{20-16} = rt; 386 let Inst{15-0} = imm16; 387} 388 389class JALR_FM { 390 bits<5> rd; 391 bits<5> rs; 392 393 bits<32> Inst; 394 395 let Inst{31-26} = 0; 396 let Inst{25-21} = rs; 397 let Inst{20-16} = 0; 398 let Inst{15-11} = rd; 399 let Inst{10-6} = 0; 400 let Inst{5-0} = 9; 401} 402 403class BAL_FM { 404 bits<16> offset; 405 406 bits<32> Inst; 407 408 let Inst{31-26} = 1; 409 let Inst{25-21} = 0; 410 let Inst{20-16} = 0x11; 411 let Inst{15-0} = offset; 412} 413 414class BGEZAL_FM<bits<5> funct> { 415 bits<5> rs; 416 bits<16> offset; 417 418 bits<32> Inst; 419 420 let Inst{31-26} = 1; 421 let Inst{25-21} = rs; 422 let Inst{20-16} = funct; 423 let Inst{15-0} = offset; 424} 425 426class SYNC_FM { 427 bits<5> stype; 428 429 bits<32> Inst; 430 431 let Inst{31-26} = 0; 432 let Inst{10-6} = stype; 433 let Inst{5-0} = 0xf; 434} 435 436class MULT_FM<bits<6> op, bits<6> funct> : StdArch { 437 bits<5> rs; 438 bits<5> rt; 439 440 bits<32> Inst; 441 442 let Inst{31-26} = op; 443 let Inst{25-21} = rs; 444 let Inst{20-16} = rt; 445 let Inst{15-6} = 0; 446 let Inst{5-0} = funct; 447} 448 449class EXT_FM<bits<6> funct> { 450 bits<5> rt; 451 bits<5> rs; 452 bits<5> pos; 453 bits<5> size; 454 455 bits<32> Inst; 456 457 let Inst{31-26} = 0x1f; 458 let Inst{25-21} = rs; 459 let Inst{20-16} = rt; 460 let Inst{15-11} = size; 461 let Inst{10-6} = pos; 462 let Inst{5-0} = funct; 463} 464 465class RDHWR_FM { 466 bits<5> rt; 467 bits<5> rd; 468 469 bits<32> Inst; 470 471 let Inst{31-26} = 0x1f; 472 let Inst{25-21} = 0; 473 let Inst{20-16} = rt; 474 let Inst{15-11} = rd; 475 let Inst{10-6} = 0; 476 let Inst{5-0} = 0x3b; 477} 478 479//===----------------------------------------------------------------------===// 480// 481// FLOATING POINT INSTRUCTION FORMATS 482// 483// opcode - operation code. 484// fs - src reg. 485// ft - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr). 486// fd - dst reg, only used on 3 regs instr. 487// fmt - double or single precision. 488// funct - combined with opcode field give us an operation code. 489// 490//===----------------------------------------------------------------------===// 491 492//===----------------------------------------------------------------------===// 493// Format FI instruction class in Mips : <|opcode|base|ft|immediate|> 494//===----------------------------------------------------------------------===// 495 496class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>: 497 InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFI> 498{ 499 bits<5> ft; 500 bits<5> base; 501 bits<16> imm16; 502 503 let Opcode = op; 504 505 let Inst{25-21} = base; 506 let Inst{20-16} = ft; 507 let Inst{15-0} = imm16; 508} 509 510class ADDS_FM<bits<6> funct, bits<5> fmt> { 511 bits<5> fd; 512 bits<5> fs; 513 bits<5> ft; 514 515 bits<32> Inst; 516 517 let Inst{31-26} = 0x11; 518 let Inst{25-21} = fmt; 519 let Inst{20-16} = ft; 520 let Inst{15-11} = fs; 521 let Inst{10-6} = fd; 522 let Inst{5-0} = funct; 523} 524 525class ABSS_FM<bits<6> funct, bits<5> fmt> { 526 bits<5> fd; 527 bits<5> fs; 528 529 bits<32> Inst; 530 531 let Inst{31-26} = 0x11; 532 let Inst{25-21} = fmt; 533 let Inst{20-16} = 0; 534 let Inst{15-11} = fs; 535 let Inst{10-6} = fd; 536 let Inst{5-0} = funct; 537} 538 539class MFC1_FM<bits<5> funct> { 540 bits<5> rt; 541 bits<5> fs; 542 543 bits<32> Inst; 544 545 let Inst{31-26} = 0x11; 546 let Inst{25-21} = funct; 547 let Inst{20-16} = rt; 548 let Inst{15-11} = fs; 549 let Inst{10-0} = 0; 550} 551 552class LW_FM<bits<6> op> : StdArch { 553 bits<5> rt; 554 bits<21> addr; 555 556 bits<32> Inst; 557 558 let Inst{31-26} = op; 559 let Inst{25-21} = addr{20-16}; 560 let Inst{20-16} = rt; 561 let Inst{15-0} = addr{15-0}; 562} 563 564class MADDS_FM<bits<3> funct, bits<3> fmt> { 565 bits<5> fd; 566 bits<5> fr; 567 bits<5> fs; 568 bits<5> ft; 569 570 bits<32> Inst; 571 572 let Inst{31-26} = 0x13; 573 let Inst{25-21} = fr; 574 let Inst{20-16} = ft; 575 let Inst{15-11} = fs; 576 let Inst{10-6} = fd; 577 let Inst{5-3} = funct; 578 let Inst{2-0} = fmt; 579} 580 581class LWXC1_FM<bits<6> funct> { 582 bits<5> fd; 583 bits<5> base; 584 bits<5> index; 585 586 bits<32> Inst; 587 588 let Inst{31-26} = 0x13; 589 let Inst{25-21} = base; 590 let Inst{20-16} = index; 591 let Inst{15-11} = 0; 592 let Inst{10-6} = fd; 593 let Inst{5-0} = funct; 594} 595 596class SWXC1_FM<bits<6> funct> { 597 bits<5> fs; 598 bits<5> base; 599 bits<5> index; 600 601 bits<32> Inst; 602 603 let Inst{31-26} = 0x13; 604 let Inst{25-21} = base; 605 let Inst{20-16} = index; 606 let Inst{15-11} = fs; 607 let Inst{10-6} = 0; 608 let Inst{5-0} = funct; 609} 610 611class BC1F_FM<bit nd, bit tf> { 612 bits<16> offset; 613 614 bits<32> Inst; 615 616 let Inst{31-26} = 0x11; 617 let Inst{25-21} = 0x8; 618 let Inst{20-18} = 0; // cc 619 let Inst{17} = nd; 620 let Inst{16} = tf; 621 let Inst{15-0} = offset; 622} 623 624class CEQS_FM<bits<5> fmt> { 625 bits<5> fs; 626 bits<5> ft; 627 bits<4> cond; 628 629 bits<32> Inst; 630 631 let Inst{31-26} = 0x11; 632 let Inst{25-21} = fmt; 633 let Inst{20-16} = ft; 634 let Inst{15-11} = fs; 635 let Inst{10-8} = 0; // cc 636 let Inst{7-4} = 0x3; 637 let Inst{3-0} = cond; 638} 639 640class CMov_I_F_FM<bits<6> funct, bits<5> fmt> { 641 bits<5> fd; 642 bits<5> fs; 643 bits<5> rt; 644 645 bits<32> Inst; 646 647 let Inst{31-26} = 0x11; 648 let Inst{25-21} = fmt; 649 let Inst{20-16} = rt; 650 let Inst{15-11} = fs; 651 let Inst{10-6} = fd; 652 let Inst{5-0} = funct; 653} 654 655class CMov_F_I_FM<bit tf> { 656 bits<5> rd; 657 bits<5> rs; 658 659 bits<32> Inst; 660 661 let Inst{31-26} = 0; 662 let Inst{25-21} = rs; 663 let Inst{20-18} = 0; // cc 664 let Inst{17} = 0; 665 let Inst{16} = tf; 666 let Inst{15-11} = rd; 667 let Inst{10-6} = 0; 668 let Inst{5-0} = 1; 669} 670 671class CMov_F_F_FM<bits<5> fmt, bit tf> { 672 bits<5> fd; 673 bits<5> fs; 674 675 bits<32> Inst; 676 677 let Inst{31-26} = 0x11; 678 let Inst{25-21} = fmt; 679 let Inst{20-18} = 0; // cc 680 let Inst{17} = 0; 681 let Inst{16} = tf; 682 let Inst{15-11} = fs; 683 let Inst{10-6} = fd; 684 let Inst{5-0} = 0x11; 685} 686