MipsInstrFormats.td revision 0c66403efdf88ff4f247b6a9f45339bb3a893235 
1//===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11//  Describe MIPS instructions format
12//
13//  CPU INSTRUCTION FORMATS
14//
15//  opcode  - operation code.
16//  rs      - src reg.
17//  rt      - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
18//  rd      - dst reg, only used on 3 regs instr.
19//  shamt   - only used on shift instructions, contains the shift amount.
20//  funct   - combined with opcode field give us an operation code.
21//
22//===----------------------------------------------------------------------===//
23
24// Format specifies the encoding used by the instruction.  This is part of the
25// ad-hoc solution used to emit machine instruction encodings by our machine
26// code emitter.
27class Format<bits<4> val> {
28  bits<4> Value = val;
29}
30
31def Pseudo    : Format<0>;
32def FrmR      : Format<1>;
33def FrmI      : Format<2>;
34def FrmJ      : Format<3>;
35def FrmFR     : Format<4>;
36def FrmFI     : Format<5>;
37def FrmOther  : Format<6>; // Instruction w/ a custom format
38
39// Generic Mips Format
40class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
41               InstrItinClass itin, Format f>: Instruction
42{
43  field bits<32> Inst;
44  Format Form = f;
45
46  let Namespace = "Mips";
47
48  let Size = 4;
49
50  bits<6> Opcode = 0;
51
52  // Top 6 bits are the 'opcode' field
53  let Inst{31-26} = Opcode;
54
55  let OutOperandList = outs;
56  let InOperandList  = ins;
57
58  let AsmString   = asmstr;
59  let Pattern     = pattern;
60  let Itinerary   = itin;
61
62  //
63  // Attributes specific to Mips instructions...
64  //
65  bits<4> FormBits = Form.Value;
66
67  // TSFlags layout should be kept in sync with MipsInstrInfo.h.
68  let TSFlags{3-0}   = FormBits;
69
70  let DecoderNamespace = "Mips";
71
72  field bits<32> SoftFail = 0;
73}
74
75// Mips32/64 Instruction Format
76class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
77             InstrItinClass itin, Format f>:
78  MipsInst<outs, ins, asmstr, pattern, itin, f> {
79  let Predicates = [HasStdEnc];
80}
81
82// Mips Pseudo Instructions Format
83class MipsPseudo<dag outs, dag ins, list<dag> pattern,
84                 InstrItinClass itin = IIPseudo> :
85  MipsInst<outs, ins, "", pattern, itin, Pseudo> {
86  let isCodeGenOnly = 1;
87  let isPseudo = 1;
88}
89
90// Mips32/64 Pseudo Instruction Format
91class PseudoSE<dag outs, dag ins, list<dag> pattern,
92               InstrItinClass itin = IIPseudo>:
93  MipsPseudo<outs, ins, pattern, itin> {
94  let Predicates = [HasStdEnc];
95}
96
97// Pseudo-instructions for alternate assembly syntax (never used by codegen).
98// These are aliases that require C++ handling to convert to the target
99// instruction, while InstAliases can be handled directly by tblgen.
100class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>:
101  MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> {
102  let isPseudo = 1;
103  let Pattern = [];
104}
105//===----------------------------------------------------------------------===//
106// Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
107//===----------------------------------------------------------------------===//
108
109class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
110         list<dag> pattern, InstrItinClass itin>:
111  InstSE<outs, ins, asmstr, pattern, itin, FrmR>
112{
113  bits<5>  rd;
114  bits<5>  rs;
115  bits<5>  rt;
116  bits<5>  shamt;
117  bits<6>  funct;
118
119  let Opcode = op;
120  let funct  = _funct;
121
122  let Inst{25-21} = rs;
123  let Inst{20-16} = rt;
124  let Inst{15-11} = rd;
125  let Inst{10-6}  = shamt;
126  let Inst{5-0}   = funct;
127}
128
129//===----------------------------------------------------------------------===//
130// Format I instruction class in Mips : <|opcode|rs|rt|immediate|>
131//===----------------------------------------------------------------------===//
132
133class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
134         InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI>
135{
136  bits<5>  rt;
137  bits<5>  rs;
138  bits<16> imm16;
139
140  let Opcode = op;
141
142  let Inst{25-21} = rs;
143  let Inst{20-16} = rt;
144  let Inst{15-0}  = imm16;
145}
146
147class BranchBase<bits<6> op, dag outs, dag ins, string asmstr,
148                  list<dag> pattern, InstrItinClass itin>:
149  InstSE<outs, ins, asmstr, pattern, itin, FrmI>
150{
151  bits<5>  rs;
152  bits<5>  rt;
153  bits<16> imm16;
154
155  let Opcode = op;
156
157  let Inst{25-21} = rs;
158  let Inst{20-16} = rt;
159  let Inst{15-0}  = imm16;
160}
161
162//===----------------------------------------------------------------------===//
163// Format J instruction class in Mips : <|opcode|address|>
164//===----------------------------------------------------------------------===//
165
166class FJ<bits<6> op>
167{
168  bits<26> target;
169
170  bits<32> Inst;
171
172  let Inst{31-26} = op;
173  let Inst{25-0}  = target;
174}
175
176//===----------------------------------------------------------------------===//
177// MFC instruction class in Mips : <|op|mf|rt|rd|0000000|sel|>
178//===----------------------------------------------------------------------===//
179class MFC3OP_FM<bits<6> op, bits<5> mfmt>
180{
181  bits<5> rt;
182  bits<5> rd;
183  bits<3> sel;
184
185  bits<32> Inst;
186
187  let Inst{31-26} = op;
188  let Inst{25-21} = mfmt;
189  let Inst{20-16} = rt;
190  let Inst{15-11} = rd;
191  let Inst{10-3}  = 0;
192  let Inst{2-0}   = sel;
193}
194
195class ADD_FM<bits<6> op, bits<6> funct> {
196  bits<5> rd;
197  bits<5> rs;
198  bits<5> rt;
199
200  bits<32> Inst;
201
202  let Inst{31-26} = op;
203  let Inst{25-21} = rs;
204  let Inst{20-16} = rt;
205  let Inst{15-11} = rd;
206  let Inst{10-6}  = 0;
207  let Inst{5-0}   = funct;
208}
209
210class ADDI_FM<bits<6> op> {
211  bits<5>  rs;
212  bits<5>  rt;
213  bits<16> imm16;
214
215  bits<32> Inst;
216
217  let Inst{31-26} = op;
218  let Inst{25-21} = rs;
219  let Inst{20-16} = rt;
220  let Inst{15-0}  = imm16;
221}
222
223class SRA_FM<bits<6> funct, bit rotate> {
224  bits<5> rd;
225  bits<5> rt;
226  bits<5> shamt;
227
228  bits<32> Inst;
229
230  let Inst{31-26} = 0;
231  let Inst{25-22} = 0;
232  let Inst{21}    = rotate;
233  let Inst{20-16} = rt;
234  let Inst{15-11} = rd;
235  let Inst{10-6}  = shamt;
236  let Inst{5-0}   = funct;
237}
238
239class SRLV_FM<bits<6> funct, bit rotate> {
240  bits<5> rd;
241  bits<5> rt;
242  bits<5> rs;
243
244  bits<32> Inst;
245
246  let Inst{31-26} = 0;
247  let Inst{25-21} = rs;
248  let Inst{20-16} = rt;
249  let Inst{15-11} = rd;
250  let Inst{10-7}  = 0;
251  let Inst{6}     = rotate;
252  let Inst{5-0}   = funct;
253}
254
255class BEQ_FM<bits<6> op> {
256  bits<5>  rs;
257  bits<5>  rt;
258  bits<16> offset;
259
260  bits<32> Inst;
261
262  let Inst{31-26} = op;
263  let Inst{25-21} = rs;
264  let Inst{20-16} = rt;
265  let Inst{15-0}  = offset;
266}
267
268class BGEZ_FM<bits<6> op, bits<5> funct> {
269  bits<5>  rs;
270  bits<16> offset;
271
272  bits<32> Inst;
273
274  let Inst{31-26} = op;
275  let Inst{25-21} = rs;
276  let Inst{20-16} = funct;
277  let Inst{15-0}  = offset;
278}
279
280class B_FM {
281  bits<16> offset;
282
283  bits<32> Inst;
284
285  let Inst{31-26} = 4;
286  let Inst{25-21} = 0;
287  let Inst{20-16} = 0;
288  let Inst{15-0}  = offset;
289}
290
291class SLTI_FM<bits<6> op> {
292  bits<5> rt;
293  bits<5> rs;
294  bits<16> imm16;
295
296  bits<32> Inst;
297
298  let Inst{31-26} = op;
299  let Inst{25-21} = rs;
300  let Inst{20-16} = rt;
301  let Inst{15-0}  = imm16;
302}
303
304class MFLO_FM<bits<6> funct> {
305  bits<5> rd;
306
307  bits<32> Inst;
308
309  let Inst{31-26} = 0;
310  let Inst{25-16} = 0;
311  let Inst{15-11} = rd;
312  let Inst{10-6}  = 0;
313  let Inst{5-0}   = funct;
314}
315
316class MTLO_FM<bits<6> funct> {
317  bits<5> rs;
318
319  bits<32> Inst;
320
321  let Inst{31-26} = 0;
322  let Inst{25-21} = rs;
323  let Inst{20-6}  = 0;
324  let Inst{5-0}   = funct;
325}
326
327class SEB_FM<bits<5> funct, bits<6> funct2> {
328  bits<5> rd;
329  bits<5> rt;
330
331  bits<32> Inst;
332
333  let Inst{31-26} = 0x1f;
334  let Inst{25-21} = 0;
335  let Inst{20-16} = rt;
336  let Inst{15-11} = rd;
337  let Inst{10-6}  = funct;
338  let Inst{5-0}   = funct2;
339}
340
341class CLO_FM<bits<6> funct> {
342  bits<5> rd;
343  bits<5> rs;
344  bits<5> rt;
345
346  bits<32> Inst;
347
348  let Inst{31-26} = 0x1c;
349  let Inst{25-21} = rs;
350  let Inst{20-16} = rt;
351  let Inst{15-11} = rd;
352  let Inst{10-6}  = 0;
353  let Inst{5-0}   = funct;
354  let rt = rd;
355}
356
357class LUI_FM {
358  bits<5> rt;
359  bits<16> imm16;
360
361  bits<32> Inst;
362
363  let Inst{31-26} = 0xf;
364  let Inst{25-21} = 0;
365  let Inst{20-16} = rt;
366  let Inst{15-0}  = imm16;
367}
368
369class JALR_FM {
370  bits<5> rd;
371  bits<5> rs;
372
373  bits<32> Inst;
374
375  let Inst{31-26} = 0;
376  let Inst{25-21} = rs;
377  let Inst{20-16} = 0;
378  let Inst{15-11} = rd;
379  let Inst{10-6}  = 0;
380  let Inst{5-0}   = 9;
381}
382
383class BAL_FM {
384  bits<16> offset;
385
386  bits<32> Inst;
387
388  let Inst{31-26} = 1;
389  let Inst{25-21} = 0;
390  let Inst{20-16} = 0x11;
391  let Inst{15-0}  = offset;
392}
393
394class BGEZAL_FM<bits<5> funct> {
395  bits<5>  rs;
396  bits<16> offset;
397
398  bits<32> Inst;
399
400  let Inst{31-26} = 1;
401  let Inst{25-21} = rs;
402  let Inst{20-16} = funct;
403  let Inst{15-0}  = offset;
404}
405
406class SYNC_FM {
407  bits<5> stype;
408
409  bits<32> Inst;
410
411  let Inst{31-26} = 0;
412  let Inst{10-6}  = stype;
413  let Inst{5-0}   = 0xf;
414}
415
416class MULT_FM<bits<6> op, bits<6> funct> {
417  bits<5>  rs;
418  bits<5>  rt;
419
420  bits<32> Inst;
421
422  let Inst{31-26} = op;
423  let Inst{25-21} = rs;
424  let Inst{20-16} = rt;
425  let Inst{15-6}  = 0;
426  let Inst{5-0}   = funct;
427}
428
429class EXT_FM<bits<6> funct> {
430  bits<5> rt;
431  bits<5> rs;
432  bits<5> pos;
433  bits<5> size;
434
435  bits<32> Inst;
436
437  let Inst{31-26} = 0x1f;
438  let Inst{25-21} = rs;
439  let Inst{20-16} = rt;
440  let Inst{15-11} = size;
441  let Inst{10-6}  = pos;
442  let Inst{5-0}   = funct;
443}
444
445class RDHWR_FM {
446  bits<5> rt;
447  bits<5> rd;
448
449  bits<32> Inst;
450
451  let Inst{31-26} = 0x1f;
452  let Inst{25-21} = 0;
453  let Inst{20-16} = rt;
454  let Inst{15-11} = rd;
455  let Inst{10-6}  = 0;
456  let Inst{5-0}   = 0x3b;
457}
458
459//===----------------------------------------------------------------------===//
460//
461//  FLOATING POINT INSTRUCTION FORMATS
462//
463//  opcode  - operation code.
464//  fs      - src reg.
465//  ft      - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
466//  fd      - dst reg, only used on 3 regs instr.
467//  fmt     - double or single precision.
468//  funct   - combined with opcode field give us an operation code.
469//
470//===----------------------------------------------------------------------===//
471
472//===----------------------------------------------------------------------===//
473// Format FI instruction class in Mips : <|opcode|base|ft|immediate|>
474//===----------------------------------------------------------------------===//
475
476class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
477  InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFI>
478{
479  bits<5>  ft;
480  bits<5>  base;
481  bits<16> imm16;
482
483  let Opcode = op;
484
485  let Inst{25-21} = base;
486  let Inst{20-16} = ft;
487  let Inst{15-0}  = imm16;
488}
489
490class ADDS_FM<bits<6> funct, bits<5> fmt> {
491  bits<5> fd;
492  bits<5> fs;
493  bits<5> ft;
494
495  bits<32> Inst;
496
497  let Inst{31-26} = 0x11;
498  let Inst{25-21} = fmt;
499  let Inst{20-16} = ft;
500  let Inst{15-11} = fs;
501  let Inst{10-6}  = fd;
502  let Inst{5-0}   = funct;
503}
504
505class ABSS_FM<bits<6> funct, bits<5> fmt> {
506  bits<5> fd;
507  bits<5> fs;
508
509  bits<32> Inst;
510
511  let Inst{31-26} = 0x11;
512  let Inst{25-21} = fmt;
513  let Inst{20-16} = 0;
514  let Inst{15-11} = fs;
515  let Inst{10-6}  = fd;
516  let Inst{5-0}   = funct;
517}
518
519class MFC1_FM<bits<5> funct> {
520  bits<5> rt;
521  bits<5> fs;
522
523  bits<32> Inst;
524
525  let Inst{31-26} = 0x11;
526  let Inst{25-21} = funct;
527  let Inst{20-16} = rt;
528  let Inst{15-11} = fs;
529  let Inst{10-0}  = 0;
530}
531
532class LW_FM<bits<6> op> {
533  bits<5> rt;
534  bits<21> addr;
535
536  bits<32> Inst;
537
538  let Inst{31-26} = op;
539  let Inst{25-21} = addr{20-16};
540  let Inst{20-16} = rt;
541  let Inst{15-0}  = addr{15-0};
542}
543
544class MADDS_FM<bits<3> funct, bits<3> fmt> {
545  bits<5> fd;
546  bits<5> fr;
547  bits<5> fs;
548  bits<5> ft;
549
550  bits<32> Inst;
551
552  let Inst{31-26} = 0x13;
553  let Inst{25-21} = fr;
554  let Inst{20-16} = ft;
555  let Inst{15-11} = fs;
556  let Inst{10-6}  = fd;
557  let Inst{5-3}   = funct;
558  let Inst{2-0}   = fmt;
559}
560
561class LWXC1_FM<bits<6> funct> {
562  bits<5> fd;
563  bits<5> base;
564  bits<5> index;
565
566  bits<32> Inst;
567
568  let Inst{31-26} = 0x13;
569  let Inst{25-21} = base;
570  let Inst{20-16} = index;
571  let Inst{15-11} = 0;
572  let Inst{10-6}  = fd;
573  let Inst{5-0}   = funct;
574}
575
576class SWXC1_FM<bits<6> funct> {
577  bits<5> fs;
578  bits<5> base;
579  bits<5> index;
580
581  bits<32> Inst;
582
583  let Inst{31-26} = 0x13;
584  let Inst{25-21} = base;
585  let Inst{20-16} = index;
586  let Inst{15-11} = fs;
587  let Inst{10-6}  = 0;
588  let Inst{5-0}   = funct;
589}
590
591class BC1F_FM<bit nd, bit tf> {
592  bits<16> offset;
593
594  bits<32> Inst;
595
596  let Inst{31-26} = 0x11;
597  let Inst{25-21} = 0x8;
598  let Inst{20-18} = 0; // cc
599  let Inst{17} = nd;
600  let Inst{16} = tf;
601  let Inst{15-0} = offset;
602}
603
604class CEQS_FM<bits<5> fmt> {
605  bits<5> fs;
606  bits<5> ft;
607  bits<4> cond;
608
609  bits<32> Inst;
610
611  let Inst{31-26} = 0x11;
612  let Inst{25-21} = fmt;
613  let Inst{20-16} = ft;
614  let Inst{15-11} = fs;
615  let Inst{10-8} = 0; // cc
616  let Inst{7-4} = 0x3;
617  let Inst{3-0} = cond;
618}
619
620class CMov_I_F_FM<bits<6> funct, bits<5> fmt> {
621  bits<5> fd;
622  bits<5> fs;
623  bits<5> rt;
624
625  bits<32> Inst;
626
627  let Inst{31-26} = 0x11;
628  let Inst{25-21} = fmt;
629  let Inst{20-16} = rt;
630  let Inst{15-11} = fs;
631  let Inst{10-6} = fd;
632  let Inst{5-0} = funct;
633}
634
635class CMov_F_I_FM<bit tf> {
636  bits<5> rd;
637  bits<5> rs;
638
639  bits<32> Inst;
640
641  let Inst{31-26} = 0;
642  let Inst{25-21} = rs;
643  let Inst{20-18} = 0; // cc
644  let Inst{17} = 0;
645  let Inst{16} = tf;
646  let Inst{15-11} = rd;
647  let Inst{10-6} = 0;
648  let Inst{5-0} = 1;
649}
650
651class CMov_F_F_FM<bits<5> fmt, bit tf> {
652  bits<5> fd;
653  bits<5> fs;
654
655  bits<32> Inst;
656
657  let Inst{31-26} = 0x11;
658  let Inst{25-21} = fmt;
659  let Inst{20-18} = 0; // cc
660  let Inst{17} = 0;
661  let Inst{16} = tf;
662  let Inst{15-11} = fs;
663  let Inst{10-6} = fd;
664  let Inst{5-0} = 0x11;
665}
666